JP4583678B2 - Semiconductor device manufacturing method and semiconductor device cleaning solution - Google Patents

Description

【００５９】
次に、表１に示したリン酸アンモニウムを使用した場合において薬液に添加されるシュウ酸を０（重量％）wt％として変質物の除去を調べたところ、表２に示すように、第１の銅配線１１の表面には腐食は発生しなかったが、１万個のビアについてのチェーンコンタクト不良率は悪くなった。即ち、これは、シュウ酸、即ち補助剤が無い場合にはビアホール１２ａ内周面でエッチングガスに起因するフロロカーボン系の生成物が除去され難くなってコンタクト不良率の上昇を招いていると考えられる。
【００６０】
【表２】

【００６１】
次に、リン酸アンモニウムとシュウ酸と水を混合して洗浄薬液を作成した場合に、それらの混合比（wt％）を変えたところ、表３、表４に示すような結果が得られた。
【００６２】
【表３】

【００６３】
【表４】

【００６４】
表３のＡ〜Ｄにおいて、シュウ酸の組成比を１wt％として水とリン酸アンモニウムの組成比を変えたところ、水の組成比が５０〜９０％では洗浄薬液の処理能力には違いがないことがわかった。
【００６５】
表４において、リン酸アンモニウムの組成比を４９wt％とし、水の組成比を５０wt％以上として、シュウ酸の組成比を変えたところ、０．５wt％よりも小さくなるほどコンタクト不良率が僅かであるが上昇した。また、シュウ酸の組成比を０．０１wtより小さくすると、第１の銅配線１１の表面の腐食が増えた。そこでシュウ酸の組成比を０．１wt％として水の組成比を９９％又は９９．５％にしたところ、水の組成比を９９％よりも増やすことは好ましくないことがわかった。
【００６６】
また、ビアホール１２ａから露出した第１の銅配線１１が必要以上に薬液中に溶出することを抑制するためには、薬液中の水素イオン濃度を１０^-5mol/liter 以上、即ちｐＨ５以下にすることが好ましい。薬液中での純銅の溶出を防止するためには、シュウ酸濃度が５wt％を超えないようにすることが好ましい。
【００６７】
従って、コンタクト不良率の低減と薬液中への銅の溶出抑制を考慮すると、シュウ酸の組成比を０．０１〜５．０wt％以上にし、水の組成比を５０〜９９％にし、さらに、リン酸アンモニウムの組成比を０．９wt％以上にすることにより、コンタクト不良率を充分に低くできるし、銅配線１１の腐食は生じなかった。
【００６８】
次に、リン酸アンモニウムとシュウ酸と水からなる洗浄液を使用してビアホール１２ａ内を洗浄する際の薬液温度（洗浄温度）の好ましい範囲は、水の温度特性から氷点以上沸点以下である必要がある。例えば洗浄薬液を１００℃に設定すると薬液中の水の組成が減少してしまう。また、表５に示すように、洗浄薬液の温度を２０℃より低くすると、コンタクト不良率が増えることがわかった。従って、ビアホール１２ａや配線用溝１２ｂの洗浄時の洗浄液の温度を２０〜８０℃に設定することが好ましい。
【００６９】
【表５】

【００７０】
ところで、銅層や絶縁膜に対する薬液の濡れ性を向上するために、次のような添加剤を薬液に添加してもよい。
【００７１】
例えば、硫酸エステルのアンモニウム塩、又は、硫酸エステルの第１アミン塩、第二アミン塩若しくは第三アミン塩がある。硫酸エステルとしては、C₁₂H₂₅O(CH₂CH₂O)₄SO₃H 、C₁₂H₂₅O(CH₂CH₂O)₂SO₃H などのアルキル硫酸エステル類、又は、C₉H₁₉PhO₂(CH₂CH₂O)₄SO₃H 等のアルキルフェノール硫酸エステル類がある。その他の添加剤として、C₈H₁₇N(CH₃)₃Br又はC₁₂H₂₅N(C₂H₅)(CH₃)₂Br がある。これらの添加剤は、リサイクル性が良い。
【００７２】
その他に、アニオン系又はカチオン系の第２の界面活性剤を添加剤として洗浄用薬液に添加してもよい。そのような界面活性剤として、例えば硫酸エステルのアンモニウム塩、又は、硫酸エステルの第１アミン塩、第二アミン塩若しくは第三アミン塩がある。
【００７３】
また、ビアホールから露出する第１の銅配線１１の表面を保護するために、洗浄用薬液にインヒビタ（腐食抑制剤）を添加してもよい。インヒビタとして、有機スルホン酸とその誘導体、第４アンモニウム塩、ベンゾトリアゾールなどがある。インヒビタは、ビアホール内の洗浄後に純水などによって除去される。
（第２の実施の形態）
第１実施形態では、第４の層間絶縁膜１２にビアホール１２ａを形成した後に有機酸アンモニウムを含む薬液によりビアホール１２ａ内を洗浄し、さらに第４の層間絶縁膜１２に配線用溝１２ｂを形成した後に有機酸アンモニウムを含む薬液により配線用溝１２ｂ及びビアホール１２ａを洗浄するというように、有機酸アンモニウム含有薬液を使用して２回の洗浄を行っている。
【００７４】
これは、図４(b) に示した最初の薬液洗浄を省略すると、ビアホール１２ａの内面に残った反応生成物１４がエッチングマスクとして機能するので、配線用溝１２ｂの形成のために第４の層間絶縁膜１２の上部をエッチングした後に、配線用溝１２ｂの中であってビアホール１２ａの直上に部分的に層間絶縁膜１２が残ることがあるからである。
【００７５】
そこで次に、ビアホール内と配線用溝内に付着した反応生成物を１回の酸アンモニウム塩含有薬液処理によって除去できるデュアルダマシン法について説明する。
【００７６】
まず、第１実施形態と同様な工程によって、シリコン基板１の上方に第１の銅配線１１を形成する。
【００７７】
続いて、図１１(a) に示すように、第１の銅配線１１と第３層間絶縁膜１０の上に、第４層間絶縁膜３１の下部層３２として膜厚２５０ｎｍのSiO₂膜を形成し、さらに下部層３２の上に中間層３３として膜厚１００ｎｍのSi₃N₄ 膜を形成する。 次に、図１１(b) に示すように、中間層３３上にレジスト３６を塗布し、これを露光、現像してビア形成用の開口３６ａを形成する。続いて、レジスト３６の開口３６ａを通して中間層３３を選択的にエッチングしてビアホール３１ａの上部を形成する。この後にレジスト３６を酸素プラズマによってアッシングして除去する。この場合、第１の銅配線１１が露出していないのでアッシングの際に酸化銅等の変質物が第１の銅配線１１上面に付着することはない。ここで、従来方法で洗浄を行う。なお、ビアホール３１ａの上部にエッチング反応生成物が付着し、これが残っても問題はない。
【００７８】
次に、図１２(a) に示すように、第４層間絶縁膜３１の中間層３３及び下部層３２の上に、上部層３４として膜厚２５０ｎｍのSiO₂膜を形成する。なお、中間層３３は、下層部３２と上層部３４に対して互いに選択的にエッチングできるような異種の絶縁材料から形成される。さらに、上部層３４の上にレジスト３７を塗布し、これを露光、現像して配線形状の開口３７ａを形成する。その配線形状はビアホール３１ａの上方を通る形状である。
【００７９】
そして、図１２(b) に示すように、レジスト３７をマスクにして上部層３４をエッチングするとともに、中間層３３のビアホール３１ａを通して下部層２１をエッチングする。この場合のエッチングは例えば反応性イオンエッチング法を用い、エッチングガスとしてCF₄ 、C₄F₈などを使用する。
【００８０】
これにより第４層間絶縁膜３１の上部層３４には第２の配線用溝３１ｂが形成され、また、下層部２１にはビアホール３１ａの下部が形成される。そして、ビアホール３１ａから第１の銅配線１１の上面が露出することになる。
【００８１】
このエッチングにより、異物３８であるエッチング生成物が第２の配線用溝３１ｂの側壁とビアホール３１ａの側壁に付着する。
【００８２】
さらに、図１３(a) に示すように、第４層間絶縁膜３１上のレジスト３７を酸素プラズマによってアッシングして除去する。このアッシングにより、異物３８であるアッシング生成物が第２の配線用溝３１ｂの側壁とビアホール３１ａの側壁に付着するとともに、第１の銅配線１１の上面が酸化されて酸化銅１１ｅが形成される。また、第１の銅配線１１の上にはエッチング生成物、アッシング生成物などの変質物が付着することもある。
【００８３】
次に、薬液（洗浄剤）として無機又は有機酸アンモニウム塩、例えばリン酸アンモニウムを用いてビアホール３１ａと第２の配線用溝３１ｂと第４の層間絶縁膜３１を洗浄し、これによりビアホール３１ａ内と第２の配線用溝３１ｂ内の異物３８を除去するとともに、第１の銅配線１１の表面の酸化１１ｅ銅を除去する。これにより、ビアホール３１ａからは第１の銅配線１１の純銅が露出する。リン酸アンモニウム塩を用いる洗浄の条件は第１実施形態と同じであるので、その詳細は省略する。
【００８４】
次に、図１３(b) に示すように、ビアホール３１ａ内面と第２の配線用溝内面と第４層間絶縁膜２１上面に、バリアメタル層３９として窒化チタン膜をスパッタにより形成する。さらに、バリアメタル層３９上に第１実施形態と同様な方法により銅層４０を形成する。
【００８５】
この後、第４層間絶縁膜３１上の銅層４０とバリアメタル層３９をＣＭＰ法により除去する。そして、ビアホール３１ａ内に残された金属膜をビア４１とし、第２の配線用溝３１ｂ内に残された金属膜を第２の銅配線４２として使用する。
【００８６】
この後に、同じような工程により多層の銅配線を形成する。
【００８７】
本実施形態によれば、酸アンモニウム塩を用いる１回の薬液処理によってビアホール３１ａと第１の配線用溝３１ｂと第１の銅配線１１の洗浄を同時に行うことができる。
【００８８】
なお、上記した実施形態では、ビアホールの中とその上の配線用溝の中に同時に銅を埋め込むというデュアルダマシンについて説明したが、ビアホールの中と配線用溝の中を別々な工程で銅を埋め込むというシングルダマシンの工程においても、ビアホール内と配線用溝を別々に酸アンモニウム塩を用いる洗浄を行ってもよい。
【００８９】
また、上記した実施形態では、層間絶縁膜にビアホール又は配線用溝を形成するためにレジストを用いたが、窒化シリコンよりなるハードマスクを用いてもよい。この場合でも、ハードマスク除去時にビアホールの底に堆積した異物を酸アンモニウム塩を用いて除去することができる。
【００９０】
さらに、上記した実施形態では、ビアホール又は配線用溝内に銅を埋め込んでビア又は配線を形成しているが、その他の金属、例えば銅合金、タングステン、タングステン合金、アルミニウム、アルミニウム合金を埋め込んでビア又は金属配線を形成してもよい。そのようなビア又は金属配線の形成工程においても、上記実施形態で使用した洗浄液によるホール、溝及び金属配線表面の洗浄効果を奏する。
（付記１）半導体基板の上方に第１絶縁膜を形成する工程と、
第１絶縁膜上に第１金属配線を形成する工程と、
前記第１金属配線及び前記第１絶縁膜上に第２絶縁膜を形成する工程と、
開口を有するマスクを前記第２絶縁膜上に形成する工程と、
前記開口を通して前記第２絶縁膜をエッチングしてホールと溝の少なくとも一方を形成する工程と、
前記マスクを除去する工程と、
前記ホールと前記溝の少なくとも一方の中に付着した異物を酸アンモニウム塩を含む洗浄液によって除去すると同時に前記ホールと前記溝の少なくとも一方から露出した前記第１金属配線の表面の酸化物を除去する工程と、
前記ホールと前記溝の少なくとも一方に金属を埋め込む工程と
を有することを特徴とする半導体装置の製造方法。
（付記２）前記洗浄液には補助剤としてカルボン酸類が添加されていることを特徴とする付記１に記載の半導体装置の製造方法。
（付記３）前記カルボン酸類は、シュウ酸、蟻酸、のいずれかであることを特徴とする付記２に記載の半導体装置の製造方法。
（付記４）前記洗浄液中の前記シュウ酸の濃度は、前記洗浄液の全体に対して０．０１重量％以上且つ５．０重量％以下であることを特徴とする付記３に記載の半導体装置の製造方法。
（付記５）前記酸アンモニウム塩は、硫酸アンモニウム、酢酸アンモニウム、クエン酸アンモニウム、硝酸アンモニウム、コハク酸アンモニウム、フッ化アンモニウム、リン酸アンモニウムのいずれかであることを付記１に記載の半導体装置の製造方法。
（付記６）前記洗浄液には、アニオン系又はカチオン系の界面活性剤が添加されていることを特徴とする付記１に記載の半導体装置の製造方法。
（付記７）前記洗浄液には、前記第１金属配線の腐食を抑制するためのインヒビタが添加されていることを特徴とする付記１に記載の半導体装置の製造方法。
（付記８）前記洗浄液の水素イオン濃度が１０^-5mol/liter 以上であることを特徴とする付記１乃至付記７のいずれかに記載の半導体装置の製造方法。
（付記９）前記洗浄液中の水分含有率が５０〜９９重量％であることを特徴とする付記１乃至付記７のいずれかに記載の半導体装置の製造方法。
（付記１０）前記洗浄液の温度は２０℃以上で８０℃以下の範囲に設定されることを特徴とする付記１乃至付記７のいずれかに記載の半導体装置の製造方法。
（付記１１）前記ホールと前記溝は、連続して形成されることを特徴とする付記１に記載の半導体装置の製造方法。
（付記１２）前記ホールと前記溝の少なくとも一方に埋め込まれる金属は、タングステン、タングステン合金、アルミニウム、アルミニウム合金、銅又は銅合金のいずれかであることを特徴とする付記１乃至付記１１のいずれかに記載の半導体装置の製造方法。
（付記１３）前記溝内に埋め込まれた金属によって第２金属配線が形成されることを特徴とする付記１又は付記１２に記載の半導体装置の製造方法。
（付記１４）前記マスクはレジストマスク又はハードマスクであって、除去時にはドライ処理がなされることを特徴とする付記１に記載の半導体装置の製造方法。
（付記１５）酸アンモニウム塩とカルボン酸類が添加されていることを特徴とする半導体装置用洗浄液。
（付記１６）前記カルボン酸類は、シュウ酸、蟻酸、酢酸、コハク酸、クエン酸のいずれかであることを特徴とする付記１５に記載の半導体装置用洗浄液。
（付記１７）前記洗浄液中の前記シュウ酸の濃度は、前記洗浄液の全体に対して０．０１重量％以上且つ５．０重量％以下であることを特徴とする付記１６に記載の半導体装置用洗浄液。
（付記１８）前記酸アンモニウム塩は、硫酸アンモニウム、酢酸アンモニウム、クエン酸アンモニウム、硝酸アンモニウム、コハク酸アンモニウム、フッ化アンモニウム、リン酸アンモニウムのいずれかであることを特徴とする付記１５に記載の半導体装置用洗浄液。
（付記１９）前記洗浄液の水素イオン濃度が１０^-5mol/liter 以上であることを特徴とする付記１５に記載の半導体装置用洗浄液。
（付記２０）前記洗浄液中の水分含有率が５０〜９９重量％であることを特徴とする付記１５に記載の半導体装置用洗浄液。
【００９１】
前記酸アンモニウム塩は、有機酸アンモニウム塩、又は無機酸アンモニウム塩であることを特徴とする付記１乃至付記２１のいずれかに記載の半導体装置の製造方法又は半導体装置用洗浄液。
【００９２】
【発明の効果】
以上述べたように本発明によれば、有機アンモニウム塩含有洗浄液によってエッチング反応生成物、アッシング反応生成物、金属酸化物等を同時に除去するようにしたので、フォトリソグラフィー法により絶縁膜に形成されたホール内又は溝内の洗浄能力や金属膜表面の洗浄能力が高くなり、その洗浄時間を従来に比べて大幅に短縮することができる。
【００９３】
これにより、半導体装置の製造工程のスループットを向上させ、反応生成物、変質物等の異物によるコンタクトプラグ、ビア及び配線の抵抗の上昇を抑制し、金属パターンの上下間の接続を良好にすることが可能になる。
【図面の簡単な説明】
【図１】図１(a) 〜(d) は、従来の半導体装置における銅配線の製造工程を示す断面図である。
【図２】図２(a),(b) は、本発明の第１実施形態に係る半導体装置の製造工程を示す断面図（その１）である。
【図３】図３(a),(b) は、本発明の第１実施形態に係る半導体装置の製造工程を示す断面図（その２）である。
【図４】図４(a),(b) は、本発明の第１実施形態に係る半導体装置の製造工程を示す断面図（その３）である。
【図５】図５(a),(b) は、本発明の第１実施形態に係る半導体装置の製造工程を示す断面図（その４）である。
【図６】図６(a),(b) は、本発明の第１実施形態に係る半導体装置の製造工程を示す断面図（その５）である。
【図７】図７(a),(b) は、本発明の第１実施形態に係る半導体装置の製造工程を示す断面図（その６）である。
【図８】図８は、本発明の実施形態に用いられる洗浄装置の一例を示す構成図である。
【図９】図９は、レジスト除去後の露出銅表面の本発明の実施形態に係る洗浄液による洗浄時間と表面状態との関係を示す図である。
【図１０】図１０は、レジスト除去後の露出銅表面の従来例のアミン系洗浄液による洗浄時間と表面状態との関係を示す図である。
【図１１】図１１(a),(b) は、本発明の第２実施形態に係る半導体装置の製造工程を示す断面図（その１）である。
【図１２】図１２(a),(b) は、本発明の第２実施形態に係る半導体装置の製造工程を示す断面図（その２）である。
【図１３】図１３(a),(b) は、本発明の第２実施形態に係る半導体装置の製造工程を示す断面図（その３）である。
【図１４】図１４(a),(b) は、本発明の第２実施形態に係る半導体装置の製造工程を示す断面図（その４）である。
【符号の説明】
１…シリコン基板、２…素子分離絶縁層、３…ＭＯＳトランジスタ、４，８，１０，１２…層間絶縁膜、５ａ，５ｂ，９…導電性プラグ、７…配線、１１…第１の銅（金属）配線、１１ｄ，１１ｅ…酸化銅、１２ａ…ビアホール、１２ｂ…配線用溝、１３…レジスト、１４…異物、１５…レジスト、１６…異物、１７ａ，３９…バリアメタル層、１７ｂ，４０…銅層、１８，４１…ビア、１９，４２…第２の銅（金属）配線、３１…層間絶縁膜、、３１ａ…ビアホール、３１ｂ…配線用溝３２…下部層、３３…中間層、３４…上部層、３６，３７…レジスト、３８…異物。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device manufacturing method and a semiconductor device cleaning liquid, and more particularly to a semiconductor device manufacturing method including a cleaning process and a cleaning liquid used in the semiconductor device manufacturing process.
[0002]
[Prior art]
Semiconductor devices are being miniaturized for higher speed and higher performance. The miniaturization has been developed not only for element parts such as transistors that affect device performance, but also for wiring structures.
[0003]
In recent years, attention has been paid to the formation of wiring by a damascene technique as a technique for realizing high-speed semiconductor devices. The damascene technology includes dual damascene and single damascene, both of which have a step of filling copper in the wiring trench or hole after forming the wiring trench or hole in the insulating film. Dual damascene has a process of filling copper in a hole and a wiring groove at the same time. Single damascene has a step of filling copper separately in the hole and the wiring groove.
[0004]
In order to form a fine pattern such as a wiring groove or a hole in an insulating film by dry etching using a resist pattern or a hard mask pattern as a mask, the mask pattern is made finer and more anisotropic. High etching is required. The etching amount of the insulating film increases as the wiring density increases.
[0005]
By the way, after the insulating film is etched to form the wiring groove or hole, foreign matter accumulates in the wiring groove or hole. The foreign matter is generated by the complex reaction of the insulating film component, the mask component, the etching gas component, etc. once removed by etching. Along with the miniaturization and high density of wiring, after dry etching and mask pattern removal, a large amount of reaction products adhere in the wiring trenches and via holes, respectively.
[0006]
Cleaning solutions are used to remove such reaction products from the trenches and via holes. However, with the miniaturization of vias and wirings, conventional cleaning solutions cannot be removed sufficiently.
[0007]
Next, a process of forming wirings and vias by dual damascene will be described.
[0008]
First, steps required until a structure shown in FIG.
[0009]
An interlayer insulating film 102 is formed above the silicon substrate 101, and a first silicon oxide film 103 is further formed on the interlayer insulating film 102. Subsequently, a first wiring groove 103a is formed in the first silicon oxide film 103, and a first barrier layer 104a and a first copper layer 104b are sequentially formed in the first wiring groove 103a. 104 is formed. The first barrier layer 104a and the first copper layer 104b on the first silicon oxide film 103 are removed by a chemical mechanical polishing (CMP) method. Further, a second silicon oxide film 105 is formed on the first copper wiring 104 and the first silicon oxide film 103 by the CVD method. Subsequently, a resist 108 having a via forming opening 108 a above the first copper wiring 104 is formed on the second silicon oxide film 105.
[0010]
Further, as shown in FIG. 1B, the second silicon oxide film 105 is etched through the opening 108a of the resist 108. As a result, a via hole 105 a is formed in the second silicon oxide film 105.
[0011]
Next, the resist 108 is removed by exposing the resist 108 to a plasma atmosphere of a gas containing oxygen.
[0012]
As shown in FIGS. 1B and 1C, the inner peripheral surface of the via hole 105a after removing the resist 108 and the upper surface of the first copper wiring exposed from the via hole 105a are etched and removed. The foreign substance 109 produced by the reaction adheres. Further, a copper oxide 104c is formed in a portion of the first copper wiring 104 exposed from the via hole 105a.
[0013]
Such foreign matters and copper oxide 104c are removed by a predetermined cleaning liquid, for example, an amine-based organic cleaning liquid such as normal ethyl ether amine.
[0014]
Next, as shown in FIG. 1D, after the second wiring groove 105b is formed on the second silicon oxide film 105, the second barrier metal layer 110a is formed in the second wiring groove 105b and the via hole 105a. By burying the second copper layer 110b, a second copper wiring is formed in the second wiring groove 105b, and a contact via is formed in the via hole 105a. The second barrier metal layer 110a and the second copper layer 110b on the second silicon oxide film 105 are removed by the CMP method. Thereby, the copper wiring of a multilayer structure is obtained.
[0015]
[Problems to be solved by the invention]
By the way, the surface of the first copper wiring 104 exposed from the bottom of the via hole 105a is oxidized by oxygen plasma used for removing the resist 108 to form an oxide 104c.
It was confirmed that the oxide 104c was dissolved in the above-described amine cleaning solution and the pure copper of the first copper wiring 104 was exposed.
[0016]
However, it was confirmed that the amine-based cleaning liquid has a low ability to remove the foreign matter 109 generated during etching and resist removal. That is, if an amine-based cleaning solution is used to remove foreign matter 109 generated during etching or resist removal, it takes a long time to sufficiently remove foreign matter, resulting in poor throughput. The improvement in throughput is important for shortening the cleaning time per sheet, particularly when a single wafer cleaning apparatus is used.
[0017]
Also resist 108 In the case where a hard mask is used instead of the above, it has been confirmed that the foreign matter deposited on the bottom of the via hole 105a when the hard mask is removed cannot be removed with an amine-based cleaning agent.
[0018]
As described above, foreign matter adhering to holes and wiring grooves sufficient If a metal plug is formed in the hole or embedded in the wiring groove without being removed, the rate of occurrence of poor connection between the metal plug and the metal wiring increases, the resistance of the metal plug or the resistance of the metal wiring Inconveniences such that each becomes higher than the design value.
[0019]
An object of the present invention is to improve the throughput of removing foreign matter in a hole or wiring groove attached during etching or resist removal, and to remove the oxide film on the lower wiring surface exposed from the hole or wiring groove. And a semiconductor device cleaning solution for use in such a cleaning process.
[0020]
[Means for Solving the Problems]
The above-described problems include a step of forming a first insulating film above a semiconductor substrate, a step of forming a first metal wiring on the first insulating film, and a step of forming a first metal wiring on the first metal wiring and the first insulating film. A step of forming two insulating films, a step of forming a mask having an opening on the second insulating film, a step of etching the second insulating film through the opening to form at least one of a hole and a groove, Removing the mask, and removing foreign matter adhering in at least one of the hole and the groove. Ammonium phosphate and carboxylic acids And removing the oxide on the surface of the first metal wiring exposed from at least one of the hole and the groove and embedding a metal in at least one of the hole and the groove. This is solved by a method for manufacturing a semiconductor device.
[0021]
The above-mentioned issues Ammonium phosphate And a carboxylic acid added to the semiconductor device.
[0022]
According to the present invention, the etching reaction product, the ashing reaction product, the metal oxide and the like are simultaneously removed by the acid ammonium salt-containing cleaning liquid.
[0023]
Such a cleaning solution is excellent in the cleaning capability in the hole or groove formed in the insulating film or the cleaning capability of the metal film surface, and the cleaning time is about 1 minute, for example, which is significantly shorter than the conventional one. This improves the throughput of the manufacturing process of the semiconductor device, suppresses the increase in resistance of contact plugs, vias and wiring due to foreign substances such as reaction products and altered substances, and improves the connection between the upper and lower sides of the metal pattern. Can do.
[0024]
Such a cleaning liquid preferably contains an acid ammonium salt as a main agent, and carboxylic acids are added as an auxiliary agent. Acid ammonium salts include organic acid ammonium salts and inorganic acid ammonium salts.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
2 to 7 are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the second embodiment of the present invention.
[0026]
First, steps required until the structure shown in FIG.
[0027]
An element isolation insulating layer 2 surrounding an active element region is formed on a p-type silicon (semiconductor) substrate 1 by a LOCOS method. The element isolation insulating layer 2 may have an STI structure formed by embedding an insulating film in silicon. Subsequently, the MOS transistor 3 is formed in the active element region.
[0028]
In the MOS transistor 3, a gate electrode 3b is formed on a silicon substrate 1 with a gate insulating film 3a interposed therebetween, and impurities are introduced into the silicon substrate 1 on both sides of the gate electrode 3b to thereby form first and second n-type impurity diffusions. It is formed by the step of forming the layers 3c and 3d. An insulating sidewall 3e is formed on the side surface of the gate electrode 3b.
[0029]
Further, by introducing impurities into the silicon substrate 1 using the gate electrode 3b and the insulating sidewall 3e as a mask, the n-type impurity diffusion layers 3c and 3d have an LDD structure.
[0030]
Next, SiO covering the MOS transistor 3 ₂ A first interlayer insulating film 4 is formed on the silicon substrate 1. Further, by patterning the first interlayer insulating film 4, the first contact hole 4a and the second contact are formed on the first n-type impurity diffusion layer 3c and the second n-type impurity diffusion layer 3d, respectively. Hole 4b is formed.
[0031]
Subsequently, a first conductive plug 5a and a second conductive plug 5b are formed in the first and second contact holes 4a and 4b, respectively. The first and second conductive plugs 5a and 5b have a two-layer structure of a titanium nitride film and a tungsten film, respectively.
[0032]
Next, a first layer wiring 7 made of aluminum connected to the second conductive plug 5 b is formed on the first interlayer insulating film 4. Subsequently, SiO 2 is formed on the first interlayer insulating film 4 and the first-layer wiring 7. ₂ A second interlayer insulating film 8 made of BPSG, PSG or the like is formed by a CVD method. Further, a third contact hole 8a is formed on the first conductive plug 5a in the second interlayer insulating film 8, and a conductive plug 9 having a two-layer structure of a titanium nitride film and a tungsten film is formed therein. Embed.
[0033]
After that, on the second interlayer insulating film 8 and the conductive plug 9, a third interlayer insulating film 10 is formed of SiO. ₂ A film is formed by a CVD method.
[0034]
Subsequently, the third interlayer insulating film 10 is patterned by a photolithography method to form a wiring trench 10. The wiring groove 10 has a planar shape partially overlapping the upper conductive plug 9.
[0035]
Next, as shown in FIG. 2B, a barrier metal layer 11a and a copper layer 11b are sequentially formed in the wiring trench 10a and on the third interlayer insulating film 10 by sputtering. For example, titanium nitride is formed as the barrier metal layer 11a.
[0036]
Further, the barrier metal layer 11a and the copper layer 11b on the third interlayer insulating film 10 are removed by a CMP method. As a result, the barrier metal layer 11 a and the copper layer 11 b embedded in the wiring trench 10 are used as the first copper wiring 11.
[0037]
Next, as shown in FIG. 3 (a), a 500-nm-thick SiO2 film is formed as a fourth interlayer insulating film 12 on the first copper wiring 11 and the third interlayer insulating film 10. ₂ A film is formed by a CVD method. Further, a resist 13 is applied on the fourth interlayer insulating film 13, and exposed and developed to form a via hole forming window 13 a on the first copper wiring 11.
[0038]
Subsequently, as shown in FIG. 3B, the fourth interlayer insulating film 12 is etched by a reactive ion etching method until the first copper wiring 11 is exposed through the window 13a of the resist 13. In this case, CF as the etching gas _Four , C _Four F ₈ Etc. By this etching, a via hole 12a is formed in the fourth interlayer insulating film 12, and an etching product as the foreign matter 14 adheres to the side wall of the via hole 12a.
[0039]
Thereafter, as shown in FIG. 4A, the silicon substrate 1 is placed in a plasma atmosphere containing oxygen, and the resist 12 is ashed by oxygen plasma. In this case, the surface of the first copper wiring 11 exposed from the via hole 12a is oxidized to form the copper oxide 11c, and the ashing product as the foreign matter 14 adheres in the via hole 12a.
[0040]
Next, the inside of the via hole 12a and the fourth interlayer insulating film 12 are cleaned using an inorganic or organic acid ammonium salt such as ammonium phosphate as a chemical solution (cleaning agent), thereby removing the foreign matter 14 in the via hole 12a. At the same time, the copper oxide 11c on the surface of the first copper wiring 11 is removed through the via hole 12a. As a result, the pure copper of the first copper wiring 11 is exposed from the via hole 12a. For example, carboxylic acids are added to such a chemical solution as an auxiliary agent. Examples of carboxylic acids include oxalic acid, formic acid, acetic acid, citric acid, succinic acid, and the like.
[0041]
For such cleaning, for example, a single wafer cleaning apparatus as shown in FIG. 8 is used. In FIG. 8, the silicon substrate 1 having the structure shown in FIG. Then, the silicon substrate 1 is transferred from the cleaning standby chamber 21 into the wet station 22 and placed on the turntable 23 therein. Then, the ammonium salt-containing cleaning is performed from the liquid supply spray 24 attached to the ceiling of the wet station 22 toward the cleaning target (that is, the fourth interlayer insulating film 12 and the via hole 12a) existing on the rotating turntable 23. Spray the agent. Then, after the cleaning of the object to be cleaned is finished and pure water is sprayed from the liquid supply spray 24 to remove the cleaning agent, the turntable 23 is stopped from rotating and the silicon substrate 1 thereon is transported into the drying module 25. After the silicon substrate 1 is dried, it is taken out.
[0042]
An example of such a single wafer cleaning apparatus is SR2000 (trade name) manufactured by Dainippon Screen. However, the cleaning apparatus is not limited to a single wafer type, and may be a batch type that processes a plurality of sheets simultaneously. As a batch type cleaning apparatus, for example, there is a WSST (trade name) manufactured by Semitool.
[0043]
After the cleaning of the via hole 12a as described above, as shown in FIG. 5A, a resist 15 is applied on the fourth interlayer insulating film 12, and this is exposed and developed, whereby the via hole 12a. A wiring-shaped opening 15a passing therethrough is formed.
[0044]
Thereafter, as shown in FIG. 5B, the second wiring trench 15a is formed by etching from the upper surface of the fourth interlayer insulating film 12 to a depth of 250 nm using the resist 15 as a mask. . At the time of this etching, the etching product as the foreign matter 16 adheres in the second wiring groove 15a.
[0045]
Further, as shown in FIG. 6A, the silicon substrate 1 is placed in a plasma atmosphere containing oxygen, and the resist 15 is ashed by oxygen plasma. In this case, the surface of the first copper wiring 11 exposed from the via hole 12a is oxidized to form copper oxide, and an ashing product as a foreign substance is formed in the second wiring groove 15a and the via hole 12a. Adhere to.
[0046]
Subsequently, as shown in FIG. 6B, the second wiring trench 15a, the via hole 12a, and the fourth interlayer insulating film 12 are cleaned by using an acid ammonium salt, for example, ammonium phosphate, as a chemical solution. The foreign matter in the second wiring groove 15a and the via hole 12a is removed, the copper oxide on the surface of the first copper wiring 11 is removed through the via hole 12a, and the chemical solution is removed with pure water. By removing the copper oxide, the pure copper of the first copper wiring 11 is exposed from the via hole 12a.
[0047]
For example, a carboxylic acid is preferably added to the chemical solution containing an acid ammonium salt as an auxiliary agent. For the cleaning, a single wafer type or batch type cleaning device as described above is used.
[0048]
Next, as shown in FIG. 7A, a nitride film having a thickness of, for example, 15 nm is formed as a conductive barrier metal layer 17a on the fourth interlayer insulating film 12, in the second wiring groove 15a, and in the via hole 12a. A titanium layer is formed by sputtering, and a second copper layer 17b having a thickness of 200 nm is formed on the barrier metal layer 17a. The copper layer 17b is formed through a process of growing copper on the copper seed layer by electrolytic plating after forming a copper seed having a film thickness of 30 to 100 nm using, for example, Cu (hfac) TMVS as a raw material.
[0049]
Thereafter, as shown in FIG. 7B, the barrier metal layer 17a and the copper layer 17b on the fourth interlayer insulating film 12 are removed by CMP. Thereby, the barrier metal layer 17a and the copper layer 17b left in the second wiring trench 12b are used as the second copper wiring 19, and the barrier metal layer 17a and the copper layer 17b left in the via hole 12a are Used as via 18.
[0050]
Thereafter, the upper copper wiring is formed by the same process as described above. Details thereof are omitted.
[0051]
Next, phosphoric acid as an acid ammonium salt is used to remove foreign substances such as etching products and ashing products adhering in the holes and wiring grooves formed in the interlayer insulating film and removing oxides on the upper surface of the copper wiring. A chemical solution containing ammonium and oxalic acid which is a carboxylic acid as an auxiliary will be described.
[0052]
FIG. 9 shows the results of examining the cleaning time and the ability to remove altered substances in the process of removing altered substances such as oxides on the upper surface of the first copper wiring 11 using such a chemical solution. FIG. 9 shows the surface state of the copper wiring 11 as it is after ashing the resist, and the surface of the copper wiring 11 after chemical treatment performed in 1 minute, 3 minutes, 5 minutes, 15 minutes or 30 minutes after ashing. It shows about the state. According to this, it was found that after one minute of cleaning with the chemical solution, the denatured material on the surface of the first copper wiring 11 was completely removed and pure copper was exposed.
[0053]
FIG. 10 shows the results of examining the cleaning time and the ability to remove the altered substance in the process of removing the altered substance on the surface of the first copper wiring 11 using an amine chemical solution that has been conventionally used as a cleaning agent. FIG. 10 shows the surface state of the copper wiring 11 as it is after ashing the resist, and the surface of the copper wiring 11 after chemical treatment performed in 1 minute, 3 minutes, 5 minutes, 15 minutes or 30 minutes after ashing. It shows about the state. According to this, it can be seen that the altered product requires a time of 30 minutes or more from the start of the amine chemical treatment.
[0054]
When FIG. 9 and FIG. 10 are compared, when the removal process of the altered substance is performed for 1 minute with the ammonium phosphate salt-containing chemical solution, compared to the case where the removal process of the altered substance is performed for 30 minutes with the amine chemical solution treatment, It can be seen that the ability to remove the altered material is excellent.
[0055]
By the way, as an acid ammonium salt, it is not restricted to use of the above-mentioned ammonium phosphate, You may use ammonium acetate, ammonium citrate, ammonium nitrate, ammonium succinate, ammonium fluoride, an ammonium sulfate salt, etc. The acid ammonium salt is an inorganic acid ammonium salt or an organic acid ammonium salt. Examples of inorganic acid ammonium salts include ammonium phosphate, ammonium sulfate, ammonium nitrate, and ammonium fluoride. Examples of organic acid ammonium salts include ammonium acetate, ammonium citrate, and ammonium succinate.
[0056]
However, even among acid ammonium salts, the ability to remove foreign substances and altered substances is different. For example, as shown in Table 1, ammonium phosphate has a higher ability to remove alterations than ammonium fluoride. Table 1 shows the corrosion state of the upper surface of the first copper wiring 11 after the chemical treatment in the state shown in FIG. 4 (b), and further shows the chain contact defect rate for 10,000 vias 12a. The result of the investigation is shown.
[0057]
In Table 1 and Tables 2 to 5 shown below, w represents the width of the via, L represents the depth of the via, and φ represents the diameter of the via.
[0058]
[Table 1]

[0059]
Next, when ammonium phosphate shown in Table 1 was used, removal of the denatured material was examined by setting oxalic acid added to the chemical solution to 0 (wt%) wt%. The surface of the copper wiring 11 was not corroded, but the chain contact defect rate for 10,000 vias deteriorated. That is, in the absence of oxalic acid, that is, an auxiliary agent, it is considered that the fluorocarbon-based product caused by the etching gas is difficult to be removed on the inner peripheral surface of the via hole 12a, leading to an increase in the contact failure rate. .
[0060]
[Table 2]

[0061]
Next, when a cleaning chemical solution was prepared by mixing ammonium phosphate, oxalic acid, and water, the mixing ratio (wt%) was changed, and the results shown in Tables 3 and 4 were obtained. .
[0062]
[Table 3]

[0063]
[Table 4]

[0064]
In Tables 3A to 3D, when the composition ratio of oxalic acid was set to 1 wt% and the composition ratio of water and ammonium phosphate was changed, the treatment capacity of the cleaning chemical solution was not different when the composition ratio of water was 50 to 90%. I understood it.
[0065]
In Table 4, when the composition ratio of ammonium phosphate was 49 wt%, the composition ratio of water was 50 wt% or more, and the composition ratio of oxalic acid was changed, the contact failure rate was smaller as it became smaller than 0.5 wt%. Rose. Further, when the composition ratio of oxalic acid was made smaller than 0.01 wt., The surface corrosion of the first copper wiring 11 increased. Therefore, when the composition ratio of oxalic acid was 0.1 wt% and the composition ratio of water was 99% or 99.5%, it was found that increasing the composition ratio of water beyond 99% was not preferable.
[0066]
In addition, in order to prevent the first copper wiring 11 exposed from the via hole 12a from eluting into the chemical more than necessary, the hydrogen ion concentration in the chemical is set to 10 ^-Five It is preferably at least mol / liter, that is, pH 5 or less. In order to prevent elution of pure copper in the chemical solution, it is preferable that the oxalic acid concentration does not exceed 5 wt%.
[0067]
Therefore, considering the reduction of the contact failure rate and the suppression of elution of copper into the chemical solution, the composition ratio of oxalic acid is 0.01 to 5.0 wt% or more, the composition ratio of water is 50 to 99%, By setting the composition ratio of ammonium phosphate to 0.9 wt% or more, the contact failure rate can be sufficiently reduced, and the copper wiring 11 is not corroded.
[0068]
Next, the preferable range of the chemical temperature (cleaning temperature) when cleaning the inside of the via hole 12a using a cleaning liquid composed of ammonium phosphate, oxalic acid and water needs to be a freezing point or higher and a boiling point or lower from the temperature characteristics of water. is there. For example, when the cleaning chemical solution is set to 100 ° C., the composition of water in the chemical solution decreases. Further, as shown in Table 5, it was found that the contact failure rate increased when the temperature of the cleaning chemical was lower than 20 ° C. Therefore, it is preferable to set the temperature of the cleaning liquid at the time of cleaning the via hole 12a and the wiring groove 12b to 20 to 80 ° C.
[0069]
[Table 5]

[0070]
By the way, in order to improve the wettability of the chemical solution with respect to the copper layer and the insulating film, the following additives may be added to the chemical solution.
[0071]
For example, an ammonium salt of a sulfate ester, or a primary amine salt, a secondary amine salt, or a tertiary amine salt of a sulfate ester. As sulfate ester, C ₁₂ H _{twenty five} O (CH ₂ CH ₂ O) _Four SO _Three H, C ₁₂ H _{twenty five} O (CH ₂ CH ₂ O) ₂ SO _Three Alkyl sulfates such as H or C ₉ H ₁₉ PhO ₂ (CH ₂ CH ₂ O) _Four SO _Three There are alkylphenol sulfates such as H. Other additives include C ₈ H ₁₇ N (CH _Three ) _Three Br or C ₁₂ H _{twenty five} N (C ₂ H _Five ) (CH _Three ) ₂ Br. These additives have good recyclability.
[0072]
In addition, an anionic or cationic second surfactant may be added to the cleaning chemical as an additive. Such surfactants include, for example, ammonium sulfate salts, or primary amine salts, secondary amine salts, or tertiary amine salts of sulfate esters.
[0073]
Further, an inhibitor (corrosion inhibitor) may be added to the cleaning chemical solution in order to protect the surface of the first copper wiring 11 exposed from the via hole. Inhibitors include organic sulfonic acids and their derivatives, quaternary ammonium salts, benzotriazoles, and the like. The inhibitor is removed by pure water or the like after cleaning the via hole.
(Second Embodiment)
In the first embodiment, after the via hole 12a is formed in the fourth interlayer insulating film 12, the inside of the via hole 12a is cleaned with a chemical solution containing organic acid ammonium, and the wiring groove 12b is formed in the fourth interlayer insulating film 12. The cleaning is performed twice using the organic acid ammonium-containing chemical solution so that the wiring groove 12b and the via hole 12a are later cleaned with a chemical solution containing the organic acid ammonium salt.
[0074]
If the first chemical cleaning shown in FIG. 4B is omitted, the reaction product 14 remaining on the inner surface of the via hole 12a functions as an etching mask, so that the fourth trench 12b is formed to form the wiring groove 12b. This is because after etching the upper portion of the interlayer insulating film 12, the interlayer insulating film 12 may partially remain in the wiring groove 12b and directly above the via hole 12a.
[0075]
Then, the dual damascene method which can remove the reaction product adhering to the inside of the via hole and the wiring groove by one chemical treatment with acid ammonium salt will be described.
[0076]
First, the first copper wiring 11 is formed above the silicon substrate 1 by the same process as in the first embodiment.
[0077]
Subsequently, as shown in FIG. 11A, an SiO layer having a thickness of 250 nm is formed as a lower layer 32 of the fourth interlayer insulating film 31 on the first copper wiring 11 and the third interlayer insulating film 10. ₂ A film is formed, and an Si layer having a film thickness of 100 nm is formed as an intermediate layer 33 on the lower layer 32. _Three N _Four A film is formed. Next, as shown in FIG. 11B, a resist 36 is applied on the intermediate layer 33, and this is exposed and developed to form an opening 36a for forming a via. Subsequently, the intermediate layer 33 is selectively etched through the opening 36a of the resist 36 to form the upper portion of the via hole 31a. Thereafter, the resist 36 is removed by ashing with oxygen plasma. In this case, since the first copper wiring 11 is not exposed, an altered material such as copper oxide does not adhere to the upper surface of the first copper wiring 11 during ashing. Here, cleaning is performed by a conventional method. An etching reaction product adheres to the upper portion of the via hole 31a, and there is no problem if it remains.
[0078]
Next, as shown in FIG. 12A, an SiO layer having a film thickness of 250 nm is formed as an upper layer 34 on the intermediate layer 33 and the lower layer 32 of the fourth interlayer insulating film 31. ₂ A film is formed. The intermediate layer 33 is formed of a different kind of insulating material that can be selectively etched with respect to the lower layer portion 32 and the upper layer portion 34. Further, a resist 37 is applied on the upper layer 34, and this is exposed and developed to form wiring-shaped openings 37a. The wiring shape is a shape passing over the via hole 31a.
[0079]
Then, as shown in FIG. 12B, the upper layer 34 is etched using the resist 37 as a mask, and the lower layer 21 is etched through the via hole 31a of the intermediate layer 33. In this case, for example, a reactive ion etching method is used, and CF as an etching gas _Four , C _Four F ₈ Etc.
[0080]
As a result, the second wiring trench 31 b is formed in the upper layer 34 of the fourth interlayer insulating film 31, and the lower portion of the via hole 31 a is formed in the lower layer portion 21. Then, the upper surface of the first copper wiring 11 is exposed from the via hole 31a.
[0081]
By this etching, the etching product as the foreign matter 38 adheres to the side wall of the second wiring groove 31b and the side wall of the via hole 31a.
[0082]
Further, as shown in FIG. 13A, the resist 37 on the fourth interlayer insulating film 31 is removed by ashing with oxygen plasma. By this ashing, the ashing product as the foreign matter 38 adheres to the side wall of the second wiring groove 31b and the side wall of the via hole 31a, and the upper surface of the first copper wiring 11 is oxidized to form copper oxide 11e. . In addition, an altered material such as an etching product or an ashing product may adhere on the first copper wiring 11.
[0083]
Next, the via hole 31a, the second wiring groove 31b, and the fourth interlayer insulating film 31 are cleaned using an inorganic or organic acid ammonium salt, for example, ammonium phosphate, as a chemical solution (cleaning agent), whereby the inside of the via hole 31a is cleaned. The foreign matter 38 in the second wiring groove 31b is removed, and the oxidized 11e copper on the surface of the first copper wiring 11 is removed. As a result, the pure copper of the first copper wiring 11 is exposed from the via hole 31a. Since the conditions for cleaning using the ammonium phosphate salt are the same as those in the first embodiment, the details thereof are omitted.
[0084]
Next, as shown in FIG. 13B, a titanium nitride film is formed as a barrier metal layer 39 on the inner surface of the via hole 31a, the second wiring groove inner surface, and the upper surface of the fourth interlayer insulating film 21 by sputtering. Further, the copper layer 40 is formed on the barrier metal layer 39 by the same method as in the first embodiment.
[0085]
Thereafter, the copper layer 40 and the barrier metal layer 39 on the fourth interlayer insulating film 31 are removed by the CMP method. The metal film left in the via hole 31a is used as the via 41, and the metal film left in the second wiring groove 31b is used as the second copper wiring.
[0086]
Thereafter, a multilayer copper wiring is formed by a similar process.
[0087]
According to the present embodiment, the cleaning of the via hole 31a, the first wiring groove 31b, and the first copper wiring 11 can be performed simultaneously by a single chemical treatment using an acid ammonium salt.
[0088]
In the above-described embodiment, the dual damascene process in which copper is simultaneously embedded in the via hole and in the wiring groove on the via hole is described. However, copper is embedded in the via hole and the wiring groove in separate steps. Also in the single damascene process, the inside of the via hole and the wiring groove may be separately cleaned using an acid ammonium salt.
[0089]
In the above-described embodiment, the resist is used to form the via hole or the wiring groove in the interlayer insulating film. However, a hard mask made of silicon nitride may be used. Even in this case, the foreign matter deposited on the bottom of the via hole when the hard mask is removed can be removed using an acid ammonium salt.
[0090]
Furthermore, in the above-described embodiment, vias or wirings are formed by embedding copper in via holes or wiring grooves, but vias are embedded by embedding other metals such as copper alloys, tungsten, tungsten alloys, aluminum, and aluminum alloys. Alternatively, a metal wiring may be formed. Also in the process of forming such vias or metal wirings, the cleaning effect of the holes, grooves and metal wiring surfaces by the cleaning liquid used in the above embodiment is exhibited.
(Appendix 1) forming a first insulating film above the semiconductor substrate;
Forming a first metal wiring on the first insulating film;
Forming a second insulating film on the first metal wiring and the first insulating film;
Forming a mask having an opening on the second insulating film;
Etching the second insulating film through the opening to form at least one of a hole and a groove;
Removing the mask;
Removing foreign matter adhering in at least one of the hole and the groove with a cleaning solution containing an ammonium acid salt and simultaneously removing oxide on the surface of the first metal wiring exposed from at least one of the hole and the groove; When,
Burying metal in at least one of the hole and the groove;
A method for manufacturing a semiconductor device, comprising:
(Supplementary note 2) The method of manufacturing a semiconductor device according to supplementary note 1, wherein a carboxylic acid is added as an auxiliary agent to the cleaning liquid.
(Additional remark 3) The said carboxylic acid is either oxalic acid or formic acid, The manufacturing method of the semiconductor device of Additional remark 2 characterized by the above-mentioned.
(Supplementary note 4) The concentration of the oxalic acid in the cleaning liquid is 0.01% by weight or more and 5.0% by weight or less with respect to the whole cleaning liquid. Production method.
(Supplementary note 5) The method for manufacturing a semiconductor device according to supplementary note 1, wherein the acid ammonium salt is any one of ammonium sulfate, ammonium acetate, ammonium citrate, ammonium nitrate, ammonium succinate, ammonium fluoride, and ammonium phosphate.
(Additional remark 6) The manufacturing method of the semiconductor device of Additional remark 1 characterized by adding an anionic or cationic surfactant to the said washing | cleaning liquid.
(Additional remark 7) The manufacturing method of the semiconductor device of Additional remark 1 characterized by adding the inhibitor for suppressing the corrosion of the said 1st metal wiring to the said washing | cleaning liquid.
(Appendix 8) The hydrogen ion concentration of the cleaning liquid is 10 ^-Five 8. The method for manufacturing a semiconductor device according to any one of appendix 1 to appendix 7, wherein the semiconductor device is mol / liter or more.
(Supplementary note 9) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 7, wherein a moisture content in the cleaning liquid is 50 to 99% by weight.
(Additional remark 10) The temperature of the said washing | cleaning liquid is set to the range of 20 to 80 degreeC, The manufacturing method of the semiconductor device in any one of Additional remark 1 thru | or 7 characterized by the above-mentioned.
(Additional remark 11) The said hole and the said groove | channel are formed continuously, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Supplementary note 12) Any one of Supplementary notes 1 to 11, wherein the metal embedded in at least one of the hole and the groove is any one of tungsten, a tungsten alloy, aluminum, an aluminum alloy, copper, or a copper alloy. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.
(Supplementary note 13) The method of manufacturing a semiconductor device according to supplementary note 1 or 12, wherein the second metal wiring is formed by the metal buried in the groove.
(Supplementary note 14) The method for manufacturing a semiconductor device according to supplementary note 1, wherein the mask is a resist mask or a hard mask, and is subjected to a dry process when removed.
(Supplementary note 15) A cleaning liquid for a semiconductor device, wherein an acid ammonium salt and a carboxylic acid are added.
(Supplementary note 16) The semiconductor device cleaning liquid according to supplementary note 15, wherein the carboxylic acid is any one of oxalic acid, formic acid, acetic acid, succinic acid, and citric acid.
(Supplementary note 17) The concentration of the oxalic acid in the cleaning liquid is 0.01% by weight or more and 5.0% by weight or less based on the whole cleaning liquid. Cleaning liquid.
(Supplementary note 18) The semiconductor device according to supplementary note 15, wherein the acid ammonium salt is any one of ammonium sulfate, ammonium acetate, ammonium citrate, ammonium nitrate, ammonium succinate, ammonium fluoride, and ammonium phosphate. Cleaning liquid.
(Supplementary note 19) The hydrogen ion concentration of the cleaning liquid is 10 ^-Five The cleaning liquid for semiconductor devices as set forth in appendix 15, wherein the cleaning liquid is mol / liter or more.
(Supplementary note 20) The semiconductor device cleaning liquid according to supplementary note 15, wherein a moisture content in the cleaning liquid is 50 to 99% by weight.
[0091]
22. The semiconductor device manufacturing method or semiconductor device cleaning solution according to any one of appendix 1 to appendix 21, wherein the acid ammonium salt is an organic acid ammonium salt or an inorganic acid ammonium salt.
[0092]
【The invention's effect】
As described above, according to the present invention, the etching reaction product, the ashing reaction product, the metal oxide, and the like are simultaneously removed by the organic ammonium salt-containing cleaning solution, so that the insulating film is formed by the photolithography method. The cleaning capability in the hole or groove and the cleaning capability of the surface of the metal film are increased, and the cleaning time can be greatly shortened compared to the conventional case.
[0093]
This improves the throughput of the manufacturing process of the semiconductor device, suppresses the increase in resistance of contact plugs, vias, and wiring due to foreign substances such as reaction products and altered substances, and improves the connection between the upper and lower sides of the metal pattern. Is possible.
[Brief description of the drawings]
FIGS. 1A to 1D are cross-sectional views showing a manufacturing process of a copper wiring in a conventional semiconductor device.
FIGS. 2A and 2B are cross-sectional views (part 1) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIGS.
FIGS. 3A and 3B are sectional views (No. 2) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIGS.
FIGS. 4A and 4B are sectional views (No. 3) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIGS.
FIGS. 5A and 5B are sectional views (No. 4) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIGS.
FIGS. 6A and 6B are sectional views (No. 5) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIGS.
FIGS. 7A and 7B are sectional views (No. 6) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIGS.
FIG. 8 is a configuration diagram showing an example of a cleaning apparatus used in an embodiment of the present invention.
FIG. 9 is a diagram showing the relationship between the cleaning time and the surface state of the exposed copper surface after resist removal using the cleaning liquid according to the embodiment of the present invention.
FIG. 10 is a diagram showing a relationship between a cleaning time and a surface state of an exposed copper surface after resist removal using a conventional amine cleaning liquid.
FIGS. 11A and 11B are cross-sectional views (part 1) showing a manufacturing process of a semiconductor device according to the second embodiment of the invention. FIGS.
FIGS. 12A and 12B are sectional views (No. 2) showing the manufacturing process of the semiconductor device according to the second embodiment of the invention. FIGS.
FIGS. 13A and 13B are sectional views (No. 3) showing the manufacturing process of the semiconductor device according to the second embodiment of the invention. FIGS.
FIGS. 14A and 14B are sectional views (No. 4) showing the manufacturing process of the semiconductor device according to the second embodiment of the invention. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation insulating layer, 3 ... MOS transistor, 4, 8, 10, 12 ... Interlayer insulating film, 5a, 5b, 9 ... Conductive plug, 7 ... Wiring, 11 ... 1st copper ( (Metal) wiring, 11d, 11e ... copper oxide, 12a ... via hole, 12b ... wiring groove, 13 ... resist, 14 ... foreign material, 15 ... resist, 16 ... foreign material, 17a, 39 ... barrier metal layer, 17b, 40 ... copper Layer, 18, 41 ... via, 19,42 ... second copper (metal) wiring, 31 ... interlayer insulating film, 31a ... via hole, 31b ... wiring trench 32 ... lower layer, 33 ... intermediate layer, 34 ... upper Layer, 36, 37 ... resist, 38 ... foreign matter.

Claims (7)

Forming a first insulating film above the semiconductor substrate;
Forming a first metal wiring on the first insulating film;
Forming a second insulating film on the first metal wiring and the first insulating film;
Forming a mask having an opening on the second insulating film;
Etching the second insulating film through the opening to form at least one of a hole and a groove;
Removing the mask;
Foreign matter adhering in at least one of the hole and the groove is removed by a cleaning solution containing ammonium phosphate and carboxylic acids, and at the same time, an oxide on the surface of the first metal wiring exposed from at least one of the hole and the groove. Removing the
A method of manufacturing a semiconductor device, comprising: filling a metal in at least one of the hole and the groove. The method of manufacturing a semiconductor device according to claim 1, wherein the carboxylic acid is oxalic acid .   The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of the cleaning liquid is set in a range of 20 ° C. or more and 80 ° C. or less. A cleaning liquid for semiconductor devices, wherein ammonium phosphate and carboxylic acids are added. 5. The carboxylic acid in the cleaning liquid is oxalic acid, and the concentration of the oxalic acid is 0.01 wt% or more and 5.0 wt% or less with respect to the entire cleaning liquid. The cleaning liquid for semiconductor devices described in 1. The cleaning liquid for a semiconductor device according to claim 4, wherein the hydrogen ion concentration is 10 ⁻⁵ mol / liter or more.   5. The semiconductor device cleaning liquid according to claim 4, wherein the moisture content is 50 to 99% by weight.

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