JP2004031637A - Method of forming wiring structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a wiring structure in which no fence is formed even when a film having a low dielectric constant is subjected to trench-etching. <P>SOLUTION: A decomposed layer 106 from which C is extracted is formed on the surface portion of the film 104 having a low dielectric constant provided in the side wall section of a via hole 105 so that the width of the layer 106 may become thicker than that of a fence 110 formed later. When the trench-etching is performed in the course of forming a dual damascene structure thereafter, a fence 110 is formed. Since the fence 110 is formed of the decomposed layer 106, only the fence 110 can be removed without etching the film 104 and a barrier insulating film 103 by performing wet-etching by using, for example, an HF-based etchant. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for forming a dual damascene wiring structure having a low dielectric constant insulating film in an electronic device such as a semiconductor device.
[0002]
[Prior art]
2. Description of the Related Art In recent years, in a semiconductor integrated circuit device, in particular, an LSI, dual damascene wiring using copper wiring has been used for the purpose of reducing wiring resistance and improving wiring reliability with an increase in the operating speed of elements. . At the same time, it has become essential to reduce the capacitance between wiring layers by using a low dielectric constant insulating film.
[0003]
In the conventional method, there is a method described in JP-A-2001-326278 as a method of forming a wiring structure. Hereinafter, description will be made with reference to FIGS.
[0004]
First, as shown in FIG. 13A, an interlayer insulating film 2 is formed on a semiconductor substrate 1, and a lower wiring 3 is formed thereon. After that, a first stopper film 4 is formed so as to cover the lower wiring 3, and a lower inter-wiring insulating film 5, a second stopper film 6, and an upper interlayer insulating film 7 are sequentially formed.
[0005]
Next, as shown in FIG. 13B, a resist pattern (not shown) is patterned on the upper interlayer insulating film 7, and the upper interlayer insulating film 7, the groove stopper film 6, and the lower interlayer The insulating film 5 is sequentially etched to form a connection hole 9 reaching the connection hole opening stopper film 4.
[0006]
After that, as shown in FIG. 13C, the resist pattern (not shown) is removed to complete the connection hole 9.
[0007]
Subsequently, as shown in FIG. 14A, the organic compound 10 is embedded in the connection hole 9.
[0008]
Next, as shown in FIG. 14B, a resist pattern 11 is patterned on the upper interlayer insulating film 7.
[0009]
Thereafter, as shown in FIG. 14C, using the resist pattern 11 as a mask, the upper interlayer insulating film 7 is subjected to dry etching with respect to the groove stopper 6 so that the etching selectivity becomes 10 or more, thereby forming the wiring groove 12. Form.
[0010]
Subsequently, as shown in FIG. 15A, the resist pattern 11, the organic compound 10, and the etching deposition film 14 are simultaneously removed. Further, the groove stopper film 6 and the connection hole opening stopper film 4 are removed by wet processing.
[0011]
Next, as shown in FIG. 15B, an upper wiring material 13 is formed on the entire surface and buried in the connection holes 9 and the wiring grooves 12 by a CMP (chemical mechanical polishing) method or the like to complete the wiring.
[0012]
[Problems to be solved by the invention]
In recent years, along with miniaturization of wiring intervals, it has become necessary to reduce the capacitance between wirings, and it has become essential to use a low dielectric constant film (organic compound film) as an interlayer insulating film. However, the etching rate of the organic compound film buried in the connection hole is lower than that of the low dielectric constant film which is an interlayer insulating film.
[0013]
Specifically, as shown in FIG. 11A, in a first insulating film 101 formed on a substrate (not shown), a lower layer made of a first barrier metal 102A and a first metal film 102B is formed. A wiring layer 102 is formed, and a barrier insulating film 103 is deposited thereon. Furthermore, a low dielectric constant film 104 is deposited thereon, and an organic ARC 107 is formed in the via hole and on the low dielectric constant film 104 in the low dielectric constant film 104. Here, since the organic ARC 107 has a lower etching rate than the low dielectric constant film 104, a step is generated at the time of etching according to the conventional method, and a deposit 109 is deposited there.
[0014]
As a result, a fence 110 is generated as shown in FIG.
[0015]
After that, when the wiring is formed as it is, as shown in FIG. 11C, the coverage of the barrier film is reduced at the fence upper part A, the cross-sectional area of the Cu film is reduced at the fence upper part B, and the barrier film is formed at the hole bottom part C. The coverage is reduced, or a burying failure of the Cu film or the like occurs.
[0016]
Therefore, an object of the present invention is to provide a method of forming a dual damascene wiring structure in which a fence does not occur even when a low dielectric constant film is used.
[0017]
[Means for Solving the Problems]
In order to solve the above problems, in the present invention, a step of forming a first groove in a low dielectric constant film and a step of forming an altered layer on a surface portion of the low dielectric constant film on the inner wall of the first groove Forming a plug made of a low-dielectric-constant film and a material that can be selectively removed in the first groove; Forming a second groove partially including a step of forming a via hole and a trench in a low dielectric constant film by selectively removing a plug and a deteriorated layer. I do.
[0018]
As a result, even when a low dielectric constant film is used, a fence made of a modified layer can be formed, so that even if a fence occurs, it can be easily removed, and finally, the fence does not exist. In addition, a dual damascene structure in which the coverage of the barrier film does not decrease and the Cu film can be easily embedded can be formed.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
[0020]
(1st Embodiment)
A method for forming a wiring structure according to the first embodiment will be described with reference to the drawings.
[0021]
First, as shown in FIG. 1A, a first wiring layer trench pattern (for example, a depth of 225 nm) is formed in an insulating film 101 formed on a semiconductor substrate (not shown), and Ta and TaN are formed. A first barrier metal 102A (for example, Ta (upper) / TaN (lower) = 10 nm / 10 nm) and a seed Cu film (not shown; for example, Cu = 80 nm) are formed by sputtering.
[0022]
Next, 102B, which is a first metal film containing Cu as a main component, is formed by an electroplating method, and an unnecessary Cu film, Ta film, and TaN film other than the trench portion are formed by a chemical mechanical polishing method (hereinafter, CMP method). Then, the first wiring layer 102 is formed.
[0023]
Then, after reducing and removing the natural oxide film on the Cu film 102 by NH ₃ plasma treatment, a Cu barrier insulating film 103 (for example, 50 nm) made of SiC and a low dielectric constant made of organic silicate glass (SiOC) are used. The film 104 (for example, 650 nm) is formed.
[0024]
Subsequently, a part (for example, 150 nm) of the low dielectric constant film 104 is removed and flattened by the CMP method. Next, photolithography and dry etching are sequentially performed to form a via hole 105, and the remaining resist and residue are removed by ashing and cleaning.
[0025]
Thereafter, as shown in FIG. 1B, by performing a plasma treatment using NH ₃ gas, an altered layer 106 in which the carbon (C) component in the side wall of the via hole 105 is partially removed is formed. The altered layer 106 contains silicon (Si) and oxygen (O) as main components. At this time, the altered layer 106 on the side wall of the via hole 105 needs to have a thickness equal to or larger than the width of the fence 110 formed at the time of trench etching which is a later step. The altered layer 106 is also formed on the surface of the SiOC film 104.
[0026]
Note that the gas in the plasma processing may be O ₂ plasma or the like in addition to NH _{3, and} other processing may be used instead of the plasma processing as long as the processing can remove the C component of the low dielectric constant film 104.
[0027]
Next, as shown in FIG. 1C, an organic ARC (organic antireflection film) 107 is applied, the via holes 105 are buried, a resist is applied, and a second wiring trench pattern 108 is formed by lithography. . The reason why the organic ARC film 107 is applied here is that, by preventing reflection at the time of exposure, dimensional variations at the time of lithography can be suppressed.
[0028]
Next, as shown in FIG. 2A, a trench 111 is formed by anisotropic dry etching. At this time, since the dry etching is anisotropic, a deposit 109 which is a reaction by-product during the dry etching is generated on the side wall of the fence 110 adjacent to the side wall of the trench 111 and the side wall of the resist plug. The side walls are protected by the deposits 109 attached to the side walls, and side etching is suppressed in a portion where the deposits 109 are attached.
[0029]
In this phenomenon, the effect of the altered layer 106 formed in FIG. This point will be described later in detail.
[0030]
Thereafter, as shown in FIG. 2B, the organic ARC 107, the resist pattern 108, and the deposit 109 are removed by ashing and cleaning.
[0031]
Subsequently, as shown in FIG. 2C, the altered layer 106 and the fence 110 formed of the altered layer 106 are removed by etching using a hydrofluoric acid (HF) -based gas. At this time, the HF-based gas hardly etches the low dielectric constant film 104 made of SiOC and the barrier insulating film 103 made of SiC at the bottom of the via hole.
[0032]
Next, as shown in FIG. 3A, the barrier insulating film 103 at the bottom of the via hole 105 is removed by etching the entire surface.
[0033]
Thereafter, as shown in FIG. 3B, the Cu natural oxide film and the like at the bottom of the via hole 105 are removed by argon (Ar) sputter etching. Subsequently, a second barrier metal 112A (for example, Ta (upper) / TaN (lower) = 10 nm / 10 nm) and a seed Cu film (not shown) in which tantalum (Ta) and tantalum nitride (TaN) films are stacked by a sputtering method. ) Is formed, and a second metal film 112B containing Cu as a main component is formed by a plating method.
[0034]
Finally, unnecessary portions of the Cu film, the Ta film, and the TaN film other than the portion of the trench 111 are removed by the CMP method, and the second wiring layer 112 is formed.
[0035]
Here, the effect of the altered layer 106, which is a feature of the present embodiment, will be described.
[0036]
First, the reason why the fence 110 occurs will be described with reference to FIG.
[0037]
The organic ARC 107 has a lower etching rate than the low dielectric constant film 104.
[0038]
Therefore, as shown in FIG. 12A, when the low dielectric constant film 104 is etched using the second wiring layer trench pattern 108 as a mask, the organic ARC 107 plug and the bottom of the low dielectric constant film 104 are etched in the process. As a result, a deposit 109 is formed on the side wall of the organic ARC 107 plug in the via hole 105 and on the side wall of the ARC film 107 plug on the trench 111 and the low dielectric constant film 104.
[0039]
Once the step is formed, as shown in FIG. 12B, a deposit 109 is formed on the side wall of the organic ARC 107 plug in the via hole 105 exposed at the step. Since the deposited material 109 is not etched, the deposited material 109 serves as a mask. As shown in FIG. 12B, the low dielectric constant film 104 remains without being etched under the deposited material 109, and the deposited material 109 remains. An additional step is formed between the trench and the flat portion at the bottom of the trench.
[0040]
When the etching is continued thereafter, as shown in FIG. 12C, the non-etched region gradually expands, and the fence 110 is formed.
[0041]
Due to the presence of the fence 110 formed in this way, as shown in FIG. 11C, due to the acute angle shape shown in the upper part A of the fence, local electric field concentration occurs, and the barrier property deteriorates. Further, since the cross-sectional area of the Cu film decreases as shown in the upper part B of the fence, the wiring resistance increases, and the electromigration resistance due to current concentration or the like deteriorates. Further, as shown in the hole bottom portion C, the effective depth of the via hole 105 increases due to the occurrence of the fence, and a poor filling of the Cu wiring due to the deterioration of the coverage of the second barrier film occurs.
[0042]
According to the present embodiment, by using the altered layer 106, the above-described problem can be solved by removing the previous fence 110. The method will be described below.
[0043]
In the etching step of FIG. 2A, the deposit 109 is always generated, and the formation of the fence 110 is inevitable. Therefore, in FIG. 1B, the altered layer 106 is formed by removing carbon (C) from an organic silicate glass (SiOC) containing silicon (Si) and oxygen (O) as main components. The altered layer 106 is formed at least in a portion that will become the fence 110 in a later step. As a result, the fence 110 actually generated is a part of the altered layer 106 and can be easily removed by etching using a hydrofluoric acid (HF) -based gas.
[0044]
On the other hand, the HF-based gas hardly etches the low dielectric constant film 104 made of SiOC and the insulating film 103 made of SiC at the bottom of the via hole 105.
[0045]
Therefore, after the via hole 105 and the trench 111 are sequentially formed, and before the barrier film 112A is deposited, only the generated fence 110 can be removed. Therefore, the barrier film 112A is deposited with good adhesion and uniformly, and Cu It is possible to prevent the occurrence of defects at the time of wiring formation.
[0046]
As described above, according to the present embodiment, the fence 110 formed at the time of trench etching is easily removed, the coverage of the barrier film is not reduced, and a dual damascene wiring structure with good Cu film embedding property can be obtained.
[0047]
In FIG. 1B, when the altered layer 106 is formed on the side wall of the via hole 105, NH ₃ plasma treatment is performed so that the altered layer 106 has a tapered shape with a thicker upper portion and a thinner lower portion. Can also be. In this case, when the altered layer 106 is removed by wet etching, the via hole 105 is tapered in a self-aligned manner. As a result, as shown in FIG. 3B, the uniform formation of the second barrier film 112A and the seed Cu by the subsequent sputtering method and the uniform formation of the second metal film 112B mainly composed of Cu by the electroplating are performed. Coverage and embedding can be improved.
[0048]
Further, in this embodiment, in addition to the embedding of the organic ARC 107 shown in FIG. 1C, as shown in FIG. 4A, a resist plug 113 formed by etching the entire surface after embedding the resist is used. Can also be. As a method other than embedding the organic ARC 107 shown in FIG. 1C, as shown in FIG. 4B, an organic ARC 107 film is deposited on the resist plug 113 formed in FIG. Can also be used.
[0049]
(Second embodiment)
A method for forming a wiring structure according to the second embodiment will be described with reference to the drawings.
[0050]
First, as shown in FIG. 5A, similarly to the first embodiment, a first wiring layer trench pattern, Ta and TaN are formed in an insulating film 101 formed on a semiconductor substrate (not shown). A first wiring layer 102 composed of a first barrier metal 102A in which films are stacked, Cu for seed (not shown), and a first metal film 102B containing Cu as a main component is formed.
[0051]
Thereafter, an NH ₃ plasma process is performed to reduce and remove the natural oxide film on the Cu film 102, and then a Cu barrier insulating film 103 made of SiC and a low dielectric constant film 104 made of SiOC are formed. Subsequently, the upper surface of the low dielectric constant film 104 is planarized by the CMP method.
[0052]
Next, a via pattern 105 is formed by photolithography, and dry etching is performed using the via pattern 121 as a mask to form a via hole 105.
[0053]
Thereafter, as shown in FIG. 5B, NH ₃ plasma processing is performed using the via pattern 121 as a mask. As a result, it is possible to form the altered layer 106 containing Si and O as main components while partially removing the C component from the side wall of the via hole 105.
[0054]
On the other hand, here, unlike the first embodiment, since the via pattern 121 is used as a mask, the altered layer 106 is not formed on the surface of the SiOC film 104. At this time, the deteriorated layer 106 on the side wall of the via hole 105 needs to have a film thickness equal to or larger than the width of the fence 110 formed at the time of subsequent trench etching.
[0055]
In addition, other than the NH ₃ plasma processing, another method may be used as long as the C component can be removed from the low dielectric constant film 104 such as O ₂ plasma.
[0056]
After that, the via pattern 121 is removed by ashing and cleaning.
[0057]
Subsequently, as shown in FIG. 5C, an organic ARC film 107 is applied to fill the via holes 105, and an ARC is also formed on the surface of the insulating film 104. Thereafter, a resist is applied, and a second wiring trench pattern 108 is formed by lithography.
[0058]
Subsequently, the wiring is completed using the same method as in the first embodiment.
[0059]
Specifically, first, as shown in FIG. 6A, a trench pattern 108 is formed by anisotropic dry etching. At this time, a deposit 109 which is a reaction by-product of dry etching and a fence 110 on the side wall of the via hole 105 due to the deposit 109 are formed. The fence 110 formed at this time is formed by the altered layer 106. This is because, in the step shown in FIG. 5B, the side wall of the via hole 105 has been altered so that the thickness of the fence 110 is equal to or greater than that of the fence 110.
[0060]
Next, as shown in FIG. 6B, the organic ARC film 107, the trench pattern 108, and the deposit 109 are sequentially removed by ashing and cleaning.
[0061]
Thereafter, as shown in FIG. 6C, etching is performed using an HF-based gas to remove the fence 110 formed of the altered layer. At this time, in the HF system, the low dielectric constant film 104 made of SiOC and the barrier insulating film 103 made of SiC at the bottom of the via hole 105 are hardly etched.
[0062]
Subsequently, as in the first embodiment, as shown in FIG. 7A, the barrier insulating film 103 at the bottom of the via hole 105 is removed by etching over the entire surface, and as shown in FIG. A second wiring layer 112 made of 112A and a second metal film 112B containing Cu as a main component is formed.
[0063]
According to the present embodiment, similarly to the first embodiment, by forming the fence 110 with the altered layer 106, the low-dielectric-constant film 104 and the barrier insulating film 103 can be etched using an HF-based gas. The fence 110 can be removed, and a dual damascene wiring structure without a fence can be realized.
[0064]
Further, since the NH ₃ plasma treatment is performed as it is using the via pattern 121 as a mask, the altered layer 106 is not formed on the surface of the low dielectric constant film 104. Therefore, damage to the surface of the low dielectric constant film 104 due to etching when the altered layer 106 is removed can be suppressed, and a high quality low dielectric constant film can be formed without increasing the number of steps.
[0065]
(Third embodiment)
A method for forming a wiring structure according to a third embodiment of the present invention will be described with reference to the drawings.
[0066]
First, as shown in FIG. 8A, a first insulating film is deposited on a semiconductor substrate (not shown), and a first wiring layer 102 is formed thereon. After that, a barrier insulating film 103 and a low dielectric constant film 104 made of SiOC are sequentially formed. Subsequently, the surface of the low dielectric constant film 104 is planarized by the CMP method, and a cap film 131 such as an oxide film (SiO ₂ ) formed by, for example, TEOS is formed thereon.
[0067]
Here, unlike the first embodiment, the present embodiment is characterized in that this “cap film 131 is used as a mask at the time of forming the altered layer”.
[0068]
Then, via holes 105 are formed by photolithography, dry etching, ashing, and cleaning.
[0069]
Next, as shown in FIG. 8B, by performing NH ₃ plasma treatment, an altered layer 106 containing Si and O as main components is formed by partially removing the C component from the side wall of the via hole 105. . At this time, the altered layer 106 on the side wall of the via hole 105 needs to have a thickness equal to or larger than the width of the fence 110 formed at the time of the subsequent trench etching. On the other hand, the deteriorated layer 106 is not formed on the surface of the low dielectric constant film (SiOC) 104 by using the cap film 131 as a mask.
[0070]
In addition, other than the NH ₃ plasma processing, other methods may be used as long as the processing can remove the C component from the low dielectric constant film 104 such as O ₂ plasma.
[0071]
Thereafter, as shown in FIG. 8C, the organic ARC 107 is applied to fill the via hole 105, and the organic ARC 107 is also formed on the surface of the cap film 131. Thereafter, a resist is applied, and a second wiring trench pattern 108 is formed by lithography.
[0072]
Subsequently, as shown in FIG. 9A, a trench pattern 108 is formed by anisotropic dry etching. At this time, a deposit 109 which is a reaction by-product of dry etching and a fence 110 on the side wall of the via hole due to the deposit 109 are formed. Since the altered layer 106 is formed so as to be equal to or larger than the size of the fence 110 in the step of FIG. 8B, the fence 110 is formed by the altered layer 106 on the side wall of the via hole 105.
[0073]
Next, as shown in FIG. 9B, the organic ARC 107, the resist pattern 108, and the deposit 109 in the via hole 105 are removed by ashing and cleaning.
[0074]
Thereafter, as shown in FIG. 9C, the altered layer 106, the fence 110 formed of the altered layer, and the cap film 131 are removed by HF etching. At this time, the HF-based gas hardly etches the low dielectric constant film 104 made of SiOC and the barrier insulating film 103 made of SiC at the bottom of the via hole 105.
[0075]
Subsequently, as shown in FIG. 10A, the barrier insulating film 103 at the bottom of the via hole 105 is removed by etching the entire surface, and as shown in FIG. 10B, the second barrier metal 112A and Cu The second wiring layer 112 made of the second metal film 112B thus formed is formed.
[0076]
As described above, according to the present embodiment, similarly to the first embodiment, by forming the fence 110 with the altered layer 106, the low dielectric constant film 104 and the barrier insulating film 103 are etched using an HF-based gas. The fence 110 can be removed without performing, and a dual damascene wiring structure without a fence can be realized.
[0077]
Further, the cap film 131 on the previously formed low dielectric constant film 104 also serves as a mask during the NH ₃ plasma treatment at the time of forming the altered layer 106 and the ashing at the time of removing the second wiring trench pattern 108 after the trench etching. . Therefore, the deteriorated layer 106 is not formed on the surface of the low dielectric constant film 104, and damage to the surface of the low dielectric constant film 104 at the time of ashing is small, so that a high quality low dielectric constant film 104 can be formed. Further, since the cap film 131 is made of SiO _2, it can be removed at the same time when the deteriorated layer 106 is removed, without increasing the number of steps.
[0078]
Even when the same mask is used, if the resist after etching the via hole 105 is used as a mask as in the second embodiment, the via hole etching is performed on the side wall of the via hole 105 after the NH ₃ plasma treatment. In some cases, deposits at the time remain, and it is difficult to form the altered layer 106 having a sufficient thickness.
[0079]
However, in the present embodiment, since the NH ₃ plasma treatment is performed after the via hole pattern is removed, the deposit 109 due to the resist material does not occur. Therefore, it is possible to easily form the altered layer 106 having a sufficient thickness.
[0080]
【The invention's effect】
According to the invention, the fence is formed by a modified layer. Therefore, for example, by performing an HF wet etching process, the fence can be easily removed without etching the low dielectric constant film and the barrier insulating film.
[0081]
As a result, the coverage of the barrier film is improved, and it is possible to prevent local electric field concentration and an increase in the effective depth of the via hole in the embedded wiring of the Cu film. Therefore, it is possible to realize a dual damascene wiring structure in which the electromigration resistance does not easily deteriorate and the Cu film can be easily embedded.
[Brief description of the drawings]
FIG. 1 is a sectional view of a process in a first embodiment; FIG. 2 is a sectional view of a process in a first embodiment; FIG. 3 is a sectional view of a process in a first embodiment; FIG. FIG. 5 is a process sectional view in the second embodiment. FIG. 6 is a process sectional view in the second embodiment. FIG. 7 is a process sectional view in the second embodiment. FIG. 8 is a third embodiment. FIG. 9 is a process cross-sectional view in the third embodiment. FIG. 10 is a process cross-sectional view in the third embodiment. FIG. 11 is a diagram showing a problem of the conventional method. 13 is a cross-sectional view of a process in a conventional method. FIG. 14 is a cross-sectional view of a process in a conventional method. FIG. 15 is a cross-sectional view of a process in a conventional method.
Reference Signs List 101 First insulating film 102 First wiring layer 102A First barrier metal 102B First metal film 103 Barrier insulating film 104 Low dielectric constant film 105 Via hole 106 Altered layer 107 Organic ARC
108 second wiring layer trench pattern 109 deposition object 110 fence 111 trench 112 second wiring layer 112A second barrier metal 112B second metal film 113 resist plug 121 via pattern 131 cap film

Claims (7)

Forming a first groove in the low dielectric constant film;
Forming an altered layer on a surface portion of the low dielectric constant film on an inner wall of the first groove;
Forming a plug made of a material that can be selectively removed with the low dielectric constant film in the first groove;
Forming a second groove partially including the first groove in the low dielectric constant film by partially removing the low dielectric constant film and the altered layer;
Selectively removing the plug and the altered layer to form via holes and trenches in the low dielectric constant film;
A method for forming a wiring structure, comprising: 2. The method according to claim 1, wherein the width of the altered layer is greater than the width of the fence. 2. The method according to claim 1, wherein the plug is made of an organic material, the plug is removed by ashing or cleaning, and the altered layer is selectively removed by wet etching. 2. The low dielectric constant film according to claim 1, wherein the low dielectric constant film mainly contains Si, O, and C as constituent components, and the altered layer is formed by a process of removing a C component from the low dielectric constant film. A method for forming a wiring structure. The altered layer is formed as a forward tapered shape in which the upper part is thicker than the lower part,
2. The method for forming a wiring structure according to claim 1, wherein the via hole having a forward tapered shape is formed by removing the altered layer. 2. The method for forming a wiring structure according to claim 1, wherein the altered layer is formed using the resist material at the time of forming the first groove as a mask. 2. The method according to claim 1, wherein a cap layer is formed on the low dielectric constant film, and the altered layer is formed using the cap layer as a mask.

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