JP2003017467A - Semiconductor integrated circuit device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for securing photoresist film, used as a mask in a process for forming a wiring groove or a connection hole, by etching in an insulating film where an SiC film is formed as an etching stopper film. SOLUTION: In a process for forming an open hole section 27, by etching where a photoresist film 26 is used as a mask in an insulation film where an insulation film 17, a cap insulating film 18, an etching stopper film 19, an insulation film 20, and a cap insulating film 21 are laminated, flow rate of an O2 gas in an etching gas is increased and decreased relatively, in the etching process of the etching stopper film 19, and that of the O2 gas in the etching gas is reduced in the etching process of the cap insulating film 21, the insulation film 20, the cap insulating film 18, and the insulating film 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique and a semiconductor integrated circuit device, and more particularly,
The present invention relates to a technique effectively applied to the manufacture of a semiconductor integrated circuit device having a wiring formed by embedding a conductive film in a wiring-forming groove formed in an insulating film.

[0002]

2. Description of the Related Art As the degree of integration of elements in a semiconductor integrated circuit device is improved and the size of a semiconductor chip is reduced, wirings constituting the semiconductor integrated circuit device are becoming finer and multilayered. In particular, in a logic semiconductor integrated circuit device having a multi-layer wiring structure, wiring delay is one of the dominant factors of signal delay of the entire semiconductor integrated circuit device.
Since the speed of the signal flowing through the wiring is proportional to the wiring resistance and the wiring capacitance, it is important to reduce the wiring resistance and the wiring capacitance in order to improve the wiring delay.

Regarding reduction of wiring resistance, damascene (Damascen) using a copper material (copper or copper alloy) as a wiring material
e) The application of the law is ongoing. In this method, after forming a wiring groove or a connection hole in an insulating film, a conductive film for forming a wiring or a plug is deposited on the main surface of a semiconductor substrate, and a region other than the wiring groove or the connection hole is formed. Chemical Mechanical Polishing (CMP) of conductive film
It is a method of forming a buried wiring in a wiring groove or a plug in a connection hole by removing it by shing). This method is particularly suitable as a method for forming embedded wiring made of a copper-based conductor material (copper or copper alloy), which is difficult to perform fine etching.

Further, as an application of the damascene method, there is a dual-damascene method. This method forms a wiring forming groove (hereinafter referred to as a wiring groove) in an insulating film and a connection hole for connecting to a lower layer wiring, and then forms a wiring forming conductive film on a main surface of a semiconductor substrate. In this method, a buried film is formed in the groove for forming a wiring and a plug is formed in the connection hole by depositing and further removing the conductive film in the region other than the groove by CMP.
In the case of this method, particularly in a semiconductor integrated circuit having a multilayer wiring structure, the number of steps can be reduced and the wiring cost can be reduced.

A wiring forming technique using such a damascene method is disclosed in, for example, Japanese Patent Laid-Open No. 10-135153.
It is described in the official gazette.

[0006]

By the way, in the damascene method and the dual damascene method described above, when a groove or hole for forming a wiring is formed in an interlayer insulating film, the lower layer is damaged due to excessive digging or a processing dimension. An insulating film for an etching stopper is formed below the interlayer insulating film in order to avoid deterioration of accuracy. In the technique of forming the interlayer insulating film with a silicon oxide film or the like, a silicon nitride film is used as the insulating film for the etching stopper. However, since the silicon nitride film has a high relative permittivity (= ε) of about 7.2, the present inventors have replaced the silicon nitride film as the insulating film for the etching stopper with Si having a low relative permittivity.
We are considering introducing a C (silicon carbide (ε = about 4.7)) film. However, the present inventors have found that the use of the SiC film as the etching stopper film has the following problems.

That is, in order to promote the etching reaction of C (carbon) in the SiC film, it is effective to increase the flow rate of O ₂ (oxygen) gas in the etching gas. However, increasing the flow rate of O ₂ gas also promotes the etching reaction of the photoresist film used as a mask during etching. Therefore, it is difficult to leave the photoresist film in the step of forming the wiring groove or the connection hole by etching using the dual damascene method, and it is difficult to secure the mask at the time of etching.

An object of the present invention is to provide a technique for securing a photoresist film serving as a mask in a step of forming a wiring groove or a connection hole in an insulating film having an SiC film as an etching stopper film by etching. is there.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the present invention, a first insulating film containing silicon oxide as a main component, a second insulating film containing silicon carbide as a main component, and a third insulating film containing silicon oxide as a main component are formed on a semiconductor substrate from the lower layer. And a step of forming a photosensitive masking layer on the third insulating film, and etching the third insulating film using the masking layer as a mask and using a first etching gas containing an oxygen-based gas. And a step of etching the second insulating film using a second etching gas containing an oxygen-based gas with the masking layer as a mask, and a first etching gas containing an oxygen-based gas with the masking layer as a mask. Is used to etch the first insulating film, and the flow rate of the oxygen-based gas contained in the first etching gas is the oxygen-based gas contained in the second etching gas. Relatively smaller than the flow rate, the first
The flow rate is such that the masking layer remains after the step of etching the insulating film.

Further, according to the present invention, (a) a fourth layer containing silicon carbide as a main component from the lower layer on the main surface of the semiconductor substrate.
An insulating film, a first insulating film containing silicon oxide as a main component, a second insulating film containing silicon carbide as a main component and a third insulating film containing silicon oxide as a main component are formed, and (b) the third insulating film.
A wiring groove for forming a wiring is formed in the insulating film and the second insulating film, and (c) a connection hole is formed from the bottom of the wiring groove to the wiring formed therebelow.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) A semiconductor integrated circuit device according to the first embodiment is, for example, a CMOS logic LSI. Regarding the manufacturing method of this CMOS logic LSI,
This will be described with reference to FIGS.

First, as shown in FIG. 1, the specific resistance is 10Ω.
The semiconductor substrate 1 made of single crystal silicon having a size of about
Heat treatment is performed at about 0 ° C. to form a thin silicon oxide film (pad oxide film) with a film thickness of about 10 nm on the main surface. Then, a silicon nitride film having a thickness of about 120 nm is deposited on the silicon oxide film by a CVD (Chemical Vapor Deposition) method, and then the silicon nitride film and the silicon oxide film in the element isolation region are dry-etched using the photoresist film as a mask. And are removed. The silicon oxide film is formed for the purpose of relieving stress applied to the substrate when the silicon oxide film embedded in the element isolation trench is densified (baked up) in a later step. In addition, since the silicon nitride film has a property of being hard to be oxidized, it is used as a mask for preventing the oxidation of the substrate surface below it (active region).

Subsequently, by dry etching using a silicon nitride film as a mask, a depth of 3 is formed in the semiconductor substrate 1 in the element isolation region.
After forming the groove of about 50 nm, in order to remove the damage layer generated on the inner wall of the groove by etching, the semiconductor substrate 1 is heat-treated at about 1000 ° C. to form a thin silicon oxide film of about 10 nm on the inner wall of the groove. Form.

Then, after depositing a silicon oxide film on the semiconductor substrate 1 by the CVD method, the semiconductor substrate 1 is heat-treated to densify (baking) it in order to improve the quality of the silicon oxide film. ) Do. After that, chemical mechanical polishing (Chemic
The silicon oxide film is polished by an al mechanical polishing (CMP) method and left inside the groove to form the element isolation groove 2 whose surface is flattened.

Then, after removing the silicon nitride film remaining on the active region of the semiconductor substrate 1 by wet etching using hot phosphoric acid, the n-channel MISF of the semiconductor substrate 1 is removed.
B (boron) is ion-implanted into the region where ET is formed, and p
A mold well 3 is formed. Then, P (phosphorus) is ion-implanted into the region of the semiconductor substrate 1 where the p-channel type MISFET is to be formed to form the n-type well 4.

Subsequently, the semiconductor substrate 1 is heat-treated to form the gate oxide film 5 on the surfaces of the p-type well 3 and the n-type well 4, and then the gate electrode 6 is formed on the gate oxide film 5. Gate electrode 6 is formed of, for example, a three-layer conductive film in which a low-resistance polycrystalline silicon film doped with P, a WN (tungsten nitride) film, and a W (tungsten) film are stacked in this order.

Next, P or As (arsenic) is ion-implanted into the p-type well 3 to form an n-type semiconductor region (source, drain) 7, and B is ion-implanted into the n-type well 4 to form the p-type. A semiconductor region (source, drain) 8 is formed. Through the steps up to this point, the n-channel type MISFETQn is formed in the p-type well 3 and the p-channel type MISFETQp is formed in the n-type well 4.

Then, an interlayer insulating film 9 made of silicon oxide is formed on the n-channel type MISFET Qn and the p-channel type MISFET Qp.

Next, as shown in FIG. 2, the interlayer insulating film 9 is dry-etched using a photoresist film (not shown) patterned by a photolithography technique as a mask, to thereby form an n-type semiconductor region (source, Drain) 7 and p-type semiconductor region (source, drain)
A contact hole 10 is formed on the upper portion of the contact hole 8. continue,
For example, a titanium nitride film is deposited on the semiconductor substrate 1 including the inside of the contact hole 10 by a sputtering method, and then a W (tungsten) film is further deposited by a CVD method to fill the contact hole 10 with the W film. After that, the insulating film 9 other than the contact hole 10
The upper titanium nitride film and the W film are removed by, for example, the CMP method to form the plug 11.

Then, a SiC film is deposited on the semiconductor substrate 1 by, for example, a plasma CVD method to obtain a film thickness of about 100 n.
An etching stopper film 12 of m is formed. The etching stopper film 12 is for avoiding damage to the lower layer or deterioration of processing dimensional accuracy due to over-digging when forming a groove or hole for forming a wiring in the upper insulating film. It is a thing. Further, since the SiC film has a relative dielectric constant relatively lower than that of, for example, a silicon nitride film, by using the SiC film as the etching stopper film 12,
The wiring delay in the CMOS logic LSI according to the first embodiment can be improved.

Next, for example, the etching stopper film 12
A silicon oxide film is deposited on the surface of the substrate by the CVD method, and an interlayer insulating film 13 having a thickness of about 200 nm is deposited. F (fluorine) may be added to silicon oxide when forming the interlayer insulating film 13. By adding F, the dielectric constant of the interlayer insulating film 13 can be lowered, so that the overall dielectric constant of the wiring of the semiconductor integrated circuit device can be lowered, and the wiring delay can be improved.

Subsequently, the etching stopper film 12 and the interlayer insulating film 13 are processed by using a photolithography technique and a dry etching technique to form a wiring groove 14. Next, in order to remove the reaction layer on the surface of the plug 11 exposed at the bottom of the wiring groove 14, the surface treatment of the semiconductor substrate 1 is performed by sputter etching in an Ar (argon) atmosphere.

Then, a tantalum nitride film, for example, a barrier conductor film 15A is deposited on the entire surface of the semiconductor substrate 1 by reactive sputtering of a tantalum target in an argon / nitrogen mixed atmosphere. This tantalum nitride film is deposited to improve the adhesion of the copper film deposited in the subsequent steps and to prevent the diffusion of copper.
The film thickness can be exemplified to be about 30 nm. In addition,
Although the tantalum nitride film is illustrated as the barrier conductor film 15A in the first embodiment, it may be a metal film of tantalum or the like, a titanium nitride film, or a laminated film of a metal film and a titanium nitride film. When the barrier conductor film 15A is tantalum or tantalum nitride, the adhesion with the copper film is better than when titanium nitride is used. When the barrier conductor film 15A is a titanium nitride film, it is possible to sputter-etch the surface of the titanium nitride film immediately after the copper film is deposited in the subsequent step. By such sputter etching, water, oxygen molecules, etc. adsorbed on the surface of the titanium nitride film can be removed, and the adhesiveness of the copper film can be improved. This technique is particularly effective in the case where the titanium nitride film is deposited, the surface is exposed to the atmosphere by breaking the vacuum, and the copper film is deposited. It should be noted that this technique is effective not only for the titanium nitride film but also for the tantalum nitride film although there is a difference in effect.

Then, a seed film, for example, a copper film or a copper alloy film is deposited on the entire surface of the semiconductor substrate 1 on which the barrier conductor film 15A is deposited. When the seed film is a copper alloy film, Cu (copper) is contained in the alloy in an amount of about 80% by weight or more. The seed film is deposited by the long-distance sputtering method, and the thickness of the seed film depends on the wiring groove 1.
4 on the surface of the barrier conductor film 15A excluding the inside of 4
It is set to about 000Å to 2000Å, preferably about 1500Å. In the first embodiment, the case of using the long-distance sputtering method for depositing the seed film is illustrated, but an ionization sputtering method in which the directivity of sputtering is increased by ionizing Cu sputtering atoms may be used. Further, the seed film may be deposited by the CVD method, and if the CVD film forming unit is connected to the chamber for forming the barrier conductor film 15A, a high vacuum state can be maintained, so that the surface of the deposited barrier conductor film 15A is Oxidation can be prevented.

Next, the semiconductor substrate 1 on which the seed film is deposited
A conductive film made of, for example, a copper film is formed on the entire surface of the wiring groove 14
And the seed film described above are combined to form a conductive film 15B. This wiring groove 1
4 is formed by, for example, an electrolytic plating method, and the plating solution is, for example, H ₂ SO ₄ (sulfuric acid) containing 10% CuSO ₄ (copper sulfate) and an additive for improving the coverage of the copper film. Is used. When the electroplating method is used to form the conductive film filling the wiring groove 14, the growth rate of the conductive film can be electrically controlled, so that the coverage of the conductive film inside the wiring groove 14 is improved. You can In the first embodiment,
Although the case where the electroplating method is used for depositing the conductive film filling the wiring groove 14 is illustrated, the electroless plating method may be used. When the electroless plating method is used, since voltage application is not required, damage to the semiconductor substrate 1 due to voltage application can be reduced as compared with the case where the electrolytic plating method is used.

Further, subsequent to the step of forming the conductive film 15B, the copper film is fluidized by an annealing process, whereby the filling property of the conductive film 15B in the wiring groove 14 can be further improved.

Next, the excess barrier conductor film 15A and conductive film 15B on the interlayer insulating film 13 are removed, and the wiring groove 14 is formed.
The buried conductor 15 is formed by leaving the barrier conductor film 15A and the conductive film 15B inside. The barrier conductor film 15A and the conductive film 15B are removed by polishing using the CMP method.

Then, after polishing abrasive grains and copper adhering to the surface of the semiconductor substrate 1 are removed by two-step brush scrub cleaning using, for example, a 0.1% aqueous ammonia solution and pure water, the result is shown in FIG. Thus, a SiC film is deposited on the embedded wiring 15 and the insulating film 13 to form an etching stopper film (fourth insulating film) 16. For depositing this SiC film, for example, a plasma CVD method can be used, and its film thickness is about 50 nm. The etching stopper film 16 can function as an etching stopper layer when etching is performed in a later step.
In addition, the etching stopper film 16 is formed in the embedded wiring 15.
Also has a function of suppressing the diffusion of Cu that forms the conductive film 15B, and the barrier conductor film 15A (see FIG. 2) is formed on the interlayer insulating films 9 and 13 and on the interlayer insulating film formed later on the etching stopper film 16. Prevents copper diffusion and retains their insulating properties.

Next, an insulating film (first insulating film) 17 having a film thickness of about 100 nm is deposited on the surface of the etching stopper film 16. As the insulating film 17, C with fluorine added
A low dielectric constant film (SiOF film) such as a VD oxide film can be exemplified. When this low dielectric constant film is used, it is possible to reduce the overall dielectric constant of the wiring of the semiconductor integrated circuit device, and it is possible to improve the wiring delay.

Then, a film thickness of 10 is formed on the surface of the insulating film 17.
A cap insulating film (first insulating film) 18 is formed by depositing a silicon oxide film of about 0 nm.

Then, a SiC film is deposited on the surface of the cap insulating film 18 by, for example, a plasma CVD method to form an etching stopper (second insulating film) film 19 having a film thickness of about 25 nm. This etching stopper film 19 may damage an underlying layer due to over-digging when an insulating film is formed on the etching stopper film 19 in a later step and a groove or hole for forming a wiring is formed in the insulating film. This is for avoiding deterioration of processing dimensional accuracy.

Next, a silicon oxide (SiOF) film containing fluorine is deposited on the surface of the etching stopper film 19 by, for example, a CVD method to form an insulating film (third insulating film) 20 having a thickness of about 100 nm. To do. Subsequently, a cap oxide film (third insulating film) 21 is formed by depositing a silicon oxide film having a film thickness of about 125 nm on the surface of the insulating film 20.
To form. Then, on the surface of the cap insulating film 21, a SiC film having a thickness of about 50 nm is formed by, for example, a plasma CVD method.
By depositing the film, the etching stopper film (the fifth
An insulating film) 22 is formed.

Next, as shown in FIG. 4, the antireflection film 2 having a film thickness of about 120 nm is formed on the surface of the etching stopper film 22.
3 is formed. Then, on the surface of the antireflection film 23,
For example, it consists of polyhydroxystyrene and acid generator,
A photoresist film (first masking layer) 24 having a film thickness of about 480 nm is formed. Then, the photoresist film 24 is subjected to heat treatment, exposure treatment, and development treatment to pattern the photoresist film 24. The pattern of the photoresist film 24 is, for example, a mask pattern for forming a flat band-shaped or rectangular wiring groove, and is formed so that the wiring groove formation region is exposed and the other regions are covered. .

Next, using the photoresist film 24 as a mask, the antireflection film 23 is etched by using, for example, an etching gas containing CHF ₃ / O ₂ / Ar as a component.

Then, the etching stopper film 22 is etched using the photoresist film 24 as a mask and an etching gas containing, for example, CHF ₃ / O ₂ / Ar as a component. At this time, instead of CHF ₃ gas, CH ₂ F ₂ gas, CF ₄ gas or CF ₄ and C is used as an etching gas.
It may also be used containing a mixed gas of HF ₃ as a component.

Next, after removing the photoresist film 24 and the antireflection film 23 by the ashing method, as shown in FIG. 5, an antireflection film 25 having a thickness of about 120 nm is formed on the semiconductor substrate 1. The antireflection film 25 is formed so as to fill the groove between the etching stopper films 22.

Subsequently, a film of polyhydroxystyrene and an acid generator having a thickness of 480 is formed on the surface of the antireflection film 25.
A photoresist film (masking layer, second masking layer) 26 having a thickness of about nm is formed. Then, the photoresist film 26 is patterned by subjecting the photoresist film 26 to heat treatment, exposure treatment, and development treatment.

Next, as shown in FIG. 6, using the patterned photoresist film 26 as a mask, for example, CH
The antireflection film 25 is etched by using an etching gas containing F ₃ / O ₂ / Ar as a component. Here, the flow rate of each gas contained in the etching gas is 30 times as much as CHF ₃ gas.
For example, about 20 ml / min of O ₂ gas and about 200 ml / min of Ar gas can be exemplified. At this time, the cap insulating film 21 below the antireflection film 25 is also etched by a predetermined amount by over-etching.

Next, as shown in FIG. 7, with the photoresist film 26 as a mask, an etching gas (first etching gas) containing C ₅ F ₈ / O ₂ / Ar as a component is used, and the cap insulating film 21 and The insulating film 20 is selectively etched. At this time, the flow rate of each gas contained in the etching gas is about 0 ml / min to 30 ml / min for C ₅ F ₈ gas and 0 ml / min to 30 ml / min for O ₂ gas.
And the Ar gas is 0 ml / min to 1500 ml /
It is about min. Further, in the first embodiment, the flow rate ratio between the C ₅ F ₈ gas and the O ₂ gas (the value obtained by dividing the flow rate value of the O ₂ gas by the flow rate value of the C ₅ F ₈ gas) is about 1.5 or less. So that That is, in the first embodiment, the flow rates of the C ₅ F ₈ gas, the O ₂ gas, and the Ar gas are about 15 ml / min and 20 ml / mi, respectively.
It is possible to exemplify, for example, about n and 1500 ml / min. When the semiconductor substrate 1 is a semiconductor wafer having a diameter of about 20.32 cm (about 8 inches), the high frequency power supplied from the dry etching device is 0.2.
For example, it can be set to about kW to 2 kW.

Under such etching conditions, the photoresist film 26 can be left after the cap insulating film 21 and the insulating film 20 are etched. That is, in the subsequent steps and thereafter, the etching stopper film 1 is formed using the photoresist film 26 as a mask.
9. The cap insulating film 18 and the insulating film 17 can be etched.

In the above example, it was shown that the etching gas for etching the cap insulating film 18 and the insulating film 17 contains C ₅ F ₈ gas, but C ₅ F ₈ gas is used instead of C ₅ F ₈ gas. ₄ F ₈ gas may be included.

Next, as shown in FIG. 8, the etching stopper film 19 is selected by using the photoresist film 26 as a mask and using an etching gas (second etching gas) containing CHF ₃ / O ₂ / Ar as a component. Etching. At this time, the flow rate of each gas contained in the etching gas is CH
F ₃ gas was set to about 0 ml / min to 30 ml / min, O ₂ gas was set to about 5 ml / min to 60 ml / min, and Ar gas was set to 0 ml / min to 1000 ml / mi.
It is about n. Furthermore, in the first embodiment, C
Flow rate ratio of HF ₃ gas and O ₂ gas (flow rate value of O ₂ gas is C
The value obtained by dividing the flow rate of the HF ₃ gas) is about 0.5 or more. That is, in the first embodiment,
The flow rates of the CHF ₃ gas, O ₂ gas, and Ar gas are about 40 ml / min and 25 ml / min, respectively.
And about 200 ml / min. Since the etching stopper film 19 is formed of a SiC film, the etching reaction is promoted by increasing the flow rate of O ₂ gas as compared with the case of etching the cap insulating film 21 and the insulating film 20. You can In addition, the semiconductor substrate 1 is about 20.32 cm
In the case of a semiconductor wafer having a diameter of (about 8 inches), it can be exemplified that the high frequency power supplied from the dry etching device is set to about 0.2 kW to 2 kW.

In the above example, the etching stopper film 19
CHF is added to the etching gas when etching
_Although it is shown that ₃ gas is contained, CH ₂ F ₂ gas, CF ₄ gas or a mixed gas of CF ₄ and CHF ₃ may be contained instead of CHF ₃ gas.

Next, as shown in FIG. 9, using the photoresist film 26 as a mask, the cap insulating film 18 and the insulating film are insulated under the same etching conditions as those used for etching the cap insulating film 21 and the insulating film 20. Membrane 1
By etching 7 the opening (first opening)
27 is formed. Cap insulating film 21 and insulating film 20
By making the etching conditions similar to the etching conditions used for etching, the photoresist film 26 can be left after the step of etching the cap insulating film 18 and the insulating film 17. That is, during the etching process of the cap insulating film 18 and the insulating film 17, the masking can be surely performed by the photoresist film 26. Thereby, it becomes possible to form the opening 27 with high processing accuracy.

As described above, the etching stopper film 1
Since 9 is a SiC film, O ₂ in the etching gas
By increasing the flow rate of the gas, the etching reaction of the etching stopper film 19 can be promoted. On the other hand, when the flow rate of O ₂ gas in the etching gas is increased in the step of forming the opening 27, the etching reaction of the photoresist film 26 is also accelerated. According to the experiment conducted by the present inventors, as shown in FIG. 10, the silicon nitride (SiN) film and the silicon oxide (SiO) film are etched even if the flow rate of O ₂ gas in the etching gas is increased. It was found that there was no rapid increase in the rate, and the etching rate was rather lowered in the silicon oxide film. On the other hand, in the SiC film and the photoresist film, it was found that the etching rate of the O ₂ gas in the etching gas increased rapidly as the flow rate of the O ₂ gas increased.

Therefore, as described above, in the step of forming the opening 27, the flow rate of the O ₂ gas in the etching gas is relatively increased during the etching step of the etching stopper film 19, and the subsequent cap insulating film 21, Insulation film 2
0, during the etching process of the cap insulating film 18 and the insulating film 17, the flow rate of O ₂ gas in the etching gas is relatively reduced. Thereby, the photoresist film 26 can be left even after the step of forming the opening 27. That is, during the process of forming the opening 27,
Masking with the photoresist film 26 can be ensured.

Next, after the photoresist film 26 and the antireflection film 25 are removed by the ashing method, FIG.
As shown in FIG. 5, the opening (first opening) 28 is formed by dry etching the cap insulating film 21 and the insulating film 20 using the etching stopper film 22 as a mask.

Next, as shown in FIG. 12, the etching stopper film 22 on the cap insulating film 21, the etching stopper film 19 at the bottom of the opening 28 and the etching stopper film 16 at the bottom of the opening 27 are dry-etched. To remove. As a result, the connection hole 29 and the wiring groove 30 are formed.
Can be formed.

Next, as shown in FIG. 13, a barrier conductor film 31A is deposited by the same process as the process of depositing the barrier conductor film 15A. As the barrier conductor film 31A, for example, a tantalum nitride film can be used. In the first embodiment, a tantalum nitride film is exemplified as the barrier conductor film 31A, but a metal film of tantalum or the like,
It may be a titanium nitride film or a laminated film of a metal film and a nitride film. When the barrier conductor film 31A is a titanium nitride film, it is possible to sputter-etch the surface of the titanium nitride film immediately after the copper film is deposited in the subsequent step.

Then, a seed film, for example, a copper film or a copper alloy film is deposited on the entire surface of the semiconductor substrate 1 on which the barrier conductor film 31A is deposited. When the seed film is a copper alloy film, the alloy contains copper (Cu) in an amount of about 80% by weight or more. The seed film can be exemplified to be deposited by a long distance sputtering method.
In the first embodiment, the case where the long-distance sputtering method is used for depositing the seed film is illustrated, but an ionization sputtering method that increases the directivity of sputtering by ionizing Cu sputtering atoms may be used. The seed film may be deposited by the CVD method.

Next, the semiconductor substrate 1 on which the seed film is deposited
A conductive film made of, for example, a copper film is formed on the entire surface of the contact hole 29.
Then, the wiring groove 30 is deposited so as to be buried, and this conductive film and the above-mentioned seed film are combined to form a conductive film 31B. The conductive film filling the connection hole 29 and the wiring groove 30 can be formed by, for example, an electrolytic plating method. In the first embodiment, the case where the electroplating method is used for depositing the conductive film filling the connection hole 29 and the wiring groove 30 is illustrated, but the electroless plating method may be used. When the electroless plating method is used, it is not necessary to apply an electric field, and therefore damage to the semiconductor substrate 1 due to the electric field application can be reduced as compared with the case where the electrolytic plating method is used.

Further, subsequent to the step of forming the conductive film 31B, the conductive film 31B is fluidized by an annealing treatment, so that the filling property of the conductive film 31B in the connection hole 29 and the wiring groove 30 is improved. You can also let it.

Then, the excess barrier conductor film 31A and the conductive film 31B on the insulating film 21 are removed, and the barrier conductor film 31A and the conductive film 3 are formed in the connection hole 29 and the wiring groove 30.
By leaving 1B, the embedded wiring 31 is formed. The removal of the barrier conductor film 31A and the conductive film 31B is performed by CMP.
It is possible to exemplify performing by polishing using the method.

Subsequently, the abrasive grains and the copper adhering to the surface of the semiconductor substrate 1 are removed by a two-step brush scrub cleaning using, for example, a 0.1% aqueous ammonia solution and pure water. To manufacture the semiconductor integrated circuit device.

Here, FIG. 14 shows the etching stopper films 12 and 1 in the semiconductor integrated circuit device according to the first embodiment.
Assuming that a silicon nitride film is used as 6, 19,
At that time, the electrostatic capacity of the etching stopper films 12, 16 and 19 is set to 100%, and the etching stopper film 1
The relationship between the relative permittivity of 2, 16, and 19 and the electrostatic capacity (unit:%) was obtained by simulation by the present inventors and shown. As shown in FIG. 14, as compared with the case where the silicon nitride film having a relative permittivity of about 7.2 is used, the etching stopper films 12 and 16 using the SiC film having a relative permittivity of about 4.7 are used. , The capacitance of 19 is about 10%
It turned out that it can be reduced. That is, in the semiconductor integrated circuit device according to the first embodiment in which the SiC films are used as the etching stopper films 12, 16 and 19, the speed of the signal flowing through the wiring can be increased.

(Embodiment 2) In Embodiment 2, the semiconductor integrated circuit device of Embodiment 1 is manufactured by another manufacturing process. The manufacturing process of the second embodiment will be described with reference to FIGS.

The manufacturing process of the semiconductor integrated circuit device of the second embodiment is the same as the process of depositing the cap insulating film 21 (see FIG. 3) described in the first embodiment.

After that, as shown in FIG. 15, an antireflection film 25 having a film thickness of about 120 nm is formed on the semiconductor substrate 1. Subsequently, a photoresist film 26 made of polyhydroxystyrene and an acid generator and having a film thickness of about 480 nm is formed on the surface of the antireflection film 25. Then, the photoresist film 26 is patterned by subjecting the photoresist film 26 to heat treatment, exposure treatment, and development treatment.

Next, as shown in FIG. 16, the antireflection film 25 is formed under the same etching conditions as the step (see FIG. 6) of etching the antireflection film 25 using the photoresist film 26 as a mask in the first embodiment. To etch.

Subsequently, as shown in FIG. 17, under the same etching conditions as the step (see FIG. 7) of etching the cap insulating film 21 and the insulating film 20 using the photoresist film 26 as a mask in the first embodiment, The cap insulating film 21 and the insulating film 20 are etched. As a result, also in the second embodiment, the cap insulating film 2
After the etching process of 1 and the insulating film 20, the photoresist film 26 can be left. That is,
After the next step, the etching stopper film 19 and the cap insulating film 1 are formed by using the photoresist film 26 as a mask.
8 and the insulating film 17 can be etched.

Then, as shown in FIG. 18, the etching stopper film 19 is formed under the same etching conditions as in the step (see FIG. 8) of etching the etching stopper film 19 using the photoresist film 26 as a mask in the first embodiment. To etch. As a result, also in the second embodiment, the cap insulating film 18 and the insulating film 1 are formed.
Since the flow rate of the O ₂ gas is increased as compared with the case where the etching processing of 7 is performed, the etching reaction of the etching stopper film 19 made of the SiC film can be promoted.

Then, as shown in FIG. 19, under the same etching conditions as the step (see FIG. 9) of etching the cap insulating film 18 and the insulating film 17 using the photoresist film 26 as a mask in the first embodiment, The cap insulating film 18 and the insulating film 17 are etched to form the opening 27. As a result, also in the second embodiment, the photoresist film 26 can be left after the step of etching the cap insulating film 18 and the insulating film 17. That is, during the etching process of the cap insulating film 18 and the insulating film 17, the photoresist film 2
6 makes it possible to reliably mask.

Also in the second embodiment, as in the case of the first embodiment, in the step of forming the opening 27, the O ₂ gas in the etching gas is relatively used during the etching step of the etching stopper film 19. The flow rate of O ₂ gas in the etching gas is relatively decreased during the etching process of the cap insulating film 21, the insulating film 20, the cap insulating film 18, and the insulating film 17. Thereby, the photoresist film 26 can be left even after the step of forming the opening 27. That is, during the process of forming the opening 27, the photoresist film 2
Masking by 6 can be ensured.

Next, after removing the photoresist film 26 and the antireflection film 25 by the ashing method, FIG.
As shown in FIG. 3, an antireflection film (sixth insulating film) 25A having a film thickness of about 120 nm is formed on the semiconductor substrate 1. The antireflection film 25A is formed so as to fill the opening 27.

Then, on the surface of the antireflection film 25A,
The film thickness consisting of polyhydroxystyrene and acid generator is 48
About 0 nm photoresist film (third masking layer) 2
6A is formed. Then, the photoresist film 26A
By subjecting the photoresist film to heat treatment, exposure treatment, and development treatment, the photoresist film 26A is patterned.

Next, as shown in FIG. 21, the patterned photoresist film 26A is used as a mask and an etching gas containing, for example, CHF ₃ / O ₂ / Ar as a component is used to prevent reflection on the cap insulating film 21. The film 25A is etched.

Next, as shown in FIG. 22, using the photoresist film 26A as a mask, for example, C ₅ F ₈ / O ₂ /
By etching the cap insulating film 21 and the insulating film 20 using an etching gas containing Ar as a component,
The opening 28 is formed.

Next, as shown in FIG. 23, the photoresist film 26 and the antireflection film 25 are ashed.
To remove. Then, the etching stopper film 19 at the bottom of the opening 28 and the etching stopper film 16 at the bottom of the opening 27 are removed by a dry etching method. Thereby, the connection hole 29 and the wiring groove 30 can be formed (see FIG. 12).

Then, in the first embodiment, as shown in FIG.
The connection hole 29 is subjected to the same steps as those described with reference to FIG.
And the embedded wiring 31 is formed in the wiring groove 30 (see FIG.
3), the semiconductor integrated circuit device according to the second embodiment is manufactured.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-described embodiment, the case where the SiC film is used as the etching stopper film has been described, but Si containing a predetermined amount of N (nitrogen) in its component is used.
A CN (silicon carbonitride) film may be used.

In the above embodiment, the method for manufacturing the semiconductor integrated circuit device according to the present invention is applied to the CMOS logic L.
Although the case of manufacturing the SI has been illustrated, various Ls manufactured by the embedded wiring forming process using the damascene method.
Application to SI and the like is also possible.

[0076]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) First insulating film containing silicon oxide as a main component, SiC
In the case of etching an insulating film formed by laminating a second insulating film containing silicon as a main component and a third insulating film containing silicon oxide as a main component using a masking layer made of a photoresist film as a mask, The flow rate of O ₂ gas contained in the etching gas when etching the third insulating film is relatively decreased, and the flow rate of O ₂ gas contained in the etching gas when etching the second insulating film is relatively increased. This allows the masking layer to remain after the etching step. That is, masking by the masking layer can be ensured during the etching process. (2) First insulating film mainly composed of silicon oxide, SiC
In a semiconductor integrated circuit device having a buried wiring formed in an insulating film formed by stacking a second insulating film containing silicon as a main component and a third insulating film containing silicon oxide as a main component, the semiconductor integrated circuit device has a function as an etching stopper layer. As compared with the case where the second insulating film is formed of a silicon nitride film, its capacitance can be relatively reduced, so that the speed of the signal flowing through the wiring can be increased.

[Brief description of drawings]

FIG. 1 is a main-portion cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 3 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 2;

FIG. 4 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 3;

5 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 6 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 5;

FIG. 7 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 6;

8 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

9 is a main-portion cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8;

FIG. 10 is an explanatory diagram showing the relationship between the flow rate of O ₂ gas contained in the etching gas and the etching rates of the SiC film, SiN film, SiO film, and photoresist film.

FIG. 11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 9;

12 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12;

FIG. 14 is an explanatory diagram showing the relationship between the relative permittivity of the etching stopper film and the capacitance in the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view showing the method of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

16 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 17 is a main-portion cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 16;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 17;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 18;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 19;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 20;

FIG. 22 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 21.

FIG. 23 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 22;

[Description of Reference Signs] 1 semiconductor substrate 2 element isolation groove 3 p-type well 4 n-type well 5 gate insulating film 6 gate electrode 7 n-type semiconductor region (source, drain) 8 p-type semiconductor region (source, drain) 9 interlayer insulation Film 10 Contact hole 11 Plug 12 Etching stopper film 13 Interlayer insulating film 14 Wiring groove 15 Embedded wiring 15A Barrier conductor film 15B Conductive film 16 Etching stopper film (fourth insulating film) 17 Insulating film (first insulating film) 18 Cap insulation Film (first insulating film) 19 Etching stopper film (second insulating film) 20 Insulating film (third insulating film) 21 Cap insulating film (third insulating film) 22 Etching stopper film (fifth insulating film) 23 Antireflection film 24 Photoresist Film (First Masking Layer) 25 Antireflection Film 25A Antireflection Film (Sixth Insulation Film) 26 Photoresist Film (masking layer, second masking layer) 26A Photoresist film (third masking layer) 27 Opening part (first opening part) 28 Opening part (first opening part) 29 Connection hole 30 Wiring groove 31 Embedded wiring 31A Barrier conductor film 31B Conductive film Qn n-channel type MISFET Qp p-channel type MISFET

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroyuki Enomoto             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center F-term (reference) 4M104 AA01 BB01 BB04 BB17 BB30                       BB31 BB40 CC01 DD08 DD15                       DD16 DD22 DD37 DD38 DD43                       DD52 DD53 DD72 DD75 DD78                       EE08 EE12 EE14 FF13 FF17                       FF18 FF22 GG09 GG10 GG14                       HH05 HH08 HH13 HH20                 5F004 CA02 DA01 DA02 DA03 DA15                       DA16 DA22 DA23 DA25 DA26                       DA30 DB03 DB12 EA22 EA23                       EB01 EB03                 5F033 HH04 HH11 HH12 HH19 HH21                       HH32 HH33 HH34 JJ01 JJ11                       JJ12 JJ19 JJ21 JJ32 JJ33                       KK01 KK11 KK12 KK21 KK32                       KK33 LL04 MM01 MM02 MM08                       MM12 MM13 NN06 NN07 PP06                       PP15 PP16 PP17 PP21 PP27                       PP28 PP33 QQ03 QQ04 QQ09                       QQ11 QQ14 QQ15 QQ25 QQ37                       QQ48 QQ58 QQ65 QQ73 QQ75                       QQ98 RR01 RR04 RR11 SS11                       SS15 TT02 WW06 XX02 XX13                       XX24 XX27 XX28

Claims (5)

[Claims] (A) A first insulating film containing silicon oxide as a main component, a second insulating film containing silicon carbide as a main component, and a third insulating film containing silicon oxide as a main component are formed on a semiconductor substrate from the lower layer. Stacking step, (b) forming a photosensitive masking layer on the third insulating film, and (c) using the masking layer as a mask, a first etching containing a fluorocarbon-based gas, an oxygen-based gas and an inert gas. Etching the third insulating film with a gas, (d) using the masking layer as a mask, and etching the second insulating film with a second etching gas containing a fluorocarbon-based gas, an oxygen-based gas, and an inert gas. Etching step, (e) the first insulating film using the masking layer as a mask and a first etching gas containing a fluorocarbon-based gas, an oxygen-based gas and an inert gas And a flow rate of the oxygen-based gas included in the first etching gas is relatively smaller than a flow rate of the oxygen-based gas included in the second etching gas, and the masking layer is formed after the step (e). A method of manufacturing a semiconductor integrated circuit device, characterized in that the flow rate is left. 2. (a) On a semiconductor substrate, a first insulating film containing silicon oxide as a main component, a second insulating film containing silicon carbide as a main component, and a third insulating film containing silicon oxide as a main component are formed from a lower layer on the semiconductor substrate. Stacking step, (b) forming a photosensitive masking layer on the third insulating film, and (c) using the masking layer as a mask, a first etching containing a fluorocarbon-based gas, an oxygen-based gas and an inert gas. Etching the third insulating film with a gas, (d) using the masking layer as a mask, and etching the second insulating film with a second etching gas containing a fluorocarbon-based gas, an oxygen-based gas, and an inert gas. Etching step, (e) the first insulating film using the masking layer as a mask and a first etching gas containing a fluorocarbon-based gas, an oxygen-based gas and an inert gas And a flow rate of the oxygen-based gas in the first etching gas is not more than 1.5 times the flow rate of the fluorocarbon-based gas,
The method for manufacturing a semiconductor integrated circuit device, wherein the flow rate of the oxygen-based gas in the second etching gas is 0.5 times or more the flow rate of the fluorocarbon-based gas. 3. (a) A fourth insulating film containing silicon carbide as a main component, a first insulating film containing silicon oxide as a main component, a second insulating film containing silicon carbide as a main component, from the lower layer on a semiconductor substrate. Stacking a third insulating film containing silicon oxide as a main component and a fifth insulating film containing silicon carbide as a main component,
(B) forming a photosensitive first masking layer on the fifth insulating film, (c) etching the fifth insulating film using the first masking layer as a mask, (d) the first masking A step of forming a photosensitive second masking layer on the third insulating film and the fifth insulating film after removing the layer; (e) using the second masking layer as a mask, a fluorocarbon-based gas, an oxygen-based gas, and Etching the third insulating film using a first etching gas containing an inert gas, (f) using the second masking layer as a mask,
A step of etching the second insulating film with a second etching gas containing a fluorocarbon-based gas, an oxygen-based gas and an inert gas; (g) using the second masking layer as a mask, the fluorocarbon-based gas, the oxygen-based gas and A step of etching the first insulating film using a first etching gas containing an inert gas to form a first opening, (h) the fifth insulating film remaining after removing the second masking layer Etching the third insulating film using the as a mask to form a first opening, (i) the second insulating film at the bottom of the first opening and the fourth opening at the bottom of the first opening. Removing the insulating film and forming a wiring groove and a connection hole, the flow rate of the oxygen-based gas included in the first etching gas is relatively smaller than the flow rate of the oxygen-based gas included in the second etching gas. , Serial (g) A method of manufacturing a semiconductor integrated circuit device, characterized in that said the flow leaving the masking layer after the step. 4. (a) A fourth insulating film containing silicon carbide as a main component, a first insulating film containing silicon oxide as a main component, a second insulating film containing silicon carbide as a main component, and Stacking a third insulating film containing silicon oxide as a main component, (b) forming a photosensitive second masking layer on the third insulating film, (c) using the second masking layer as a mask, A step of etching the third insulating film using a first etching gas containing a fluorocarbon-based gas, an oxygen-based gas and an inert gas; (d) using the second masking layer as a mask, a fluorocarbon-based gas, an oxygen-based gas and A step of etching the second insulating film using a second etching gas containing an inert gas; (e) a fluorocarbon-based gas using the second masking layer as a mask;
Etching the first insulating film with a first etching gas containing an oxygen-based gas and an inert gas to form a first opening, (f) after removing the second masking layer,
Forming a sixth insulating film filling the first opening on the third insulating film, (g) forming a photosensitive third masking layer on the sixth insulating film, (h) the Etching the sixth insulating film on the third insulating film using the third masking layer as a mask, (i) etching the third insulating film using the third masking layer as a mask, and opening the first opening. Forming step; (j) removing the third masking layer and the third insulating film filling the first opening; (k) the second insulating film at the bottom of the first opening; Removing the fourth insulating film at the bottom of the first opening to form a wiring groove and a connection hole, and the flow rate of the oxygen-based gas contained in the first etching gas is the second etching gas. Is relatively smaller than the flow rate of oxygen-containing gas contained in (E) The method of manufacturing a semiconductor integrated circuit device, characterized in that said the flow leaving the masking layer after the step. 5. A wiring formed on a main surface of a semiconductor substrate, and a fourth insulating film containing silicon carbide as a main component and a first insulating film containing silicon oxide as a main component from the lower layer on the wiring. A second insulating film containing silicon carbide as a main component and a third insulating film containing silicon oxide as a main component are formed, and wiring grooves for forming wiring are formed in the third insulating film and the second insulating film. A semiconductor integrated circuit device, wherein a connection hole reaching from the bottom of the wiring groove to the wiring is formed.