JP4582893B2

JP4582893B2 - Semiconductor substrate, method for manufacturing the same, and semiconductor element using the semiconductor substrate

Info

Publication number: JP4582893B2
Application number: JP2000340406A
Authority: JP
Inventors: 裕司小野; 栄吉吉田; 道夫根本; 英二山中
Original assignee: NEC Tokin Corp
Current assignee: Tokin Corp
Priority date: 2000-11-02
Filing date: 2000-11-02
Publication date: 2010-11-17
Anticipated expiration: 2020-11-02
Also published as: JP2002141252A

Description

【０００１】
【発明の属する技術分野】
本発明は、産業用乃至民生用の各種の半導体素子の製造に使用される半導体基板に関し、特に、ノイズ対策を施した電磁波吸収半導体基板及びその製造方法、並びに当該半導体基板を用いて製造される半導体素子に関する。
【０００２】
【従来の技術】
従来より、産業用乃至民生用の半導体素子は、いわゆるシリコンウエハ等の半導体基板上に個々の回路パターンを形成することにより製造されている。かかる半導体素子の形成に従来より使用されている半導体基板、及び当該半導体基板を用いて製造される半導体素子について、図６（ａ）及び（ｂ）を参照して説明する。図６に、従来の半導体基板の概観図を示す。図６（ａ）は平面図であり、図６（ｂ）は、図６（ａ）のＤＤ線における断面図である。
【０００３】
半導体基板１１Ｃは、材質をシリコンとしており、図６（ａ）及び（ｂ）での半導体基板１１Ｃは、半導体素子の製造工程の初期の状態を示す。半導体基板１１Ｃに、周知の各種半導体製造工程を施すことにより、上述した個々の半導体素子の回路パターンが形成された半導体基板となる。この半導体基板の最終形態を図７に示す。図７（ａ）は平面図であり、図７（ｂ）は、図７（ａ）のＥＥ線における断面図である。図７（ａ）及び（ｂ）にて、半導体基板１１Ｃにおける、個々の回路パターン領域２０１は、各半導体素子の機能部分に相当する。そして、半導体基板１１Ｃからそれぞれ回路パターン領域２０１を含む個々の半導体素子を切り出すことにより、各半導体素子が製作される。
【０００４】
図８は、半導体基板１１Ｃを切断後に完成された１個の半導体素子２００´の説明図である。図８（ａ）は、概観斜視図であり、図８（ｂ）は、図８（ａ）のＦＦ線における断面図である。
【０００５】
【発明が解決しようとする課題】
従来の半導体基板１１Ｃでは、基板そのものでは、ノイズ対策を行ってない。
そのため、図８（ａ）及び（ｂ）に示す半導体素子２００´を作成した後、半導体素子２００´の回路パターン領域２０１´からノイズが発生しても、このノイズは、そのまま外部に漏れていき、他のデバイス、装置を誤作動させる場合があった。
【０００６】
そこで半導体素子へのノイズ対策として、個々の半導体素子ごとに、半導体素子裏面に電磁波の吸収材料を塗布する等して、新たな電磁波吸収層を形成していた。図９は、従来の半導体素子でのノイズ対策例の説明図である。図９（ａ）は、ノイズ対策後の概観斜視図であり、図９（ｂ）は、図９（ａ）のＧＧ線における断面図である。即ち、この図９（ａ）及び（ｂ）に示す半導体素子２００ａ´では、半導体基板から個々の半導体素子を切り出した後、半導体素子２００ａ´裏面（回路パターン領域２０１´が形成されていない側の面）に電磁波の吸収材料２１０を塗布する等して、新たな電磁波吸収層を形成していた。
【０００７】
しかし、この従来の半導体素子２００ａ´のノイズ対策では、ノイズ吸収部材（電磁波の吸収材料２１０）を後工程にて、半導体素子２００ａ´の１個ごとに、その裏面に塗布するため、ノイズ対策のための工程に多大の時間を要するという問題点があった。また、半導体素子２００ａ´の１個ごと、その裏面に塗布することから、ノイズ吸収部材（電磁波の吸収材料２１０）の厚みには、ばらつきが生じやすく、個々の半導体素子のノイズ吸収特性にも、ばらつきが生ずるという問題点があった。
【０００８】
本発明は、上記のような種々の課題に鑑みなされたものであり、その目的は、ＭＨｚ帯域からＧＨｚ帯域までの妨害電磁波を効率良く吸収でき、個々の半導体素子に分割された時に、電磁波吸収の効果を示すことができ、ノイズ対策された半導体素子を量産することに優れた半導体基板及びその製造方法、並びに該半導体基板を用いた半導体素子を提供することにある。
【０００９】
【課題を解決するための手段】
上記目的達成のため、本発明の請求項１記載の半導体基板では、磁気損失部材が一部に形成されてなる半導体基板であって、前記磁気損失部材はＭ（Ｍは、Ｆｅ、Ｃｏ、Ｎｉのいずれか、若しくはそれらの混合物）−Ｘ（Ｘは、Ｍ及びＹ以外の元素、若しくはそれらの混合物）−Ｙ（Ｙは、Ｆ、Ｎ、Ｏのいずれか、若しくはそれらの混合物）から成り、前記半導体基板の半導体素子が形成される面と反対側の表面に所定パターンに形成されており、該磁気損失部材及び前記表面における半導体基板領域とが絶縁膜にて一様に被覆されていることを特徴とする。
【００１０】
また、請求項２記載の半導体基板においては、前記磁気損失部材は、半導体基板の略全面に形成されていることを特徴とする。更に、請求項３記載の半導体基板においては、前記磁気損失部材が形成される所定のパターンは、ストライプ状であることを特徴とする。
【００１１】
更にまた、請求項４記載の半導体基板においては、前記磁気損失部材が形成される所定のパターンは、格子状であることを特徴とする。尚、請求項５記載の半導体基板においては、前記磁気損失部材が形成される所定のパターンは、島状であることを特徴とする。
【００１２】
そして、請求項６記載の半導体基板においては、前記絶縁膜は、酸化シリコン、窒化シリコン、又は窒化酸化シリコンから成る群より選択される少なくとも一の材料から成ることを特徴とする。また、請求項７記載の半導体基板においては、前記磁気損失部材は、前記所定のパターンにて複数形成されており、該複数の磁気損失部材のそれぞれは、少なくとも当該半導体基板から個々に分割される各半導体素子の領域より狭い面積の領域に形成されていることを特徴とする。
【００１３】
一方、本発明の請求項８記載の半導体基板では、第１の半導体基板部材と、第２の半導体基板部材とが、半導体素子が形成されるのとは反対側の面で貼り合わされて形成され、磁気損失部材が一部に形成されてなる半導体基板であって、前記第１の半導体基板部材或いは前記第２の半導体基板部材のうち、少なくとも一方の半導体基板部材には、前記貼り合わされる側の面上にトレンチ部が形成されており、前記トレンチ部内にＭ（Ｍは、Ｆｅ、Ｃｏ、Ｎｉのいずれか、若しくはそれらの混合物）−Ｘ（Ｘは、Ｍ及びＹ以外の元素、若しくはそれらの混合物）−Ｙ（Ｙは、Ｆ、Ｎ、Ｏのいずれか、若しくはそれらの混合物）から成る前記磁気損失部材が埋め込まれていることを特徴とする。
【００１４】
また、請求項９記載の半導体基板においては、前記トレンチ部は、所定のパターンにて複数形成されており、該複数のトレンチ部のそれぞれは、少なくとも当該半導体基板から個々に分割される各半導体素子の領域より狭い面積の領域に形成されていることを特徴とする。
【００１５】
また、請求項１０記載の半導体基板においては、当該半導体基板及び、前記第１の半導体基板部材並びに前記第２の半導体基板部材の材質は、それぞれシリコンから成ることを特徴とする。更に、請求項１１記載の半導体基板においては、当該半導体基板及び、前記第１の半導体基板部材並びに前記第２の半導体基板部材の材質は、それぞれガリウム砒素から成ることを特徴とする。
【００１６】
一方、本発明の請求項１２記載の半導体素子では、請求項１乃至１１のいずれかに記載の半導体基板上に所定のパターン状に繰り返し形成された複数の半導体素子であって、前記複数の半導体素子の各々は、前記磁気損失部材が形成された単位領域の少なくともひとつを含むことを特徴とする。
【００１７】
また一方、本発明の請求項１３記載の半導体基板の製造方法では、磁気損失部材を一部に形成する半導体基板の製造方法であって、Ｍ（Ｍは、Ｆｅ、Ｃｏ、Ｎｉのいずれか、若しくはそれらの混合物）−Ｘ（Ｘは、Ｍ及びＹ以外の元素、若しくはそれらの混合物）−Ｙ（Ｙは、Ｆ、Ｎ、Ｏのいずれか、若しくはそれらの混合物）から成る前記磁気損失部材を、前記半導体基板の半導体素子が形成される面と反対側の表面に、所定パターン、所定の膜厚にて形成する第１の工程と、該第１の工程の後、前記磁気損失部材及び前記表面における半導体基板領域を絶縁膜にて一様に被覆する第２の工程とを有することを特徴とする。
【００１８】
しかして、本発明の請求項１４記載の半導体基板の製造方法では、少なくとも第１の半導体基板部材にトレンチ構造を形成し、該トレンチ構造内に磁気損失部材を形成した後、前記第１の半導体基板部材の前記トレンチ構造を形成した面に第２の半導体基板部材を貼り合わせて半導体基板を製造する半導体基板の製造方法であって、
前記第１の半導体基板部材に絶縁膜パターンを形成する工程と、該絶縁膜パターンを形成した後、前記第１の半導体基板部材にエッチング処理を施して、所定の深さ前記トレンチ構造を形成する工程と、該トレンチ構造を形成した後、前記第１の半導体基板部材から前記絶縁膜パターンを除去する工程と、該絶縁膜パターンを除去した後、前記第１の半導体基板部材に一様にＭ（Ｍは、Ｆｅ、Ｃｏ、Ｎｉのいずれか、若しくはそれらの混合物）−Ｘ（Ｘは、Ｍ及びＹ以外の元素、若しくはそれらの混合物）−Ｙ（Ｙは、Ｆ、Ｎ、Ｏのいずれか、若しくはそれらの混合物）から成る磁気損失部材を成膜させる工程と、該磁気損失部材を成膜させた後、前記トレンチ構造以外の領域の基板面が露出するように前記第１の半導体基板部材の全面に研磨処理を施す工程と、該研磨処理を施した前記第１の半導体基板部材に前記第２の半導体基板部材を密着させて、貼り合わせ処理を施す工程とを有することを特徴とする。
【００１９】
また、本発明の請求項１５記載の半導体基板の製造方法では、少なくとも第１の半導体基板部材にトレンチ構造を形成し、該トレンチ構造内に磁気損失部材を形成した後、前記第１の半導体基板部材の前記トレンチ構造を形成した面に第２の半導体基板部材を貼り合わせて半導体基板を製造する半導体基板の製造方法であって、
前記第１の半導体基板部材に絶縁膜パターンを形成する工程と、該絶縁膜パターンを形成した後、前記第１の半導体基板部材にエッチング処理を施して、所定の深さ前記トレンチ構造を形成する工程と、該トレンチ構造を形成した後、前記第１の半導体基板部材から前記絶縁膜パターンを除去する工程と、該絶縁膜パターンを除去した後、前記第１の半導体基板部材に一様にＭ（Ｍは、Ｆｅ、Ｃｏ、Ｎｉのいずれか、若しくはそれらの混合物）−Ｘ（Ｘは、Ｍ及びＹ以外の元素、若しくはそれらの混合物）−Ｙ（Ｙは、Ｆ、Ｎ、Ｏのいずれか、若しくはそれらの混合物）から成る磁気損失部材を成膜させる工程と、該磁気損失部材を成膜させた後、前記トレンチ構造以外の領域の基板面が露出するように前記第１の半導体基板部材の全面に研磨処理を施す工程と、前記トレンチ構造を形成していない第２の半導体基板部材の前記第１の半導体基板部材と対向する面の全面を熱酸化させる工程と、該対向面を熱酸化させた前記第２の半導体基板部材を前記第１の半導体基板部材に、静電接合によって貼り合わせる処理を施す工程とを有することを特徴とする。
【００２０】
尚、請求項１６記載の半導体基板の製造方法においては、当該半導体基板及び、前記第１の半導体基板部材並びに前記第２の半導体基板部材の材質は、それぞれシリコンから成ることを特徴とする。
【００２１】
更に、請求項１７記載の半導体基板の製造方法においては、当該半導体基板及び、前記第１の半導体基板部材並びに前記第２の半導体基板部材の材質は、それぞれガリウム砒素から成ることを特徴とする。
【００２２】
【発明の実施の形態】
以下、図面に基づいて、本発明の実施の形態に係る半導体基板及びその製造方法、並びに当該半導体基板を用いた半導体素子について説明する。図１は、本発明の第１の実施形態に係る半導体基板を説明するための図である。図１（ａ）は、本実施形態の半導体基板の平面図を、図１（ｂ）は、図１（ａ）のＡＡ線における断面図を示す。また、図２は、本実施形態による半導体基板の製造方法を説明するための図である。
【００２３】
図１（ａ）及び（ｂ）に示す半導体基板１０１は、シリコン基板１の上に、所定の領域にてパターン化された磁気損失部材２が形成され、全体が絶縁膜３に覆われている。また、図１（ｂ）に示すように、本実施形態の半導体基板１０１において、半導体素子が形成される面は、磁気損失部材２が形成された面と反対側の面である。尚、シリコン基板１は、最終形態品となる各種半導体素子に対応して、所定の不純物濃度に設定されている。
【００２４】
また、磁気損失部材２の材質は、Ｍ（Ｍは、Ｆｅ、Ｃｏ、Ｎｉのいずれか、若しくはそれらの混合物）−Ｘ（Ｘは、Ｍ及びＹ以外の元素、若しくはそれらの混合物）−Ｙ（Ｙは、Ｆ、Ｎ、Ｏのいずれか、若しくはそれらの混合物）から成り、例えば、磁気損失部材２の組成は、Ｆｅ₇₂、Ａｌ₁₁、Ｏ₁₇に設定されるものである。かかる組成の磁気損失部材は、特にＭＨｚ帯の電磁波から、ＧＨｚ帯の電磁波までの吸収特性が優れており、シリコン基板１上に形成される各種半導体素子から発生する上記帯域の電磁波を効率良く吸収するものである。
【００２５】
また、上記組成の磁気損失部材２は、電磁波吸収による極めて大きな磁気損失を示す配合であるため、その分、磁気損失部材２の厚みを格段に薄くすることができる。これにより、磁気損失部材２の厚みは、数１０ミクロン以下にすることができる。
【００２６】
さて、本実施形態の半導体基板１０１を用いて製作した半導体素子に関して、磁気損失部材２による電磁波の吸収特性を調べてみた。その結果、電磁波対策を行わない、従来の半導体基板（例えば、図６（ａ）及び（ｂ）に示す半導体基板１１Ｃ）を用いた半導体素子の場合に比較して、磁気損失部材２により、約３ＧＨｚの周波数において、略１０デシベル程度の電磁波の吸収効果が得られた。
【００２７】
また、磁気損失部材２をシリコン基板１上に形成する方法としては、まず、例えば、スパッタ法或いは蒸着法を用いて、シリコン基板１の上述した半導体素子が形成される面と反対側の全面に磁気損失部材２の層を形成し、その後、リソグラフィ法によって、ストライプ状、格子状、島状等の所定のパターン形状の磁気損失部材２を形成する。尚、シリコン基板１上に磁気損失部材２の層を形成するには、上記スパッタ法及び蒸着法以外の製膜法、例えば、化学気相成長法（ＣＶＤ法）等を用いても良い。尚、絶縁膜３の材質は、酸化シリコン、窒化シリコン、或いは、窒化酸化シリコンのいずれかとするものである。また、磁気損失部材２のそれぞれは、少なくとも半導体基板１０１から個々に分割される各半導体素子領域［その一辺の長さを図１（ａ）にＬ₁で示す］より狭い面積の領域に形成されている。
【００２８】
ここで、本実施形態の半導体基板１０１の製造方法を説明する。本実施形態の半導体基板１０１を製造するには、まず、図２（ａ）に示すように、シリコン基板１の上述した半導体素子が形成される面と反対側の面に、上述したスパッタ法或いは蒸着法等を用いて、磁気損失部材の層２´を全面に形成する。
【００２９】
次に、この磁気損失部材の層２´から、上述したリソグラフィ法を用いて所定のパターン形状の磁気損失部材２を形成する。即ち、図２（ｂ）に示すように、磁気損失部材の層２´上にレジストパターン７を形成し、続いて、図２（ｃ）に示すように、図２（ｂ）で磁気損失部材の層２´のレジストパターン７が付加された部分のみ残して、磁気損失部材２を上述したストライプ状、格子状、島状等の所定のパターン形状に形成する。
【００３０】
この後、図２（ｄ）に示すように、シリコン基板１の、図２（ｃ）で磁気損失部材２のパターンを形成した面を、上述した酸化シリコン、窒化シリコン、或いは、窒化酸化シリコンから成る絶縁膜３にて被覆する。これにより、図２（ｄ）に示す本実施形態の半導体基板１０１が完成する。
【００３１】
この半導体基板１０１の磁気損失部材２が形成された面と反対側の面の個々の領域ごとに、各半導体素子の回路パターンが形成され、当該個々の領域を切り出して各半導体素子が製造される。尚、上述したように、磁気損失部材２をストライプ状、格子状、島状等に形成した場合、半導体素子の各々は磁気損失部材２が形成された単位領域の少なくともひとつを含むものとする。
【００３２】
本実施形態によれば、いわば基板そのものの段階でノイズ対策を行うので、ノイズ対策された半導体素子を量産することに優れた技術を提供し得る。即ち、この半導体基板１０１を用いて各半導体素子を製造すれば、半導体素子からノイズが発生しても、このノイズは、そのまま外部に漏れることなく、半導体素子裏面に形成された磁気損失部材２に吸収される。その結果、他のデバイス、装置を誤作動させることが無い。また、ノイズ吸収部材を後工程にて、半導体素子の１個ごとに、その裏面に塗布する等してノイズ対策を行う従来例に比べて、ノイズ対策のための工程に多くの時間を必要としない。更に、半導体基板１０１上の個々の半導体素子形成領域の裏面に、磁気損失部材２を同一工程にて形成することから、磁気損失部材２（ノイズ吸収部材）の厚みにも、ばらつきを生じにくく、従って、個々の半導体素子のノイズ吸収特性に、ばらつきを生ずることを防止できる。
【００３３】
図３は、本発明の第２の実施形態に係る半導体基板を説明するための図である。図３（ａ）は、本実施形態の半導体基板の平面図を、図３（ｂ）は、図３（ａ）のＢＢ線における断面図を示す。また、図４は、本実施形態による半導体基板の製造方法を説明するための図である。
【００３４】
図３（ａ）及び（ｂ）に示す半導体基板１０２は、第１のシリコン基板１１ａと、第２のシリコン基板１１ｂとが、シリコン基板どうしの貼り合わせ、あるいは静電接合によって貼り合わされている。ここで、第１のシリコン基板１１ａには、所定のパターンにてトレンチ部４が形成されており、各トレンチ部４の内部には、磁気損失部材２１が埋め込まれて形成されている。
【００３５】
ここで、図３（ｂ）に示すように、半導体基板１０２における半導体素子の形成面は、第１のシリコン基板１１ａに対応する（半導体素子形成の）第１の面と、第２のシリコン基板１１ｂに対応する（半導体素子形成の）第２の面のどちらでも良い。尚、各シリコン基板１１ａ又は１１ｂは、最終的に作製される半導体素子に対応して、あらかじめ所定の不純物濃度に設定される。
【００３６】
また、磁気損失部材２１の材質は、Ｍ（Ｍは、Ｆｅ、Ｃｏ、Ｎｉのいずれか、若しくはそれらの混合物）−Ｘ（Ｘは、Ｍ及びＹ以外の元素、若しくはそれらの混合物）−Ｙ（Ｙは、Ｆ、Ｎ、Ｏのいずれか、若しくはそれらの混合物）から成り、例えば、磁気損失部材２１の組成は、Ｆｅ₇₂、Ａｌ₁₁、Ｏ₁₇に設定されるものである。かかる組成の磁気損失部材は、特にＭＨｚ帯の電磁波から、ＧＨｚ帯の電磁波までの吸収特性が優れており、第１のシリコン基板１１ａ上、又は第２のシリコン基板１１ｂ上に形成される各種半導体素子から発生する上記帯域の電磁波を効率良く吸収する。また、上記組成の磁気損失部材２１は、電磁波吸収による極めて大きな磁気損失を示す配合であるため、その分、磁気損失部材２１の厚みを、数１０ミクロン以下というように、格段に薄くすることができる。従って、トレンチ部４の深さは、数１０ミクロン程度に設定される。尚、トレンチ部４のそれぞれは、少なくとも半導体基板１０２から個々に分割される各半導体素子領域［その一辺の長さを図３（ａ）にＬ₂で示す］より狭い面積の領域に形成されている。更に、図３（ｂ）に示す第１のシリコン基板１１ａの厚みｔ₁と第２のシリコン基板１１ｂの厚みｔ₂は、以下のふたつの条件を満足するように適宜設定すれば良い。即ち、一つは、ｔ₁＋ｔ₂にて所望の厚さを有する半導体基板が得られることであり、二つは、第１のシリコン基板１１ａ及び第２のシリコン基板１１ｂにそれぞれ形成される半導体素子のノイズ耐性及びノイズ発生量に対応した最適な位置に磁気損失部材２１が配置されるように、ｔ₁、ｔ₂、及びトレンチ部４の深さが設定されることである。
【００３７】
ここで、本実施形態の半導体基板１０２の製造方法を説明する。
【００３８】
本実施形態の半導体基板１０２を製造するには、まず、図４（ａ）に示すように、第１のシリコン基板１１ａに、酸化シリコン３１のパターンを形成した後、第１のシリコン基板１１ａをドライエッチングする。その結果、第１のシリコン基板１１ａにおける酸化シリコン３１のパターン部分以外のシリコンの露出部分がエッチングされ、図４（ｂ）に示すように、所定の深さＬ１のトレンチ部４１のパターンが形成される。続いて、図４（ｃ）に示すように、酸化シリコン３１を除去してトレンチ部４１を持ったシリコン基板面を露出させる。次に、図４（ｄ）に示すように、図４（ｃ）で露出させた、第１のシリコン基板１１ａのトレンチ部４１を含む片側面の全面に磁気損失部材の層２１´を形成する。尚、この磁気損失部材の層２１´を形成する方法としては、上述した第１の実施形態と同様に、スパッタ法、蒸着法、或いは化学気相成長法（ＣＶＤ法）等の製膜法を用いる。
【００３９】
続いて、図４（ｅ）に示すように、図４（ｄ）で磁気損失部材の層２１´を形成した第１のシリコン基板１１ａの片側面を研磨処理して、シリコン基板面と、磁気損失部材の層２１´のトレンチ部４１内に埋入した部分を露出させた状態とする。この結果、図４（ｅ）に示すように、第１のシリコン基板１１ａ上のトレンチ部４１のパターンに対応して、磁気損失部材２１が形成される。
【００４０】
更に、図４（ｆ）に示すように、上述した第２のシリコン基板１１ｂを用意し、図４（ｇ）に示すように、第１のシリコン基板１１ａの図４（ｅ）で研磨処理した面側に貼り合わせる。尚、図４（ｆ）において、第２のシリコン基板１１ｂは、予め第１のシリコン基板１１ａと対向する面の全面を熱酸化させておく。そして、第２のシリコン基板１１ｂの熱酸化させた対向面を第１のシリコン基板１１ａに、静電接合によって貼り合わせる。これにより、図４（ｇ）に示す、第１のシリコン基板１１ａと第２のシリコン基板１１ｂとが貼り合わされた半導体基板１０２が製作される。尚、図４（ｇ）において、１００は、貼り合わせの境界面を示す。この図４（ｇ）の半導体基板１０２が、本実施形態の半導体基板の完成状態である。
【００４１】
尚、図４（ａ）に示した酸化シリコン３１を形成するパターンに応じて、トレンチ部４１のパターンが決定されるから、このトレンチ部４１内に埋め込まれる磁気損失部材２１のパターンが、ストライプ状、格子状、島状等の所定のパターンになるように、上記酸化シリコン３１のパターンを形成すれば良い。また、本実施形態では、第１のシリコン基板１１ａの磁気損失部材２１が埋入形成された面側に第２のシリコン基板１１ｂを貼り合わせるので、上述した第１の実施形態と異なり、磁気損失部材２１の形成面を酸化シリコン等の絶縁膜にて被覆することは不要である。
【００４２】
さて、上述したように、本実施形態の半導体基板１０２においては、第１のシリコン基板１１ａに対応する（半導体素子形成の）第１の面と、第２のシリコン基板１１ｂに対応する（半導体素子形成の）第２の面のどちらにも、半導体素子を形成することができる。そして、これら第１又は第２の面の個々の領域ごとに、各半導体素子の回路パターンが形成され、当該個々の領域を切り出して各半導体素子が製造される。尚、上述したように、磁気損失部材２１をストライプ状、格子状、島状等に形成した場合、半導体素子の各々は磁気損失部材２１が形成された単位領域の少なくともひとつを含むものとする。
【００４３】
本実施形態によっても、基板そのものの段階でノイズ対策を行うので、ノイズ対策された半導体素子を量産することに優れた技術を提供し得る。即ち、この半導体基板１０２を用いて各半導体素子を製造すれば、半導体素子からノイズが発生しても、このノイズは、そのまま外部に漏れることなく、半導体素子の内部に埋入形成された磁気損失部材２１に吸収される。その結果、他のデバイス、装置を誤作動させることが無い。また、ノイズ吸収部材を後工程にて、半導体素子の１個ごとに、その裏面に塗布する等してノイズ対策を行う従来例に比べて、ノイズ対策のための工程に多くの時間を必要としない。更に、半導体基板１０２の個々の半導体素子形成領域に対応した箇所の内部に磁気損失部材２１を同一工程にて形成し得るので、磁気損失部材２１（ノイズ吸収部材）の厚みにも、ばらつきを生じにくく、従って、個々の半導体素子のノイズ吸収特性に、ばらつきを生ずることを防止できる。
【００４４】
図５は、本発明の第２の実施形態に係る半導体基板１０２を用いて製作された本発明の第３の実施形態に係る半導体素子を説明するための図である。
【００４５】
図５（ａ）は、本実施形態の半導体素子の外観斜視図を、図５（ｂ）は、図５（ａ）のＣＣ線における断面図を示す。
【００４６】
図５（ａ）及び（ｂ）に示すように、本発明の第３の実施形態に係る半導体素子２００は、磁気損失部材２１ａが埋め込まれた第１のシリコン基板１１ａ´と第２のシリコン基板１１ｂ´とが貼り合わされて形成され、第２のシリコン基板１１ｂ´の表面の近傍に、回路パターン領域２０１ａが形成されている。
【００４７】
本実施形態の半導体素子２００では、その構造上、回路パターン領域２０１ａ近傍から発生したノイズの電磁波が、効率良く、磁気損失部材２１ａにて吸収される。そこで、本実施形態の半導体素子２００による電磁波の吸収特性を調べてみたところ、約３ＧＨｚの周波数において、図８に示した従来のノイズ対策なしの半導体素子と比較した場合、約１０デシベル程度の電磁波の吸収効果が得られた。また、本実施形態の半導体素子２００による電磁波の吸収特性は、約３ＧＨｚの周波数において、図９に示した従来のノイズ対策を施した半導体素子と比較した場合でも、約７デシベル程度の電磁波の吸収効果が得られた。
【００４８】
以上、本発明を種々の実施形態に関して述べたが、本発明は以上の実施形態に限られるものではなく、特許請求の範囲に記載された発明の範囲内で、他の実施形態についても適用されるのは勿論である。
【００４９】
例えば、上述した実施形態では、半導体基板の材質をシリコンとしたが、シリコン以外でも同様の効果が得られる。シリコン以外の材質としては、ガリウム砒素系部材、或いはシリコン−ゲルマニウム系部材が挙げられる。
【００５０】
【発明の効果】
以上、本発明によれば、ＭＨｚ帯域からＧＨｚ帯域までの妨害電磁波を効率良く吸収でき、個々のデバイスに分割されたときに、ノイズ吸収の効果を示すことができ、デバイス作製に対して、量産性の優れた半導体基板及びその製造方法、並びに当該半導体基板を用いた半導体素子を提供することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る半導体基板を説明するための図であり、図１（ａ）は、本実施形態の半導体基板の平面図、図１（ｂ）は、図１（ａ）のＡＡ線における断面図を示す。
【図２】本発明の第１の実施形態による半導体基板の製造方法を説明するための図であり、図２（ａ）は、シリコン基板１に、磁気損失部材の層２´を全面に形成した状態を示し、図２（ｂ）は、磁気損失部材の層２´でのレジストパターン７を形成した状態を示し、図２（ｃ）は、図２（ｂ）での磁気損失部材の層２´のレジストパターン７が付加された部分のみ残して、所定のパターンを持つ磁気損失部材２を形成した状態を示し、図２（ｄ）は、図２（ｃ）での磁気損失部材２を形成した面を絶縁膜３にて覆った状態を示す。
【図３】本発明の第２の実施形態に係る半導体基板を説明するための図であり、図３（ａ）は、本実施形態の半導体基板の平面図、図３（ｂ）は、図３（ａ）のＢＢ線における断面図を示す。
【図４】本発明の第２の実施形態による半導体基板の製造方法を説明するための図であり、図４（ａ）は、第１のシリコン基板に、酸化シリコン３１のパターンを形成し、シリコンの露出部分を、ドライエッチングしている状態を示し、図４（ｂ）は、所定の深さＬ１のトレンチ部４１を形成した状態を示し、図４（ｃ）は、酸化シリコン３１を除去してトレンチ部４１を持ったシリコン基板面を露出させた状態を示し、図４（ｄ）は、図４（ｃ）の基板の片側面の全面に磁気損失部材の層２１´を形成した状態を示し、図４（ｅ）は、片側を研磨処理して、シリコン基板面と、トレンチ部４内の磁気損失部材２１を露出させた状態を示し、図４（ｆ）は、第２のシリコン基板を用意し、第１のシリコン基板に貼り合わせる直前の状態を示し、図４（ｇ）は、第１のシリコン基板と第２のシリコン基板とを貼り合わせた状態を示す。
【図５】本発明の第３の実施形態に係る半導体素子を説明するための図であり、図５（ａ）は、本実施形態の半導体素子の外観斜視図を、図５（ｂ）は、図５（ａ）のＣＣ線における断面図を示す。
【図６】従来の半導体基板の概観図を示し、図６（ａ）は平面図、図６（ｂ）は、図６（ａ）のＤＤ線における断面図である。
【図７】従来の半導体基板に、各種の半導体製造工程を実施した後の半導体基板の最終形態を示し、図７（ａ）は平面図、図７（ｂ）は、図７（ａ）のＥＥ線における断面図である。
【図８】従来の半導体基板を切断後に完成された１個の半導体素子の説明図であり、図８（ａ）は、概観斜視図、図８（ｂ）は、図８（ａ）のＦＦ線における断面図である。
【図９】従来の半導体素子でのノイズ対策例の説明図であり、図９（ａ）は、ノイズ対策後の概観斜視図、図９（ｂ）は、図９（ａ）のＧＧ線における断面図である。
【符号の説明】
１シリコン基板
１１ａ第１のシリコン基板
１１ｂ第２のシリコン基板
１０１、１０２半導体基板
２、２１、２１ａ、２１’ 磁気損失部材
３絶縁膜
３１酸化シリコン
４、４１トレンチ部
７レジストパターン
１００シリコン基板貼り合わせの境界面
２００、２００´ 半導体素子
２０１回路パターン領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor substrate used for manufacturing various industrial or consumer semiconductor devices, and in particular, an electromagnetic wave absorbing semiconductor substrate with noise countermeasures, a manufacturing method thereof, and the semiconductor substrate. The present invention relates to a semiconductor element.
[0002]
[Prior art]
Conventionally, industrial or consumer semiconductor devices have been manufactured by forming individual circuit patterns on a semiconductor substrate such as a so-called silicon wafer. A semiconductor substrate conventionally used for forming such a semiconductor element and a semiconductor element manufactured using the semiconductor substrate will be described with reference to FIGS. FIG. 6 shows an overview of a conventional semiconductor substrate. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along line DD in FIG. 6A.
[0003]
The semiconductor substrate 11C is made of silicon, and the semiconductor substrate 11C in FIGS. 6A and 6B shows an initial state of the semiconductor element manufacturing process. By subjecting the semiconductor substrate 11C to various known semiconductor manufacturing processes, the semiconductor substrate on which the circuit patterns of the individual semiconductor elements described above are formed is obtained. The final form of this semiconductor substrate is shown in FIG. FIG. 7A is a plan view, and FIG. 7B is a cross-sectional view taken along the line EE in FIG. 7A and 7B, each circuit pattern region 201 in the semiconductor substrate 11C corresponds to a functional portion of each semiconductor element. Then, each semiconductor element is manufactured by cutting out each semiconductor element including the circuit pattern region 201 from the semiconductor substrate 11C.
[0004]
FIG. 8 is an explanatory diagram of one semiconductor element 200 ′ completed after cutting the semiconductor substrate 11C. 8A is an overview perspective view, and FIG. 8B is a cross-sectional view taken along line FF in FIG. 8A.
[0005]
[Problems to be solved by the invention]
In the conventional semiconductor substrate 11C, the substrate itself does not take measures against noise.
Therefore, even if noise is generated from the circuit pattern region 201 ′ of the semiconductor element 200 ′ after the semiconductor element 200 ′ shown in FIGS. 8A and 8B is created, this noise leaks to the outside as it is. Other devices and devices may malfunction.
[0006]
Therefore, as a noise countermeasure for the semiconductor element, a new electromagnetic wave absorbing layer is formed for each individual semiconductor element by applying an electromagnetic wave absorbing material to the back surface of the semiconductor element. FIG. 9 is an explanatory diagram of an example of noise countermeasures in a conventional semiconductor element. FIG. 9A is a schematic perspective view after noise countermeasures, and FIG. 9B is a cross-sectional view taken along the line GG in FIG. 9A. That is, in the semiconductor element 200a ′ shown in FIGS. 9A and 9B, after the individual semiconductor elements are cut out from the semiconductor substrate, the back surface of the semiconductor element 200a ′ (the side where the circuit pattern region 201 ′ is not formed). A new electromagnetic wave absorbing layer was formed by applying an electromagnetic wave absorbing material 210 on the surface).
[0007]
However, in the noise countermeasure of the conventional semiconductor element 200a ′, the noise absorbing member (electromagnetic wave absorbing material 210) is applied to the back surface of each semiconductor element 200a ′ in the subsequent process, so that noise countermeasures are taken. Therefore, there is a problem that it takes a lot of time for the process. Further, since each semiconductor element 200a ′ is applied to the back surface thereof, the thickness of the noise absorbing member (electromagnetic wave absorbing material 210) is likely to vary, and the noise absorbing characteristics of the individual semiconductor elements are also There was a problem that variations occurred.
[0008]
The present invention has been made in view of the various problems as described above, and its purpose is to efficiently absorb disturbing electromagnetic waves from the MHz band to the GHz band and absorb the electromagnetic waves when divided into individual semiconductor elements. It is an object of the present invention to provide a semiconductor substrate excellent in mass-producing semiconductor elements with noise suppression, a method for manufacturing the same, and a semiconductor element using the semiconductor substrate.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor substrate according to claim 1 of the present invention is a semiconductor substrate in which a magnetic loss member is partially formed, and the magnetic loss member isM (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, or a mixture thereof) -Y (Y is any of F, N, O) Or a mixture thereof)A surface of the semiconductor substrate on which a semiconductor element is formed;On the opposite surfaceFormed in a predetermined patternAnd theMagnetic loss member and said surfaceInThe semiconductor substrate region is uniformly covered with an insulating film.
[0010]
According to a second aspect of the present invention, the magnetic loss member is formed on substantially the entire surface of the semiconductor substrate. Further, in the semiconductor substrate according to claim 3, the predetermined pattern on which the magnetic loss member is formed is a stripe shape.
[0011]
Furthermore, the semiconductor substrate according to claim 4 is characterized in that the predetermined pattern on which the magnetic loss member is formed is in a lattice shape. The semiconductor substrate according to claim 5 is characterized in that the predetermined pattern on which the magnetic loss member is formed is an island shape.
[0012]
The semiconductor substrate according to claim 6 is characterized in that the insulating film is made of at least one material selected from the group consisting of silicon oxide, silicon nitride, or silicon nitride oxide. The semiconductor substrate according to claim 7, wherein a plurality of the magnetic loss members are formed in the predetermined pattern, and each of the plurality of magnetic loss members is individually divided from at least the semiconductor substrate. It is characterized by being formed in a region having a smaller area than the region of each semiconductor element.
[0013]
On the other hand, in the semiconductor substrate according to claim 8 of the present invention, the first semiconductor substrate member and the second semiconductor substrate member are:On the side opposite to where the semiconductor elements are formedA semiconductor substrate formed by bonding and having a magnetic loss member formed in part, and at least one of the first semiconductor substrate member and the second semiconductor substrate member includes: A trench portion is formed on the surface to be bonded, and the trench portionM (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, or a mixture thereof) -Y (Y is any of F, N, O) Or a mixture thereof)The magnetic loss member is embedded.
[0014]
The semiconductor substrate according to claim 9, wherein a plurality of the trench portions are formed in a predetermined pattern, and each of the plurality of trench portions is individually divided at least from the semiconductor substrate. It is characterized in that it is formed in a region having a smaller area than this region.
[0015]
Claims10The semiconductor substrate described above is characterized in that the semiconductor substrate, the first semiconductor substrate member, and the second semiconductor substrate member are each made of silicon. Further claims11In the semiconductor substrate described above, the materials of the semiconductor substrate, the first semiconductor substrate member, and the second semiconductor substrate member are each made of gallium arsenide.
[0016]
Meanwhile, the claims of the present invention1212. The semiconductor element according to claim 1, wherein the semiconductor element is a plurality of semiconductor elements repeatedly formed in a predetermined pattern on the semiconductor substrate according to any one of claims 1 to 11, wherein each of the plurality of semiconductor elements includes the magnetic loss. It includes at least one unit region in which the member is formed.
[0017]
Meanwhile, the claims of the present invention13In the manufacturing method of a semiconductor substrate described, a semiconductor substrate manufacturing method in which a magnetic loss member is formed in part,M (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, or a mixture thereof) -Y (Y is any of F, N, O) Or a mixture thereof)A first step of forming the magnetic loss member on a surface of the semiconductor substrate opposite to a surface on which a semiconductor element is formed, with a predetermined pattern and a predetermined film thickness; and after the first step, Magnetic loss memberAnd a semiconductor substrate region on the surfaceAnd a second step of uniformly covering the substrate with an insulating film.
[0018]
Thus, the claims of the present invention14In the semiconductor substrate manufacturing method described above, after forming a trench structure in at least a first semiconductor substrate member and forming a magnetic loss member in the trench structure, the first semiconductor substrate memberOn the surface where the trench structure is formedA semiconductor substrate manufacturing method for manufacturing a semiconductor substrate by bonding a second semiconductor substrate member,
Forming an insulating film pattern on the first semiconductor substrate member; and after forming the insulating film pattern, the first semiconductor substrate member is etched to form the trench structure having a predetermined depth. A step of removing the insulating film pattern from the first semiconductor substrate member after forming the trench structure; and after removing the insulating film pattern, uniformly on the first semiconductor substrate memberM (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, or a mixture thereof) -Y (Y is any of F, N, O) Or a mixture thereof)A step of forming a magnetic loss member; and a step of polishing the entire surface of the first semiconductor substrate member so that the substrate surface in a region other than the trench structure is exposed after forming the magnetic loss member. And a step of bringing the second semiconductor substrate member into close contact with the first semiconductor substrate member subjected to the polishing process and performing a bonding process.
[0019]
Further, the claims of the present invention15In the semiconductor substrate manufacturing method described above, after forming a trench structure in at least a first semiconductor substrate member and forming a magnetic loss member in the trench structure, the first semiconductor substrate memberOn the surface where the trench structure is formedA semiconductor substrate manufacturing method for manufacturing a semiconductor substrate by bonding a second semiconductor substrate member,
Forming an insulating film pattern on the first semiconductor substrate member; and after forming the insulating film pattern, the first semiconductor substrate member is etched to form the trench structure having a predetermined depth. A step of removing the insulating film pattern from the first semiconductor substrate member after forming the trench structure; and after removing the insulating film pattern, uniformly on the first semiconductor substrate memberM (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, or a mixture thereof) -Y (Y is any of F, N, O) Or a mixture thereof)A step of forming a magnetic loss member; and a step of polishing the entire surface of the first semiconductor substrate member so that the substrate surface in a region other than the trench structure is exposed after forming the magnetic loss member. And a step of thermally oxidizing the entire surface of the second semiconductor substrate member that does not form the trench structure that faces the first semiconductor substrate member, and the second semiconductor in which the facing surface is thermally oxidized. And a step of performing a process of bonding the substrate member to the first semiconductor substrate member by electrostatic bonding.
[0020]
still,The method of manufacturing a semiconductor substrate according to claim 16 is characterized in that the semiconductor substrate, the first semiconductor substrate member, and the second semiconductor substrate member are made of silicon.
[0021]
Further claims17In the semiconductor substrate manufacturing method described above, the materials of the semiconductor substrate, the first semiconductor substrate member, and the second semiconductor substrate member are each composed of gallium arsenide.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, based on the drawings, a semiconductor substrate according to an embodiment of the present invention, a manufacturing method thereof, and a semiconductor element using the semiconductor substrate will be described. FIG. 1 is a diagram for explaining a semiconductor substrate according to a first embodiment of the present invention. FIG. 1A is a plan view of the semiconductor substrate of the present embodiment, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. FIG. 2 is a view for explaining the semiconductor substrate manufacturing method according to the present embodiment.
[0023]
A semiconductor substrate 101 shown in FIGS. 1A and 1B has a magnetic loss member 2 patterned in a predetermined region on a silicon substrate 1 and is entirely covered with an insulating film 3. . Further, as shown in FIG. 1B, in the semiconductor substrate 101 of the present embodiment, the surface on which the semiconductor element is formed is the surface opposite to the surface on which the magnetic loss member 2 is formed. In addition, the silicon substrate 1 is set to a predetermined impurity concentration corresponding to various semiconductor elements that are final forms.
[0024]
The material of the magnetic loss member 2 is M (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, or a mixture thereof) -Y ( Y is made of F, N, O, or a mixture thereof. For example, the composition of the magnetic loss member 2 is Fe₇₂, Al₁₁, O₁₇Is set to The magnetic loss member having such a composition has particularly excellent absorption characteristics from an electromagnetic wave in the MHz band to an electromagnetic wave in the GHz band, and efficiently absorbs the electromagnetic wave in the above band generated from various semiconductor elements formed on the silicon substrate 1. To do.
[0025]
In addition, since the magnetic loss member 2 having the above composition is a composition that exhibits an extremely large magnetic loss due to electromagnetic wave absorption, the thickness of the magnetic loss member 2 can be remarkably reduced. Thereby, the thickness of the magnetic loss member 2 can be set to several tens of microns or less.
[0026]
Now, regarding the semiconductor element manufactured using the semiconductor substrate 101 of the present embodiment, the electromagnetic wave absorption characteristics of the magnetic loss member 2 were examined. As a result, compared with the case of a semiconductor element using a conventional semiconductor substrate (for example, the semiconductor substrate 11C shown in FIGS. An electromagnetic wave absorption effect of about 10 dB was obtained at a frequency of 3 GHz.
[0027]
Further, as a method of forming the magnetic loss member 2 on the silicon substrate 1, first, for example, by using a sputtering method or a vapor deposition method, the entire surface of the silicon substrate 1 opposite to the surface on which the above-described semiconductor element is formed is used. A layer of the magnetic loss member 2 is formed, and then the magnetic loss member 2 having a predetermined pattern shape such as a stripe shape, a lattice shape, or an island shape is formed by lithography. In order to form the layer of the magnetic loss member 2 on the silicon substrate 1, a film forming method other than the sputtering method and the vapor deposition method, for example, a chemical vapor deposition method (CVD method) may be used. Note that the material of the insulating film 3 is either silicon oxide, silicon nitride, or silicon nitride oxide. In addition, each of the magnetic loss members 2 includes at least each semiconductor element region that is individually divided from the semiconductor substrate 101 [the length of one side thereof is represented by L in FIG.₁It is formed in a region having a smaller area.
[0028]
Here, a method for manufacturing the semiconductor substrate 101 of the present embodiment will be described. In order to manufacture the semiconductor substrate 101 of the present embodiment, first, as shown in FIG. 2A, the above-described sputtering method or Using a vapor deposition method or the like, the magnetic loss member layer 2 'is formed on the entire surface.
[0029]
Next, the magnetic loss member 2 having a predetermined pattern shape is formed from the layer 2 'of the magnetic loss member using the above-described lithography method. That is, as shown in FIG. 2 (b), a resist pattern 7 is formed on the layer 2 'of the magnetic loss member, and subsequently, as shown in FIG. 2 (c), the magnetic loss member in FIG. The magnetic loss member 2 is formed in a predetermined pattern shape such as a stripe shape, a lattice shape, or an island shape as described above, leaving only the portion of the layer 2 ′ to which the resist pattern 7 is added.
[0030]
Thereafter, as shown in FIG. 2D, the surface of the silicon substrate 1 on which the pattern of the magnetic loss member 2 is formed in FIG. 2C is made of the above-described silicon oxide, silicon nitride, or silicon nitride oxide. The insulating film 3 is covered. Thereby, the semiconductor substrate 101 of this embodiment shown in FIG. 2D is completed.
[0031]
A circuit pattern of each semiconductor element is formed for each region on the surface opposite to the surface on which the magnetic loss member 2 of the semiconductor substrate 101 is formed, and each semiconductor device is manufactured by cutting out the individual region. . As described above, when the magnetic loss member 2 is formed in a stripe shape, a lattice shape, an island shape or the like, each of the semiconductor elements includes at least one unit region in which the magnetic loss member 2 is formed.
[0032]
According to the present embodiment, noise countermeasures are performed at the stage of the substrate itself, so that it is possible to provide a technique excellent in mass-producing semiconductor elements with noise countermeasures. That is, if each semiconductor element is manufactured using this semiconductor substrate 101, even if noise is generated from the semiconductor element, this noise does not leak to the outside as it is, but is not applied to the magnetic loss member 2 formed on the back surface of the semiconductor element. Absorbed. As a result, other devices and apparatuses do not malfunction. In addition, the noise absorbing process requires a lot of time for the noise reduction process as compared with the conventional example in which the noise absorbing member is applied to the back surface of each of the semiconductor elements in the subsequent process to reduce the noise. do not do. Furthermore, since the magnetic loss member 2 is formed on the back surface of each semiconductor element formation region on the semiconductor substrate 101 in the same process, the thickness of the magnetic loss member 2 (noise absorbing member) is less likely to vary. Therefore, it is possible to prevent variation in noise absorption characteristics of individual semiconductor elements.
[0033]
FIG. 3 is a view for explaining a semiconductor substrate according to the second embodiment of the present invention. FIG. 3A is a plan view of the semiconductor substrate of this embodiment, and FIG. 3B is a cross-sectional view taken along line BB in FIG. FIG. 4 is a view for explaining the method for manufacturing the semiconductor substrate according to the present embodiment.
[0034]
In a semiconductor substrate 102 shown in FIGS. 3A and 3B, a first silicon substrate 11a and a second silicon substrate 11b are bonded to each other by bonding of silicon substrates or electrostatic bonding. Here, the trench portions 4 are formed in a predetermined pattern in the first silicon substrate 11 a, and the magnetic loss member 21 is embedded in each trench portion 4.
[0035]
Here, as shown in FIG. 3B, the formation surface of the semiconductor element in the semiconductor substrate 102 is the first surface (for forming the semiconductor element) corresponding to the first silicon substrate 11a and the second silicon substrate. Either of the second surfaces (for forming a semiconductor element) corresponding to 11b may be used. Each silicon substrate 11a or 11b is set to a predetermined impurity concentration in advance corresponding to the finally produced semiconductor element.
[0036]
The material of the magnetic loss member 21 is M (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, or a mixture thereof) -Y ( Y is made of F, N, O, or a mixture thereof. For example, the composition of the magnetic loss member 21 is Fe₇₂, Al₁₁, O₁₇Is set to The magnetic loss member having such a composition has particularly excellent absorption characteristics from an electromagnetic wave in the MHz band to an electromagnetic wave in the GHz band, and various semiconductors formed on the first silicon substrate 11a or the second silicon substrate 11b. Efficiently absorbs electromagnetic waves in the above band generated from the element. Further, since the magnetic loss member 21 having the above composition has a composition that exhibits an extremely large magnetic loss due to electromagnetic wave absorption, the thickness of the magnetic loss member 21 can be remarkably reduced to a few tens of microns or less. it can. Accordingly, the depth of the trench portion 4 is set to about several tens of microns. Each of the trench portions 4 includes at least each semiconductor element region that is individually divided from the semiconductor substrate 102 [the length of one side is L in FIG.₂It is formed in a region having a smaller area. Further, the thickness t of the first silicon substrate 11a shown in FIG.₁And the thickness t of the second silicon substrate 11b₂May be set as appropriate so as to satisfy the following two conditions. That is, one is t₁+ T₂A semiconductor substrate having a desired thickness can be obtained, and the second corresponds to the noise resistance and noise generation amount of the semiconductor elements formed on the first silicon substrate 11a and the second silicon substrate 11b, respectively. T so that the magnetic loss member 21 is arranged at the optimal position.₁, T₂And the depth of the trench portion 4 is set.
[0037]
Here, a method for manufacturing the semiconductor substrate 102 of the present embodiment will be described.
[0038]
In order to manufacture the semiconductor substrate 102 of the present embodiment, first, as shown in FIG. 4A, after the pattern of the silicon oxide 31 is formed on the first silicon substrate 11a, the first silicon substrate 11a is formed. Perform dry etching. As a result, the exposed portion of silicon other than the pattern portion of the silicon oxide 31 in the first silicon substrate 11a is etched, and a pattern of the trench portion 41 having a predetermined depth L1 is formed as shown in FIG. 4B. The Subsequently, as shown in FIG. 4C, the silicon oxide 31 is removed to expose the silicon substrate surface having the trench portions 41. Next, as shown in FIG. 4D, a magnetic loss member layer 21 'is formed on the entire surface of one side including the trench portion 41 of the first silicon substrate 11a exposed in FIG. 4C. . As a method of forming the magnetic loss member layer 21 ', a film forming method such as sputtering, vapor deposition, or chemical vapor deposition (CVD) is used as in the first embodiment. Use.
[0039]
Subsequently, as shown in FIG. 4E, one side surface of the first silicon substrate 11a on which the layer 21 ′ of the magnetic loss member is formed in FIG. The portion embedded in the trench portion 41 of the loss member layer 21 ′ is exposed. As a result, as shown in FIG. 4E, the magnetic loss member 21 is formed corresponding to the pattern of the trench portion 41 on the first silicon substrate 11a.
[0040]
Further, as shown in FIG. 4 (f), the second silicon substrate 11b described above is prepared, and the first silicon substrate 11a is polished in FIG. 4 (e) as shown in FIG. 4 (g). Affix to the surface side. In FIG. 4F, the entire surface of the second silicon substrate 11b facing the first silicon substrate 11a is previously thermally oxidized. Then, the thermally oxidized facing surface of the second silicon substrate 11b is bonded to the first silicon substrate 11a by electrostatic bonding. Thereby, the semiconductor substrate 102 in which the first silicon substrate 11a and the second silicon substrate 11b are bonded together as shown in FIG. 4G is manufactured. In FIG. 4G, reference numeral 100 denotes a bonding boundary surface. The semiconductor substrate 102 of FIG. 4G is a completed state of the semiconductor substrate of this embodiment.
[0041]
Since the pattern of the trench portion 41 is determined according to the pattern for forming the silicon oxide 31 shown in FIG. 4A, the pattern of the magnetic loss member 21 embedded in the trench portion 41 is striped. The silicon oxide 31 pattern may be formed so as to have a predetermined pattern such as a lattice shape or an island shape. In the present embodiment, the second silicon substrate 11b is bonded to the surface of the first silicon substrate 11a on which the magnetic loss member 21 is embedded, so that unlike the first embodiment described above, the magnetic loss It is not necessary to cover the formation surface of the member 21 with an insulating film such as silicon oxide.
[0042]
As described above, in the semiconductor substrate 102 of the present embodiment, the first surface corresponding to the first silicon substrate 11a (for semiconductor element formation) and the second surface corresponding to the second silicon substrate 11b (semiconductor element). A semiconductor element can be formed on either of the second surfaces (of formation). Then, a circuit pattern of each semiconductor element is formed for each of the individual regions of the first or second surface, and each semiconductor device is manufactured by cutting out the individual region. As described above, when the magnetic loss member 21 is formed in a stripe shape, a lattice shape, an island shape, or the like, each of the semiconductor elements includes at least one unit region in which the magnetic loss member 21 is formed.
[0043]
Also according to the present embodiment, noise countermeasures are performed at the stage of the substrate itself, so that it is possible to provide a technology excellent in mass-producing semiconductor elements with noise countermeasures. That is, if each semiconductor element is manufactured using this semiconductor substrate 102, even if noise is generated from the semiconductor element, this noise does not leak to the outside as it is, and the magnetic loss embedded in the semiconductor element is formed. Absorbed by member 21. As a result, other devices and apparatuses do not malfunction. In addition, the noise absorbing process requires a lot of time for the noise reduction process as compared with the conventional example in which the noise absorbing member is applied to the back surface of each of the semiconductor elements in the subsequent process to reduce the noise. do not do. Furthermore, since the magnetic loss member 21 can be formed in the same process in the portion corresponding to each semiconductor element formation region of the semiconductor substrate 102, the thickness of the magnetic loss member 21 (noise absorbing member) also varies. Therefore, it is possible to prevent variation in noise absorption characteristics of individual semiconductor elements.
[0044]
FIG. 5 is a view for explaining a semiconductor device according to the third embodiment of the present invention manufactured using the semiconductor substrate 102 according to the second embodiment of the present invention.
[0045]
FIG. 5A is an external perspective view of the semiconductor element of this embodiment, and FIG. 5B is a cross-sectional view taken along line CC in FIG.
[0046]
As shown in FIGS. 5A and 5B, a semiconductor element 200 according to the third embodiment of the present invention includes a first silicon substrate 11a ′ and a second silicon substrate in which a magnetic loss member 21a is embedded. The circuit pattern region 201a is formed in the vicinity of the surface of the second silicon substrate 11b ′.
[0047]
In the semiconductor element 200 of the present embodiment, noise electromagnetic waves generated from the vicinity of the circuit pattern region 201a are efficiently absorbed by the magnetic loss member 21a due to its structure. Therefore, when the electromagnetic wave absorption characteristics of the semiconductor element 200 of the present embodiment were examined, the electromagnetic wave of about 10 decibels at a frequency of about 3 GHz was compared with the conventional semiconductor element without noise countermeasures shown in FIG. The absorption effect of was obtained. Further, the electromagnetic wave absorption characteristics of the semiconductor element 200 of the present embodiment are about 7 dB at a frequency of about 3 GHz, even when compared with the conventional semiconductor element with noise countermeasures shown in FIG. The effect was obtained.
[0048]
Although the present invention has been described with reference to various embodiments, the present invention is not limited to the above embodiments, and may be applied to other embodiments within the scope of the invention described in the claims. Of course.
[0049]
For example, in the above-described embodiment, the material of the semiconductor substrate is silicon, but the same effect can be obtained when other than silicon. Examples of materials other than silicon include gallium arsenide-based members and silicon-germanium-based members.
[0050]
【The invention's effect】
As described above, according to the present invention, interference electromagnetic waves from the MHz band to the GHz band can be efficiently absorbed, and when divided into individual devices, the effect of noise absorption can be shown. It is possible to provide a semiconductor substrate having excellent properties, a method for manufacturing the same, and a semiconductor element using the semiconductor substrate.
[Brief description of the drawings]
1A and 1B are diagrams for explaining a semiconductor substrate according to a first embodiment of the present invention. FIG. 1A is a plan view of the semiconductor substrate of the present embodiment, and FIG. Sectional drawing in the AA line of 1 (a) is shown.
FIG. 2 is a view for explaining the method of manufacturing the semiconductor substrate according to the first embodiment of the present invention. FIG. FIG. 2B shows a state in which the resist pattern 7 is formed on the layer 2 ′ of the magnetic loss member, and FIG. 2C shows the layer of the magnetic loss member in FIG. 2B. FIG. 2D shows a state in which the magnetic loss member 2 having a predetermined pattern is formed while leaving only the portion to which the 2 ′ resist pattern 7 is added. FIG. 2D shows the magnetic loss member 2 in FIG. A state in which the formed surface is covered with an insulating film 3 is shown.
3A and 3B are diagrams for explaining a semiconductor substrate according to a second embodiment of the present invention, in which FIG. 3A is a plan view of the semiconductor substrate of the present embodiment, and FIG. Sectional drawing in the BB line of 3 (a) is shown.
FIG. 4 is a diagram for explaining a method of manufacturing a semiconductor substrate according to a second embodiment of the present invention, in which FIG. 4 (a) forms a pattern of silicon oxide 31 on a first silicon substrate; FIG. 4B shows a state in which a trench portion 41 having a predetermined depth L1 is formed, and FIG. 4C shows a state in which the silicon oxide 31 is removed. 4D shows a state in which the silicon substrate surface having the trench portion 41 is exposed, and FIG. 4D shows a state in which a layer 21 ′ of a magnetic loss member is formed on the entire surface of one side of the substrate in FIG. FIG. 4E shows a state in which one side is polished to expose the silicon substrate surface and the magnetic loss member 21 in the trench portion 4, and FIG. 4F shows the second silicon. Shows the state just before the substrate is prepared and bonded to the first silicon substrate Figure 4 (g) shows a state in which bonding the first silicon substrate and the second silicon substrate.
FIGS. 5A and 5B are diagrams for explaining a semiconductor device according to a third embodiment of the present invention. FIG. 5A is an external perspective view of the semiconductor device of the present embodiment, and FIG. FIG. 6 is a cross-sectional view taken along the line CC in FIG.
6A and 6B are schematic views of a conventional semiconductor substrate, in which FIG. 6A is a plan view and FIG. 6B is a cross-sectional view taken along the line DD in FIG.
7A and 7B show a final form of a semiconductor substrate after various semiconductor manufacturing processes are performed on a conventional semiconductor substrate, FIG. 7A is a plan view, and FIG. 7B is a plan view of FIG. It is sectional drawing in the EE line.
8A and 8B are explanatory diagrams of one semiconductor element completed after cutting a conventional semiconductor substrate, in which FIG. 8A is an overview perspective view, and FIG. 8B is an FF in FIG. 8A; It is sectional drawing in a line.
9A and 9B are explanatory diagrams of an example of noise countermeasures in a conventional semiconductor device, in which FIG. 9A is an overview perspective view after noise countermeasures, and FIG. 9B is a GG line in FIG. It is sectional drawing.
[Explanation of symbols]
1 Silicon substrate
11a First silicon substrate
11b Second silicon substrate
101, 102 Semiconductor substrate
2, 21, 21a, 21 'Magnetic loss member
3 Insulating film
31 Silicon oxide
4, 41 Trench
7 resist pattern
100 Silicon substrate bonding interface
200, 200 'semiconductor element
201 Circuit pattern area

Claims

A semiconductor substrate in which a magnetic loss member is formed in part, wherein the magnetic loss member is M (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is M and Y) Element other than or a mixture thereof) -Y (Y is one of F, N, O, or a mixture thereof), and is formed on the surface of the semiconductor substrate opposite to the surface on which the semiconductor element is formed. are formed in the pattern, a semiconductor substrate, characterized in that the semiconductor substrate region in said magnetic loss member and the surface is uniformly covered with an insulating film.

2. The semiconductor substrate according to claim 1, wherein the magnetic loss member is formed on substantially the entire surface of the semiconductor substrate.

2. The semiconductor substrate according to claim 1, wherein the predetermined pattern on which the magnetic loss member is formed is a stripe shape.

2. The semiconductor substrate according to claim 1, wherein the predetermined pattern on which the magnetic loss member is formed has a lattice shape.

2. The semiconductor substrate according to claim 1, wherein the predetermined pattern on which the magnetic loss member is formed is an island shape.

6. The semiconductor substrate according to claim 1, wherein the insulating film is made of at least one material selected from the group consisting of silicon oxide, silicon nitride, or silicon nitride oxide.

7. The semiconductor substrate according to claim 1, wherein a plurality of the magnetic loss members are formed in the predetermined pattern, and each of the plurality of magnetic loss members is individually divided from at least the semiconductor substrate. A semiconductor substrate characterized in that it is formed in a region having a smaller area than a region of a semiconductor element.

A semiconductor substrate in which a first semiconductor substrate member and a second semiconductor substrate member are bonded to each other on a surface opposite to that on which a semiconductor element is formed, and a magnetic loss member is partially formed In the first semiconductor substrate member or the second semiconductor substrate member, at least one semiconductor substrate member has a trench portion formed on the surface to be bonded, and the trench M (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, or a mixture thereof) -Y (Y is F, N, O) Or a mixture thereof) is embedded in the magnetic loss member.

9. The semiconductor substrate according to claim 8, wherein a plurality of the trench portions are formed in a predetermined pattern, and each of the plurality of trench portions includes at least a region of each semiconductor element that is individually divided from the semiconductor substrate. A semiconductor substrate which is formed in a narrow area.

The semiconductor substrate according to claim 1 to 9, wherein the semiconductor substrate and the material of the first semiconductor substrate member and said second semiconductor substrate member, a semiconductor substrate, characterized in that each made of silicon.

The semiconductor substrate according to claim 1 to 9, wherein the semiconductor substrate and the material of the first semiconductor substrate member and said second semiconductor substrate member, a semiconductor substrate, characterized in that each of gallium arsenide.

A plurality of semiconductor elements repeatedly formed in a predetermined pattern on the semiconductor substrate according to any one of claims 1 to 11 , wherein each of the plurality of semiconductor elements is a unit in which the magnetic loss member is formed. A semiconductor element including at least one of regions.

A method of manufacturing a semiconductor substrate in which a magnetic loss member is partially formed, wherein M (M is any one of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, Or a mixture thereof) -Y (Y is one of F, N, O, or a mixture thereof) on the surface of the semiconductor substrate opposite to the surface on which the semiconductor element is formed. A first step of forming a predetermined pattern and a predetermined film thickness, and a second step of uniformly covering the magnetic loss member and the semiconductor substrate region on the surface with an insulating film after the first step. A method for manufacturing a semiconductor substrate, comprising: a step.

After forming a trench structure in at least the first semiconductor substrate member and forming a magnetic loss member in the trench structure, a second semiconductor substrate member is formed on the surface of the first semiconductor substrate member on which the trench structure is formed. A semiconductor substrate manufacturing method for manufacturing a semiconductor substrate by bonding,
Forming an insulating film pattern on the first semiconductor substrate member; and after forming the insulating film pattern, the first semiconductor substrate member is etched to form the trench structure having a predetermined depth. A step of removing the insulating film pattern from the first semiconductor substrate member after forming the trench structure; and removing M from the first semiconductor substrate member uniformly after removing the insulating film pattern. (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, or a mixture thereof) -Y (Y is any of F, N, O) Or a mixture thereof), and after forming the magnetic loss member, the first semiconductor substrate member is exposed so that the substrate surface in a region other than the trench structure is exposed. Research on the entire surface A semiconductor substrate manufacturing method comprising: a step of performing a treatment; and a step of bringing the second semiconductor substrate member into close contact with the first semiconductor substrate member subjected to the polishing treatment and performing a bonding treatment. Method.

After forming a trench structure in at least the first semiconductor substrate member and forming a magnetic loss member in the trench structure, a second semiconductor substrate member is formed on the surface of the first semiconductor substrate member on which the trench structure is formed. A semiconductor substrate manufacturing method for manufacturing a semiconductor substrate by bonding,
Forming an insulating film pattern on the first semiconductor substrate member; and after forming the insulating film pattern, the first semiconductor substrate member is etched to form the trench structure having a predetermined depth. A step of removing the insulating film pattern from the first semiconductor substrate member after forming the trench structure; and removing M from the first semiconductor substrate member uniformly after removing the insulating film pattern. (M is any of Fe, Co, Ni, or a mixture thereof) -X (X is an element other than M and Y, or a mixture thereof) -Y (Y is any of F, N, O) Or a mixture thereof), and after forming the magnetic loss member, the first semiconductor substrate member is exposed so that the substrate surface in a region other than the trench structure is exposed. Research on the entire surface A step of performing a treatment, a step of thermally oxidizing the entire surface of the second semiconductor substrate member not forming the trench structure facing the first semiconductor substrate member, and the step of thermally oxidizing the facing surface And a step of applying a process of bonding a second semiconductor substrate member to the first semiconductor substrate member by electrostatic bonding.

16. The method of manufacturing a semiconductor substrate according to claim 13 , wherein materials of the semiconductor substrate, the first semiconductor substrate member, and the second semiconductor substrate member are each made of silicon. Production method.

16. The method of manufacturing a semiconductor substrate according to claim 13 , wherein materials of the semiconductor substrate, the first semiconductor substrate member, and the second semiconductor substrate member are each made of gallium arsenide. Manufacturing method.