JP4577135B2 - Wireless transmission circuit and wireless transmission device - Google Patents

Description

  The present invention relates to a radio transmission circuit used for ultra-wideband communication and a radio transmission apparatus using the same.

  In recent years, an ultra wide band (UWB) communication system has attracted attention as one of high-speed wireless transmission systems. Ultra-wideband communication means ultra-wideband wireless, refers to a wireless transmission method that occupies a bandwidth of 25% or more of the center frequency or 1.5 GHz or more, and does not use a carrier wave, for example, a pulse width of 1 nsec or less, etc. The communication is performed using a pulse signal sequence composed of extremely fine short pulse signals (see, for example, Patent Document 1). A radio transmission circuit using a step recovery diode is known as a high-speed pulse generation circuit that generates such a short pulse.

  FIG. 10 is a block diagram illustrating a configuration of a wireless transmission circuit of an ultra-wideband communication system according to the background art. The radio transmission circuit 100 shown in FIG. 10 modulates transmission data and outputs it to the driver circuit 102, and increases the drive current in the modulation signal output from the modulation circuit 101 and outputs it to the step recovery diode circuit 103. A driver circuit 102 for generating a signal, a step recovery diode circuit 103 for generating a high frequency signal component in the modulation signal output from the driver circuit 102, and a short pulse by extracting a high frequency signal component generated by the step recovery diode circuit 103. A band-pass filter (BPF) 104 that generates a signal and transmits it as a radio signal from the antenna 105 is provided.

  FIG. 11 is a signal waveform diagram for explaining the operation of radio transmission circuit 100 shown in FIG. The radio transmission circuit 100 shown in FIG. 10 modulates transmission data DATA1 by OOK (On Off Keying). As shown in FIG. 11, the modulation circuit 101 has a logical value of “1” for the transmission data DATA1. ", The pulse signal is output to the driver circuit 102 as the modulation signal DATA2, the drive current in the pulse signal is increased by the driver circuit 102 and output to the step recovery diode circuit 103, and the driver circuit 102 is output by the step recovery diode circuit 103. A high-frequency signal component is generated according to the modulation signal output from the signal, and further, the high-frequency signal component is extracted by a band pass filter (BPF). Antenna 10 generated as DATA3 5 is emitted as a radio signal.

On the other hand, if the logical value of the transmission data DATA1 is “0”, the modulation circuit 101 fixes the modulation signal DATA2 to a low level. As a result, the radio signal pulse signal DATA3 also does not include the pulse P. As described above, in the wireless transmission circuit 100 illustrated in FIG. 10, the transmission data DATA1 is modulated by OOK, and the transmission data DATA1 is represented by the presence or absence of the pulse P.
Special table 2003-515974 gazette

  By the way, when performing the modulation by OOK as described above, when the transmission data DATA1 is “0”, the radio signal radiated from the antenna 105 does not include the pulse P. Therefore, the radio transmission circuit 100 on the receiver side. Therefore, it is difficult to maintain synchronization with the radio signal transmitted from the mobile phone, and the reliability of communication is reduced.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a wireless transmission circuit capable of improving the reliability of ultra-wideband communication and a wireless transmission device using the same. To do.

  In order to achieve the above-described object, a wireless transmission circuit according to the first means of the present invention is a wireless transmission circuit that transmits transmission data by a wireless signal using a pulse. First and second step recovery diodes for generating first and second modulated signals that generate signal components, respectively, and the first and second step recovery according to the logical value of each bit in the transmission data A modulation unit that causes the first and second step recovery diodes to generate the first and second modulation signals by outputting the pulse signal to any one of the diodes; and the first and second A differential output unit that generates a differential signal by taking a difference between the first and second modulation signals generated by the step recovery diode; and the differential output unit Extracting a signal component of the high frequency from more generated difference signals, it is characterized by comprising a filter unit for outputting a signal component of the frequency as a pulse for the radio signal representative of the transmission data.

  Further, in the above-described wireless transmission circuit, the modulation unit may select one of the first and second step recovery diodes for each preset number of bits in the transmission data according to a bit pattern of the number of bits. The pulse signal is outputted to the radio signal and the peak value of the pulse for the radio signal is changed.

  In the wireless transmission circuit described above, the modulation unit may change the peak value of the pulse for the wireless signal by changing a bias voltage supplied to the step recovery diode.

  Further, in the above-described wireless transmission circuit, a pulse interposed between the modulation unit and the first and second step recovery diodes and output from the modulation unit to the first and second step recovery diodes First and second driver units for respectively increasing drive currents in the signal are further included, and the modulation unit is a step recovery diode that outputs the pulse signal among at least the first and second step recovery diodes. It is characterized in that the peak value of the pulse for the radio signal is changed by changing the power supply voltage for operation of the connected driver unit.

  The wireless transmission device according to the second means of the present invention is a wireless transmission device that transmits transmission data by a wireless signal using a pulse, and is generated by a data generation unit that generates the transmission data and the data generation unit. A radio transmission circuit that outputs a pulse for a radio signal representing the transmission data based on the transmitted data, and an antenna that radiates a pulse output by the radio transmission circuit, the radio transmission circuit including The wireless transmission circuit according to any one of the above.

  In the wireless transmission circuit and the wireless transmission device having such a configuration, the modulation unit outputs a pulse signal to one of the first and second step recovery diodes according to the logical value of each bit in the transmission data, One of the first and second step recovery diodes generates either one of the first and second modulation signals in which a high-frequency signal component is generated based on the pulse signal. . Then, the differential output unit generates a difference between the first and second modulation signals as a difference signal. Then, the difference signal is generated when the first modulation signal is generated by outputting the pulse signal to the first step recovery diode by the modulation unit, and when the first modulation signal is generated by the modulation unit to the second step recovery diode. The polarity is reversed when the second modulation signal is generated. Further, the filter unit extracts a high-frequency signal component from the differential signal, and the high-frequency signal component is output as a pulse for a radio signal representing transmission data. Then, the phase of the radio signal pulse is inverted according to the polarity of the difference signal. Therefore, the phase of the pulse for the radio signal is inverted according to the logical value of each bit in the transmission data, and the logical value of the transmission data is represented by phase modulation by the phase of the pulse for the radio signal. Regardless of the logical value of the transmission data, a pulse for a radio signal is transmitted, and it becomes easy to maintain synchronization with the radio signal on the receiver side. As a result, communication reliability can be improved.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted.

(First embodiment)
FIG. 1 is a block diagram illustrating an example of a configuration of a wireless transmission device and a wireless transmission circuit according to the first embodiment of the present invention. A wireless transmission device 1 illustrated in FIG. 1 includes a crystal oscillator OSC1, an oscillation circuit 2, a data generation unit 3, a wireless transmission circuit 4, and an antenna 5. The wireless transmission circuit 4 modulates the transmission data SD1 output from the data generation unit 3, and transmits a wireless communication signal using a pulse, for example, a wireless signal using a pulse in an ultra-wideband communication method. Thus, the modulation circuit 6 (modulation unit), pre-driver circuits 71 and 72, driver units 81 and 82, step recovery diode circuits 91 and 92, differential output unit 10, and band-pass filter (BPF in each figure) 11 (filter part).

  The oscillation circuit 2 oscillates the crystal oscillator OSC1 to generate a periodic signal that is the basis of the operation of the wireless transmission device 1, for example, a clock signal CLK1 having a short pulse output period in the transmission signal, and a data generation unit 3 and a modulation circuit. Output to 6.

  The data generation unit 3 is a circuit unit that generates data to be transmitted. For example, the data generation unit 3 controls a detection device such as a human sensor or a temperature sensor that detects the presence or absence of a person, and a lighting device, an air conditioner, or the like. The remote control device or the like generates data representing information, instruction commands, etc., adds the communication address of the receiving device as the transmission destination to the generated data, and outputs the clock signal CLK1 output from the oscillation circuit 2 as transmission data SD1. And output to the modulation circuit 6. Note that the data generation unit 3 is not limited to the one that generates data to be transmitted by itself. For example, the data generation unit 3 receives data to be transmitted from a device connected to the outside and outputs the data to the modulation circuit 6 as transmission data SD1. It may be a thing.

  The modulation circuit 6 is a circuit that performs modulation by the ultra-wide band system, and outputs, for example, a pulse signal obtained by ANDing the clock signal CLK1 and the transmission data SD1 to the pre-driver circuit 71 as a signal S11, A pulse signal obtained by ANDing the signal CLK1 and the signal obtained by inverting the transmission data SD1 is output to the pre-driver circuit 72 as a signal S12.

  FIG. 2 is a circuit diagram showing an example of the configuration of the pre-driver circuits 71 and 72 and the driver units 81 and 82. Since the pre-driver circuit 71 and the pre-driver circuit 72 and the driver unit 81 and the driver unit 82 have the same configuration, FIG. 2 shows a common circuit diagram.

  The pre-driver circuits 71 and 72 are amplification circuits that primarily amplify the signals S11 and S12 output from the modulation circuit 6 to control the gate voltages of the driver units 81 and 82. For example, the source of the PMOS transistor QP1 is connected to the power supply. The drain of the PMOS transistor QP1 is connected to the drain of the NMOS transistor QN1, and the source of the NMOS transistor QN1 is connected to the ground. Signals S11 and S12 are output from the modulation circuit 6 to the gate of the PMOS transistor QP1 and the gate of the NMOS transistor QN1, and the drain voltage of the PMOS transistor QP1 is output to the driver units 81 and 82 as the output voltage of the pre-driver circuits 71 and 72. Is output.

  The driver units 81 and 82 are amplification circuits that increase the drive currents of the pulse signals S21 and S22 output to the step recovery diode circuits 91 and 92. For example, the operation power supply voltage VDD is supplied to the source of the PMOS transistor QP2, and the PMOS The drain of the transistor QP2 is connected to the drain of the NMOS transistor QN2, and the source of the NMOS transistor QN2 is connected to the ground. The output voltages of the pre-driver circuits 71 and 72 are applied to the gate of the PMOS transistor QP2 and the gate of the NMOS transistor QN2, and the drain voltage of the PMOS transistor QP2 is output to the step recovery diode circuits 91 and 92 as signals S21 and S22. The

  The step recovery diode circuits 91 and 92 generate modulation signals S31 and S32 that generate high-frequency signal components based on the signals S21 and S22 output from the driver units 81 and 82, respectively. Output to. FIG. 3 is a circuit diagram showing an example of the configuration of the step recovery diode circuits 91 and 92. Since the step recovery diode circuit 91 and the step recovery diode circuit 92 have the same configuration, FIG. 3 shows a common circuit diagram.

  In the step recovery diode circuits 91 and 92 shown in FIG. 3, the signals S21 and S22 output from the driver units 81 and 82 are input to the high pass filter 93, and the output of the high pass filter 93 is connected to the anode of the step recovery diode SRD. The cathode of the step recovery diode SRD is connected to the ground. A predetermined bias voltage Vbias is supplied to the anode of the step recovery diode SRD via the voltage-current conversion element 94.

  The high-pass filter 93 is a high-pass filter configured using, for example, a capacitor, and allows high-frequency components of the signals S21 and S22 output from the driver units 81 and 82 to pass therethrough. The voltage-current conversion element 94 is an element that converts the bias voltage Vbias into a current, and for example, a resistor or an inductor is used. The voltage generated at the anode of the step recovery diode SRD by the signal passing through the high-pass filter 93 is output to the differential output unit 10 as modulation signals S31 and S32.

  The differential output unit 10 takes the difference between the modulation signals S31 and S32 generated by the step recovery diode circuits 91 and 92, generates a difference signal S4, and outputs the difference signal S4 to the bandpass filter 11. FIG. 4 is a circuit diagram illustrating an example of the configuration of the differential output unit 10. The differential output unit 10 shown in FIG. 4 is configured using a transformer, and a modulation signal S31 is input to one end of the primary winding, and a modulation signal S32 is input to the other end. One end of the secondary winding is connected to the band pass filter 11 and the other end is connected to the ground.

  The bandpass filter 11 is a bandpass filter that extracts a high-frequency signal component from the differential signal S4 output from the differential output unit 10, and the extracted high-frequency signal component is used as a pulse signal Sout for ultra-wideband communication with the antenna 5. Output to. The antenna 5 radiates the pulse signal Sout as a radio signal.

  Next, the operation of the wireless transmission device 1 configured as described above will be described. FIG. 5 is a signal waveform diagram for explaining the operation of the wireless transmission device 1. First, the oscillation circuit 2 generates the clock signal CLK1 based on the oscillation frequency of the crystal oscillator OSC1, and outputs it to the data generation unit 3 and the modulation circuit 6. Next, the transmission data SD1 is output from the data generation unit 3 to the modulation circuit 6 in synchronization with the clock signal CLK1. Then, for example, the pulse signal obtained by taking the logical product of the clock signal CLK1 and the transmission data SD1 by the modulation circuit 6 is output to the pre-driver circuit 71 as the signal S11, and the clock signal CLK1 and the transmission data SD1 are inverted. A pulse signal obtained by logical product with the signal is output to the pre-driver circuit 72 as a signal S12.

  Then, the signals S11 and S12 are amplified by the pre-driver circuits 71 and 72, respectively, and the drive current is increased by the driver units 81 and 82, which are output to the step recovery diode circuits 91 and 92 as the signals S21 and S22. The step recovery diode SRD in the diode circuits 91 and 92 generates a high-frequency signal component at the signal falling portions of the signals S21 and S22, so that the falling edges are sharpened and undermodulated modulation signals S31 and S32 are generated. Generated.

  Then, the differential output unit 10 outputs the difference between the modulation signals S31 and S32 to the bandpass filter 11 as a difference signal S4. In this case, the differential signal S4 is a positive pulse when the modulation signal S31 has a pulse, that is, when the logical value of the transmission data SD1 is “1”, while the modulation signal S32 has a pulse, that is, transmission. When the logical value of the data SD1 is “0”, the pulse is in the reverse direction.

  Furthermore, a high-frequency signal component is extracted from the differential signal S4 output from the differential output unit 10 by the bandpass filter 11, and is output to the antenna 5 as a pulse signal Sout for ultra-wideband communication. The signal Sout is emitted as a radio signal. In this case, as shown in an enlarged view in FIG. 5, the pulse P1 representing the logical value “1” of the transmission data SD1 and the pulse P2 representing the logical value “0” of the transmission data SD1 have a signal waveform whose phase is inverted. Become.

  That is, the logical value of the transmission data SD1 can be represented by the phase of the output pulse, and modulation by PSK (Phase Shift Keying) can be performed.

  Thus, unlike the case where the transmission data DATA1 is modulated by OOK as in the wireless transmission circuit 100 according to the background art, the wireless signal modulated by PSK is not related to the logical value (1/0) of the transmission data SD1. Since the pulse signal is included at a constant period, it is easy to maintain synchronization with the radio signal transmitted from the radio transmission circuit 100 on the receiver side, and the reliability of communication can be improved.

  In addition, when transmitting data is modulated by OOK as in the case of the wireless transmission circuit 100 according to the background art, data is represented by the presence or absence of a pulse in a wireless signal. Therefore, if noise occurs in the absence of a pulse, the receiver side There is a risk of receiving incorrect data. However, like the wireless transmission device 1 shown in FIG. 1, the wireless signal modulated by PSK includes a pulse signal regardless of the logical value (1/0) of the transmission data SD1, and the wireless signal varies depending on the phase of the pulse signal. Since the logical value of the signal is discriminated, the influence of noise can be reduced, and the S / N ratio (signal to noise ratio) can be improved to improve the reliability of communication.

(Second Embodiment)
Next, a wireless transmission device and a wireless transmission circuit according to the second embodiment of the present invention will be described. FIG. 6 is a block diagram showing an example of the configuration of the wireless transmission device 1a according to the second embodiment of the present invention. 6, when the bias voltage Vbias is changed in the step recovery diode circuits 91 and 92 shown in FIG. 3, the peak values of the modulation signals S31 and S32 change, and the pulse signal Sout The multi-level modulation is performed by expressing the information of a plurality of bits by the peak value and the phase of the pulse signal Sout using the change in the amplitude of the signal. As a result, for example, a wireless transmitter configured to transmit one bit using eight short pulse signals can transmit data of a plurality of bits using the same eight short pulse signals to increase the transmission speed. To do.

  The wireless transmission circuit 4a shown in FIG. 6 differs from the wireless transmission circuit 4 shown in FIG. 1 in the following points. That is, the wireless transmission circuit 4a shown in FIG. 6 further includes bias control circuits 61 and 62 that change the bias voltage Vbias of the step recovery diode circuits 91 and 92, respectively. In addition, the modulation circuit 6a includes a register 63 that temporarily stores the transmission data SD1 output from the data generation unit 3 by a plurality of bits, for example, by 2 bits.

  The modulation circuit 6 a outputs a control signal to the bias control circuits 61 and 62 in order to change the bias voltage Vbias based on the data of a plurality of bits temporarily stored by the register 63. The bias control circuits 61 and 62 are power supply circuits that change the bias voltage Vbias supplied to the step recovery diode circuits 91 and 92 in accordance with a control signal from the modulation circuit 6a.

  Since other configurations and operations are the same as those of the wireless transmission device 1 shown in FIG. 1 except for the following operations, description thereof will be omitted, and characteristic operations of the present embodiment will be described below. In the following description, an example in which 2 bits are multi-valued will be described. FIG. 7 is a signal waveform diagram for explaining the operation of the wireless transmission circuit 4a. First, the clock signal CLK1 generated based on the oscillation frequency of the crystal oscillator OSC1 by the oscillation circuit 2 is output to the modulation circuit 6a and the data generation unit 3.

  Then, the transmission data SD1 is output from the data generator 3 to the register 63 in synchronization with the clock signal CLK1, and the register 63 holds the data every two bits. In FIG. 7, transmission data SD1 represents one bit with four clocks of the clock signal CLK1, and represents “0” at a low level and “1” at a high level.

  Then, for every two bits held by the register 63, the modulation circuit 6a outputs a pulse signal to either the pre-driver circuit 71 or the pre-driver circuit 72 in accordance with the bit pattern of the number of bits. The phase of Sout is controlled, and a control signal is output to the bias control circuits 61 and 62 to change the pulse signal Sout peak value.

  Specifically, for example, when the value of the register 63 is “00” by the modulation circuit 6a, a pulse is output as the signal S12 to the pre-driver circuit 72 and the bias voltage Vbias is supplied to the bias control circuit 62. Is output to a predetermined low voltage set in advance, and the pulse signal Sout is a pulse signal having an opposite phase and a small signal amplitude. When the value of the register 63 is “01”, a pulse is output as the signal S11 to the pre-driver circuit 71 and a control signal for lowering the bias voltage Vbias is output to the bias control circuit 61. The output pulse signal Sout is a pulse signal having a positive phase and a small signal amplitude.

  When the value of the register 63 is “10” by the modulation circuit 6a, a pulse is output as the signal S12 to the pre-driver circuit 72 and the bias voltage Vbias is preset to the bias control circuit 62. A control signal for outputting a predetermined high voltage is output, and the pulse signal Sout is a pulse signal having an opposite phase and a large signal amplitude. When the value of the register 63 is “11”, a pulse is output as the signal S11 to the pre-driver circuit 71 and a control signal for increasing the bias voltage Vbias is supplied to the bias control circuit 61. The output pulse signal Sout is a pulse signal having a positive phase and a large signal amplitude.

  As a result, the pulse signal Sout can be multi-valued and information for a plurality of bits can be transmitted with one pulse, so that the communication speed can be increased.

  Note that the modulation circuit 6a switches the bias voltage Vbias into two stages of a low voltage and a high voltage by the bias control circuits 61 and 62, and sets one bit in the pulse signal Sout for 2-bit data in combination with the phase of the pulse signal Sout. Although an example in which one pulse is multi-valued has been shown, the number of bits to be multi-valued into one pulse may be increased by setting the bias voltage Vbias to three stages or four or more stages.

  Further, the modulation circuit 6a may output a control signal to the bias control circuits 61 and 62 to make the bias voltage Vbias zero at a timing when no pulse is output. As a result, the bias current flowing through the step recovery diode SRD in the step recovery diode circuits 91 and 92 can be reduced to zero at the timing when the pulse is not output and the bias voltage Vbias is not required. Can be reduced.

(Third embodiment)
Next, a radio transmission apparatus and radio transmission circuit according to the third embodiment of the present invention will be described. FIG. 8 is a block diagram illustrating an example of a configuration of the wireless transmission device 1b according to the third embodiment of the present invention. In the wireless transmission device 1b and the wireless transmission circuit 4b shown in FIG. 8, when the operating power supply voltage VDD is changed in the driver units 81 and 82 shown in FIG. 2, the peak values of the signals S21 and S22 change, and the pulse signal Sout Using the change in amplitude, multi-level modulation is performed by expressing information of a plurality of bits as a peak value and a phase of the pulse signal Sout. As a result, for example, a wireless transmitter configured to transmit one bit using eight short pulse signals can transmit data of a plurality of bits using the same eight short pulse signals to increase the transmission speed. To do.

  The radio transmission circuit 4b shown in FIG. 8 differs from the radio transmission circuit 4a shown in FIG. 6 in the following points. That is, the wireless transmission circuit 4 b shown in FIG. 8 is different in that it includes VDD control circuits 64 and 65 instead of the bias control circuits 61 and 62. The modulation circuit 6 b outputs a control signal to the VDD control circuits 64 and 65 in order to change the operation power supply voltage VDD based on a plurality of bits of data temporarily stored by the register 63. The VDD control circuits 64 and 65 are power supply circuits that change the operation power supply voltage VDD supplied to the driver units 81 and 82 in accordance with a control signal from the modulation circuit 6b.

  Since other configurations and operations are the same as those of the wireless transmission device 1a shown in FIG. 6 except for the following operations, description thereof will be omitted, and characteristic operations of the present embodiment will be described below. In the following description, an example in which 2 bits are multi-valued will be described. FIG. 9 is a signal waveform diagram for explaining the operation of the wireless transmission circuit 4a. First, the clock signal CLK1 generated based on the oscillation frequency of the crystal oscillator OSC1 by the oscillation circuit 2 is output to the modulation circuit 6b and the data generation unit 3.

  Then, the transmission data SD1 is output from the data generator 3 to the register 63 in synchronization with the clock signal CLK1, and the register 63 holds the data every two bits. In FIG. 9, transmission data SD1 represents one bit with four clocks of the clock signal CLK1, and represents “0” at a low level and “1” at a high level.

  Then, for every 2 bits held by the register 63, the modulation circuit 6b outputs a pulse signal to either the pre-driver circuit 71 or the pre-driver circuit 72 according to the bit pattern of the number of bits. The phase of Sout is controlled, and a control signal is output to the VDD control circuits 64 and 65 to change the peak value of the pulse signal Sout.

  Specifically, for example, when the value of the register 63 is “00” by the modulation circuit 6b, a pulse is output as the signal S12 to the pre-driver circuit 72 and the operation power supply to the VDD control circuit 65. A control signal indicating that the voltage VDD is set to a predetermined low voltage is output, and the pulse signal Sout is a pulse signal having an opposite phase and a small signal amplitude. When the value of the register 63 is “01”, a pulse is output as the signal S11 to the pre-driver circuit 71, and the control to lower the operating power supply voltage VDD to the VDD control circuit 64 is performed. A signal is output, and the pulse signal Sout is a pulse signal having a positive phase and a small signal amplitude.

  When the value of the register 63 is “10” by the modulation circuit 6b, a pulse is output as the signal S12 to the pre-driver circuit 72, and the operation power supply voltage VDD is set in advance to the VDD control circuit 65. Then, the control signal indicating the predetermined high voltage is output, and the pulse signal Sout is converted into a pulse signal having an opposite phase and a large signal amplitude. Further, when the value of the register 63 is “11”, a pulse is output as the signal S11 to the pre-driver circuit 71, and at the same time, a control to increase the operating power supply voltage VDD to the VDD control circuit 64. A signal is output, and the pulse signal Sout is a pulse signal having a positive phase and a large signal amplitude.

  As a result, the pulse signal Sout can be multi-valued and information for a plurality of bits can be transmitted with one pulse, so that the communication speed can be increased.

  Note that the modulation circuit 6b switches the operation power supply voltage VDD to two levels of low voltage and high voltage by the VDD control circuits 64 and 65, and the pulse signal Sout for 2-bit data by combining with the phase of the pulse signal Sout. In the above example, one pulse is multi-valued, but the number of bits to be multi-valued in one pulse can be increased by setting the operation power supply voltage VDD to three stages or four or more stages. Good.

  Further, the bias control circuits 61 and 62 may be further provided, and the peak value of the pulse signal Sout may be changed to be multi-valued by a combination of voltage changes of the operation power supply voltage VDD and the bias voltage Vbias.

It is a block diagram which shows an example of a structure of the wireless transmission device and wireless transmission circuit which concern on the 1st Embodiment of this invention. FIG. 2 is a circuit diagram illustrating an example of a configuration of a pre-driver circuit and a driver unit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a configuration of a step recovery diode circuit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a configuration of a differential output unit illustrated in FIG. 1. FIG. 3 is a signal waveform diagram for explaining the operation of the wireless transmission device 1 shown in FIG. 1. It is a block diagram which shows an example of a structure of the radio transmission apparatus and radio transmission circuit which concern on the 2nd Embodiment of this invention. FIG. 7 is an explanatory diagram for explaining an operation of the wireless transmission circuit illustrated in FIG. 6. It is a block diagram which shows an example of a structure of the wireless transmission device and wireless transmission circuit which concern on the 3rd Embodiment of this invention. It is explanatory drawing for demonstrating operation | movement of the radio | wireless transmission circuit shown in FIG. It is a block diagram which shows the structure of the wireless transmission circuit of the ultra wide band communication system which concerns on background art. It is a signal waveform diagram for demonstrating operation | movement of the radio | wireless transmission circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1a, 1b Radio transmission apparatus 2 Oscillation circuit 3 Data generation part 4, 4a, 4b Radio transmission circuit 5 Antenna 6, 6a, 6b Modulation circuit 10 Differential output part 11 Band pass filter 61, 62 Bias control circuit 64, 65 VDD control circuit 71, 72 Pre-driver circuit 81, 82 Driver unit 91, 92 Step recovery diode circuit 93 High-pass filter 94 Voltage-current conversion element QN1, QP1, QN2, QP2 Transistor SRD Step recovery diode

Claims (5)

In a wireless transmission circuit that transmits transmission data by a wireless signal using a pulse,
First and second step recovery diodes for generating first and second modulated signals, respectively, which generate high-frequency signal components based on the input pulse signal;
By outputting the pulse signal to one of the first and second step recovery diodes according to the logical value of each bit in the transmission data, the first and second step recovery diodes are supplied with the first signal. And a modulation unit for generating the second modulation signal, and
A differential output unit that generates a difference signal by taking a difference between the first and second modulation signals generated by the first and second step recovery diodes;
A filter unit that extracts the high-frequency signal component from the differential signal generated by the differential output unit, and outputs the high-frequency signal component as a pulse for the radio signal representing the transmission data. Wireless transmission circuit. The modulation unit outputs the pulse signal to one of the first and second step recovery diodes according to a bit pattern of the number of bits for each preset number of bits in the transmission data, and The wireless transmission circuit according to claim 1, wherein a peak value of a pulse for a wireless signal is changed. The wireless transmission circuit according to claim 2, wherein the modulation unit changes a peak value of the pulse for the wireless signal by changing a bias voltage supplied to the step recovery diode. A first step is provided between the modulation unit and the first and second step recovery diodes to increase the drive currents in the pulse signals output from the modulation unit to the first and second step recovery diodes, respectively. A first driver portion and a second driver portion;
The modulation unit changes the power supply voltage for operation of the driver unit connected to the step recovery diode that outputs the pulse signal among at least the first and second step recovery diodes, thereby changing the wireless The wireless transmission circuit according to claim 2, wherein the peak value of the signal pulse is changed. In a wireless transmission device that transmits transmission data by a wireless signal using a pulse,
A data generation unit for generating the transmission data;
Based on the transmission data generated by the data generation unit, a wireless transmission circuit that outputs a pulse for a wireless signal representing the transmission data;
An antenna that radiates pulses output by the wireless transmission circuit;
The wireless transmission circuit according to claim 1, wherein the wireless transmission circuit is the wireless transmission circuit according to claim 1.

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