JP4622724B2 - Wireless transmission circuit and wireless transmission device - Google Patents

Description

  The present invention relates to a radio transmission circuit used for ultra-wideband communication and a radio transmission apparatus using the same.

  In recent years, an ultra wide band (UWB) communication system has attracted attention as one of high-speed wireless transmission systems. Ultra-wideband communication means ultra-wideband wireless, refers to a wireless transmission method that occupies a bandwidth of 25% or more of the center frequency or 1.5 GHz or more, and does not use a carrier wave, for example, a pulse width of 1 nsec or less, etc. The communication is performed using a pulse signal sequence composed of extremely fine short pulse signals (see, for example, Patent Document 1). A radio transmission circuit using a step recovery diode is known as a high-speed pulse generation circuit that generates such a short pulse.

  FIG. 19 is a block diagram showing a configuration of a radio transmission circuit of an ultra-wideband communication system according to the background art. The radio transmission circuit 100 shown in FIG. 19 modulates transmission data and outputs it to the driver circuit 102, and increases the drive current in the modulation signal output from the modulation circuit 101 and outputs it to the step recovery diode circuit 103. A driver circuit 102 for generating a signal, a step recovery diode circuit 103 for generating a high frequency signal component in the modulation signal output from the driver circuit 102, and a short pulse by extracting a high frequency signal component generated by the step recovery diode circuit 103. A band-pass filter (BPF) 104 that generates a signal and transmits it as a radio signal from the antenna 105 is provided.

In addition, the transmission power by the ultra-wide band communication method needs to be equal to or less than the spectrum mask SPM defined by the Federal Communications Commission (FCC) shown in FIG. In the spectrum mask shown in FIG. 20, the horizontal axis indicates the transmission frequency, the vertical axis indicates the transmission power, and the transmission power is defined for each frequency. For example, in the spectrum mask shown in FIG. 20, the allowable power level is high in the range of 3.1 GHz to 10.6 GHz, and the allowable power level is low when outside this frequency range. By cutting out frequency components outside the frequency range, the transmission power by the ultra-wide band communication method is made to be equal to or less than the spectrum mask SPM.
Special table 2003-515974 gazette

  By the way, in the above-described wireless transmission circuit, the bandpass filter can be eliminated because the transmission power is made less than the spectrum mask defined by the FCC by limiting the frequency range of the transmission signal using the bandpass filter. Therefore, the wireless transmission circuit is an obstacle to downsizing and cost reduction.

  The present invention has been made in view of such problems, and a wireless transmission circuit that can be reduced in size and cost by eliminating a bandpass filter, and wireless transmission using the same An object is to provide an apparatus.

In order to achieve the above-described object, a wireless transmission circuit according to the first means of the present invention is a wireless transmission circuit that transmits transmission data by a wireless signal using a pulse, and sets a logical value of each bit in the transmission data. a modulation unit for outputting a pulse signal in response, the first step recovery diode for generating a first modulated signal that caused the high frequency signal components on the basis of a pulse signal output from the modulation unit, the modulation unit A delay unit that delays the pulse signal output from the signal by a predetermined delay time, and a second step of generating a second modulation signal that generates a high-frequency signal component based on the pulse signal delayed by the delay unit generating a difference signal by taking a recovery diode, a difference between the first and second modulating signals generated by said first and second step recovery diode It is characterized in that it comprises a differential output unit that.

  In the above-described wireless transmission circuit, the delay time by the delay unit is set to ½ of the pulse width of the wireless signal.

  In the above wireless transmission circuit, the delay unit is configured using a transmission line that generates a propagation delay time corresponding to the delay time.

  In the wireless transmission circuit described above, the delay unit is configured using a series circuit of a plurality of switches and capacitors connected to the signal path.

  Further, in the above-described wireless transmission circuit, the modulation unit changes a bias voltage supplied to the step recovery diode in accordance with a bit pattern of the number of bits for each preset number of bits in the transmission data. Thus, the peak value of the radio signal pulse is changed.

  Further, in the above-described wireless transmission circuit, a pulse interposed between the modulation unit and the first and second step recovery diodes and output from the modulation unit to the first and second step recovery diodes First and second driver units for respectively increasing the drive current in the signal, the modulation unit for each of the preset number of bits in the transmission data according to the bit pattern of the number of bits And the peak value of the pulse for the radio signal is changed by changing the power supply voltage for operation of the second driver section.

  The wireless transmission device according to the second means of the present invention is a wireless transmission device that transmits transmission data by a wireless signal using a pulse, and is generated by a data generation unit that generates the transmission data and the data generation unit. A radio transmission circuit that outputs a pulse for a radio signal representing the transmission data based on the transmitted data, and an antenna that radiates a pulse output by the radio transmission circuit, the radio transmission circuit including The wireless transmission circuit according to any one of the above.

  In the wireless transmission circuit and the wireless transmission device having such a configuration, the modulation unit outputs a pulse signal to the first and second step recovery diodes according to the logical value of each bit in the transmission data, and based on the pulse signal Thus, first and second modulated signals that generate high-frequency signal components are generated. Then, the second modulated signal is delayed by a delay unit provided in a signal path from the modulation unit to the differential output unit. Furthermore, the differential output unit generates a difference between the first and second modulation signals as a difference signal. Then, since the second modulation signal is delayed by the delay unit, a high-frequency signal included in the first modulation signal is first extracted as a differential signal, and a high-frequency signal included in the second modulation signal is delayed. The difference signal is generated by extracting the signal generated from the first modulation signal with the opposite polarity. Then, the difference signal becomes a Gaussian pulse in which pulses of opposite polarities are combined, and it becomes easy to make the transmission power below the FCC spectrum mask without using a bandpass filter. By eliminating the bandpass filter as compared with the case where the transmission power is less than or equal to the FCC spectrum mask, it is possible to reduce the size and cost.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted.

(First embodiment)
FIG. 1 is a block diagram illustrating an example of a configuration of a wireless transmission device and a wireless transmission circuit according to the first embodiment of the present invention. A wireless transmission device 1 illustrated in FIG. 1 includes a crystal oscillator OSC1, an oscillation circuit 2, a data generation unit 3, a wireless transmission circuit 4, and an antenna 5. The wireless transmission circuit 4 modulates the transmission data SD1 output from the data generation unit 3, and transmits a wireless communication signal using a pulse, for example, a wireless signal using a pulse in an ultra-wideband communication method. Thus, a modulation circuit 6 (modulation unit), pre-driver circuits 71 and 72, driver units 81 and 82, step recovery diode circuits 91 and 92, a differential output unit 10, and a delay unit 11 are provided. .

  The oscillation circuit 2 oscillates the crystal oscillator OSC1 to generate a periodic signal that is the basis of the operation of the wireless transmission device 1, for example, a clock signal CLK1 having a short pulse output period in the transmission signal, and a data generation unit 3 and a modulation circuit. Output to 6.

  The data generation unit 3 is a circuit unit that generates data to be transmitted. For example, the data generation unit 3 controls a detection device such as a human sensor or a temperature sensor that detects the presence or absence of a person, and a lighting device, an air conditioner, or the like. The remote control device or the like generates data representing information, instruction commands, etc., adds the communication address of the receiving device as the transmission destination to the generated data, and outputs the clock signal CLK1 output from the oscillation circuit 2 as transmission data SD1. And output to the modulation circuit 6. Note that the data generation unit 3 is not limited to the one that generates data to be transmitted by itself. For example, the data generation unit 3 receives data to be transmitted from a device connected to the outside and outputs the data to the modulation circuit 6 as transmission data SD1. It may be a thing.

  The modulation circuit 6 is a circuit that performs modulation by the ultra-wide band system. For example, the pre-driver circuit 71, the delay unit 11 and the pulse signal obtained by ANDing the clock signal CLK1 and the transmission data SD1 are used as the signal S11. Output to.

  The delay unit 11 is a delay circuit that outputs the signal S12 obtained by delaying the signal S11 to the pre-driver circuit 72. The delay unit 11 includes, for example, a buffer circuit, a capacitor, a delay line, and the like. Depending on the charging time or the like, the signal S11 is delayed by about ½ of the pulse width of the short pulse signal, which is an ultra-wideband transmission signal, for example, about 50 psec to 150 psec.

  FIG. 2 is a circuit diagram showing an example of the configuration of the pre-driver circuits 71 and 72 and the driver units 81 and 82. Since the pre-driver circuit 71 and the pre-driver circuit 72 and the driver unit 81 and the driver unit 82 have the same configuration, FIG. 2 shows a common circuit diagram.

  The pre-driver circuits 71 and 72 are amplification circuits that primarily amplify the signals S11 and S12 output from the modulation circuit 6 to control the gate voltages of the driver units 81 and 82. For example, the source of the PMOS transistor QP1 is connected to the power supply. The drain of the PMOS transistor QP1 is connected to the drain of the NMOS transistor QN1, and the source of the NMOS transistor QN1 is connected to the ground. Signals S11 and S12 are output from the modulation circuit 6 to the gate of the PMOS transistor QP1 and the gate of the NMOS transistor QN1, and the drain voltage of the PMOS transistor QP1 is output to the driver units 81 and 82 as the output voltage of the pre-driver circuits 71 and 72. Is output.

  The driver units 81 and 82 are amplification circuits that increase the drive currents of the pulse signals S21 and S22 output to the step recovery diode circuits 91 and 92. For example, the operation power supply voltage VDD is supplied to the source of the PMOS transistor QP2, and the PMOS The drain of the transistor QP2 is connected to the drain of the NMOS transistor QN2, and the source of the NMOS transistor QN2 is connected to the ground. The output voltages of the pre-driver circuits 71 and 72 are applied to the gate of the PMOS transistor QP2 and the gate of the NMOS transistor QN2, and the drain voltage of the PMOS transistor QP2 is output to the step recovery diode circuits 91 and 92 as signals S21 and S22. The

  The step recovery diode circuits 91 and 92 generate modulation signals S31 and S32 that generate high-frequency signal components based on the signals S21 and S22 output from the driver units 81 and 82, respectively. Output to. FIG. 3 is a circuit diagram showing an example of the configuration of the step recovery diode circuits 91 and 92. Since the step recovery diode circuit 91 and the step recovery diode circuit 92 have the same configuration, FIG. 3 shows a common circuit diagram.

  In the step recovery diode circuits 91 and 92 shown in FIG. 3, the signals S21 and S22 output from the driver units 81 and 82 are input to the high pass filter 93, and the output of the high pass filter 93 is connected to the anode of the step recovery diode SRD. The cathode of the step recovery diode SRD is connected to the ground. A bias voltage Vbias for supplying a bias current to the step recovery diode SRD is supplied to the anode of the step recovery diode SRD via the voltage-current conversion element 94.

  The high-pass filter 93 is a high-pass filter configured using, for example, a capacitor, and allows high-frequency components of the signals S21 and S22 output from the driver units 81 and 82 to pass therethrough. The voltage-current conversion element 94 is an element that converts the bias voltage Vbias into a current, and for example, a resistor or an inductor is used. The voltage generated at the anode of the step recovery diode SRD by the signal passing through the high-pass filter 93 is output to the differential output unit 10 as modulation signals S31 and S32.

  The differential output unit 10 takes the difference between the modulation signals S31 and S32 generated by the step recovery diode circuits 91 and 92 and outputs the difference to the antenna 5 as a pulse signal Sout (difference signal) for ultra-wideband communication. The antenna 5 radiates the pulse signal Sout as a radio signal.

  FIG. 4 is a circuit diagram illustrating an example of the configuration of the differential output unit 10. The differential output unit 10 shown in FIG. 4 is configured using a transformer, and a modulation signal S31 is input to one end of the primary winding, and a modulation signal S32 is input to the other end. One end of the secondary winding is connected to the antenna 5 and the other end is connected to the ground.

  Next, the operation of the wireless transmission device 1 configured as described above will be described. FIG. 5 is a signal waveform diagram for explaining the operation of the wireless transmission device 1. First, the oscillation circuit 2 generates the clock signal CLK1 based on the oscillation frequency of the crystal oscillator OSC1, and outputs it to the data generation unit 3 and the modulation circuit 6. Next, the transmission data SD1 is output from the data generation unit 3 to the modulation circuit 6 in synchronization with the clock signal CLK1. Then, for example, a pulse signal obtained by taking the logical product of the clock signal CLK1 and the transmission data SD1 by the modulation circuit 6 is output to the pre-driver circuit 71 and the delay unit 11 as a signal S11. S11 is delayed by a delay time td and output to the pre-driver circuit 72 as a signal S12.

  Then, the signals S11 and S12 are amplified by the pre-driver circuits 71 and 72, respectively, and the drive current is increased by the driver units 81 and 82, which are output to the step recovery diode circuits 91 and 92 as the signals S21 and S22. The step recovery diode SRD in the diode circuits 91 and 92 generates a high-frequency signal component at the signal falling portions of the signals S21 and S22, so that the falling edges are sharpened and undermodulated modulation signals S31 and S32 are generated. Generated. In this case, the modulation signal S32 is delayed by a delay time td from the modulation signal S31.

  Then, the differential output unit 10 outputs the difference between the modulation signals S31 and S32 to the antenna 5 as a pulse signal Sout. In this case, the pulse signal Sout becomes a pulse in the reverse direction at the timing before the modulation signal S31 falls and the modulation signal S32 falls, and at the timing when the modulation signal S31 is delayed by the delay time td from the fall. When the modulation signal S32 falls after S31 rises, the pulse signal Sout becomes a pulse in the positive direction. Then, the pulse signal Sout becomes a Gaussian pulse in which a reverse pulse and a forward pulse are continuous.

  FIG. 6 is an explanatory diagram showing an example of the waveform of a Gaussian pulse, where the vertical axis indicates the current Iant flowing through the antenna 5 by the pulse signal Sout, and the horizontal axis indicates time t. In the FCC spectrum mask, since 3.1 GHz to 10.6 GHz is an ultra-wide band, the pulse width tw of the pulse signal Sout needs to be in the range of about 320 psec to 94 psec. Then, the delay time td is smaller than the pulse width tw and needs to be about ½, for example, and is about 200 psec to 30 psec.

  FIG. 7 is a graph showing transmission power distributions of impulses and Gaussian pulses. As shown in FIG. 7, in the case of an impulse signal, it exceeds the reference value of the ultra-wide band standard defined by the spectrum mask of the FCC in the low frequency region, and thus exceeds the reference value using a bandpass filter. It is necessary to cut the signal in the frequency band. However, as shown in FIG. 7, in the case of a Gaussian pulse, the transmission power can be kept within the reference value of the ultra wide band standard without using a band pass filter.

  Thereby, since the bandpass filter 104 used in the wireless transmission circuit 100 according to the background art shown in FIG. 19 can be deleted, the wireless transmission circuit 4 and the wireless transmission device 1 using the same can be reduced in size, In addition, cost reduction can be achieved.

  FIG. 8A is a signal waveform diagram showing an example of a pulse signal waveform output from the bandpass filter 104 in the wireless transmission circuit 100 according to the background art shown in FIG. FIG. 8B is a signal waveform diagram showing a signal waveform of the pulse signal Sout output from the wireless transmission circuit 4 shown in FIG. As shown in FIG. 8, the pulse width (time during which a pulse is output) t1 of the pulse signal waveform output from the wireless transmission circuit 100 according to the background art, and the pulse output from the wireless transmission circuit 4 shown in FIG. The pulse width tw of the signal Sout has a relationship of t1> tw.

  On the other hand, in an ultra-wideband receiver, the pulse width of one of the radio signals (the time during which a pulse is output) is shorter in order to detect and synchronize the timing of the pulse signal transmitted from the transmitter. However, it becomes easy to improve the detection accuracy of the synchronization timing. Further, in the receiver of the ultra-wide band system, after synchronizing with the pulse signal of the radio signal, the receiving circuit is operated only for a certain period including the timing synchronized with the timing of the pulse signal, and reception is performed during a period other than the period. It is conceivable to reduce current consumption by stopping the operation of the circuit.

  In this case, according to the wireless transmission circuit 4 shown in FIG. 1, it is easy to improve the synchronization timing detection accuracy on the receiving device side, and if the synchronization timing detection accuracy is improved, the reception circuit is operated for one pulse. Since the necessity to allow for a margin in the period is reduced and the operation period can be shortened, the power consumption on the receiver side can be easily reduced.

  Although an example in which the delay unit 11 is provided between the modulation circuit 6 and the pre-driver circuit 72 has been shown, it is provided on any path on the path from the modulation circuit 6 to the differential output unit 10 via the step recovery diode circuit 92. However, the present invention is not limited to the example provided between the modulation circuit 6 and the pre-driver circuit 72.

(Second Embodiment)
Next, a wireless transmission device and a wireless transmission circuit according to the second embodiment of the present invention will be described. FIG. 9 is a block diagram showing an example of a configuration of a wireless transmission device 1a using the wireless transmission circuit 4a according to the second embodiment of the present invention. 9 is different from the wireless transmission circuit 4 shown in FIG. 1 in that a wiring pattern (transmission line) having a length that generates a propagation delay time corresponding to the delay time td is used instead of the delay unit 11. The difference is that it includes a configured delay unit 11a.

  In the wireless transmission circuit 4a shown in FIG. 9, the signal S21a output from the driver unit 81 is delayed by the wiring pattern A and then received by the step recovery diode circuit 91 as the signal S21b. The signal S22a output from the driver unit 82 is delayed by the wiring pattern B that is longer than the wiring pattern A by the delay unit 11a, and then received by the step recovery diode circuit 92 as the signal S22b.

  Since other configurations and operations are the same as those of the wireless transmission device 1 shown in FIG. 1, the description thereof will be omitted, and the characteristic configuration of the present embodiment will be described below. FIG. 10 is an explanatory diagram showing an example of the wiring patterns A and B. As shown in FIG. FIG. 11 is a cross-sectional view showing an example of a cross section of the wiring patterns A and B. The wiring patterns A and B shown in FIG. 11 are transmission lines configured by, for example, microstrip lines, and are formed by, for example, wiring patterns having a width W and a thickness t formed on the upper surface of the dielectric substrate 12 having a thickness h. It is configured. A conductor pattern is formed on the lower surface of the dielectric substrate 12 so as to widely cover the lower surface of the dielectric substrate 12.

Then, the signal propagation speed V _p (m / sec) in the wiring patterns A and B is obtained by the following equation (1).

Here, when W = 0.15 mm, t = 0.035 mm, h = 0.2 mm, and the relative dielectric constant εr = 4.7 of the dielectric substrate 12, V _p = 1.65 × 10 ⁸ (m / sec) ) = 165 mm / nsec.

  Then, for example, as shown in FIG. 10, if the length of the wiring pattern A is 100 mm, and the length of the wiring pattern B is 120 mm longer than the wiring pattern A by the delay unit 11a, as shown in FIG. The signal S21b is delayed by 606 psec from the signal S21a by the wiring pattern A, and the signal S22b is delayed by 727 psec from the signal S22a by the wiring pattern B. As a result, the signal S22b is delayed by 121 psec from the signal S21b.

  Other configurations and operations are the same as those of the wireless transmission device 1 shown in FIG. Thus, the signal of the signal path from the modulation circuit 6 to the differential output unit 10 can be delayed by the delay unit 11a similarly to the delay unit 11, so that the pulse signal Sout is a Gaussian pulse. The delay unit 11a can be configured with a wiring pattern, so that the radio transmission circuit 4a and a radio using the same can be obtained. The transmitter 1a can be reduced in size and cost.

  Note that the delay unit 11a may be provided on any path on the path from the modulation circuit 6 to the differential output unit 10 via the step recovery diode circuit 92, and the driver unit 82 and the step recovery diode circuit 92 are connected to each other. Although not limited to the example provided in between, the oscillation circuit 2, the data generation unit 3, the modulation circuit 6, the pre-driver circuits 71 and 72, and the driver units 81 and 82 are integrated into an integrated circuit (IC) as one integrated circuit. Since the oscillation circuit 2 and the like are integrated into an IC, the delay unit 11a is provided between the driver unit 82 and the step recovery diode circuit 92 or between the step recovery diode circuit 92 and the differential output unit. If the delay portion 11a is provided between the delay portion 11a and the wiring pattern, the delay portion 11a can be easily configured by a wiring pattern.

  The delay unit 11a is not limited to the wiring pattern on the printed wiring board, and may be a transmission line. For example, the delay unit 11a may be configured by increasing the length of a signal path in a cable or IC.

(Third embodiment)
Next, a radio transmission apparatus and radio transmission circuit according to the third embodiment of the present invention will be described. FIG. 13 is a block diagram showing an example of a configuration of a wireless transmission device 1b using the wireless transmission circuit 4b according to the third embodiment of the present invention. The wireless transmission circuit 4b shown in FIG. 13 differs from the wireless transmission circuit 4 shown in FIG. 1 in that the delay unit 11b in which the delay time td is made variable instead of the delay unit 11 and the delay time td of the delay unit 11b are set. The difference is that it includes a setting switch 13 to be received.

  The setting switch 13 is configured using, for example, one or a plurality of dip switches or operation switches such as a rotary switch which is an example of a multi-contact switch, and sets a delay time td of the delay unit 11b according to a user setting. Control signals SEL0, SEL1, SEL2, and SEL3 are output to the delay unit 11b.

  FIG. 14 is a circuit diagram showing an example of the configuration of the delay unit 11b. The delay unit 11b shown in FIG. 14 includes a series circuit of a switch SW1 and a capacitor C1, and a series circuit of a switch SW2 and a capacitor C2, one end of which is connected to the signal path between the modulation circuit 6 and the predriver circuit 72. And a series circuit of a switch SW3 and a capacitor C3 and a series circuit of a switch SW4 and a capacitor C4. The other end of each series circuit is connected to the ground.

  The switches SW1, SW2, SW3, and SW4 are configured using transistors, for example, and are turned on and off in response to control signals SEL0, SEL1, SEL2, and SEL3 output from the setting switch 13.

  The capacitance of the capacitor C1 is C, the capacitance of the capacitor C2 is 2C that is twice that of the capacitor C1, the capacitance of the capacitor C3 is 4C that is four times that of the capacitor C1, and the capacitance of the capacitor C4 is 8 of the capacitor C1. The switch SW1, SW2, SW3, and SW4 are turned on and off in accordance with the control signals SEL0, SEL1, SEL2, and SEL3 output from the setting switch 13, and the modulation circuit 6 and the pre-driver circuit 72 are switched. Since the capacitance connected to the signal path between them changes, the delay time td can be changed according to the setting contents by the setting switch 13.

  Accordingly, the setting switch 13 is set so that the delay time td becomes, for example, 1/2 of the pulse width tw according to the pulse width tw (frequency of the signal to be transmitted) of the short pulse signal to be transmitted from the antenna 5. By setting, the delay time td can be adjusted to make the pulse signal Sout a Gaussian pulse signal waveform, and a favorable Gaussian pulse signal waveform can be obtained.

  The switches SW1, SW2, SW3, and SW4 are configured using operation switches such as a dip switch and a rotary switch, and the delay time td of the delay unit 11b is set by directly operating the switches SW1, SW2, SW3, and SW4. You may make it do. In this case, it is not necessary to provide the setting switch 13 separately.

(Fourth embodiment)
Next, a wireless transmission device and a wireless transmission circuit according to the fourth embodiment of the present invention will be described. FIG. 15 is a block diagram showing an example of a configuration of a wireless transmission device 1c using a wireless transmission circuit 4c according to the fourth embodiment of the present invention. When the bias voltage Vbias is changed in the step recovery diode circuits 91 and 92 shown in FIG. 3, the wireless transmission device 1c and the wireless transmission circuit 4c shown in FIG. 15 change the peak values of the modulation signals S31 and S32, and the pulse signal Sout The multi-level modulation is performed by expressing the information of a plurality of bits by the peak value of the pulse signal Sout using the change in the amplitude of the signal. As a result, for example, a wireless transmitter configured to transmit one bit using eight short pulse signals can transmit data of a plurality of bits using the same eight short pulse signals to increase the transmission speed. To do.

  The wireless transmission circuit 4c shown in FIG. 15 differs from the wireless transmission circuit 4 shown in FIG. 1 in the following points. That is, the wireless transmission circuit 4c shown in FIG. 15 further includes bias control circuits 61 and 62 that change the bias voltage Vbias of the step recovery diode circuits 91 and 92, respectively. In addition, the modulation circuit 6a includes a register 63 that temporarily stores the transmission data SD1 output from the data generation unit 3 by a plurality of bits, for example, by 2 bits.

  The modulation circuit 6 a outputs a control signal to the bias control circuits 61 and 62 in order to change the bias voltage Vbias based on the data of a plurality of bits temporarily stored by the register 63. The bias control circuits 61 and 62 are power supply circuits that change the bias voltage Vbias supplied to the step recovery diode circuits 91 and 92 in accordance with a control signal from the modulation circuit 6a.

  Since other configurations and operations are the same as those of the wireless transmission device 1 shown in FIG. 1 except for the following operations, description thereof will be omitted, and characteristic operations of the present embodiment will be described below. In the following description, an example in which 2 bits are multi-valued will be described. FIG. 16 is a signal waveform diagram for explaining the operation of the wireless transmission circuit 4c. First, the clock signal CLK1 generated based on the oscillation frequency of the crystal oscillator OSC1 by the oscillation circuit 2 is output to the modulation circuit 6a and the data generation unit 3.

  Then, the transmission data SD1 is output from the data generator 3 to the register 63 in synchronization with the clock signal CLK1, and the register 63 holds the data every two bits. In FIG. 16, transmission data SD1 represents one bit with four clocks of the clock signal CLK1, and represents “0” at a low level and “1” at a high level.

  The modulation circuit 6a changes the bias voltage Vbias in four steps according to the bit pattern “00”, “01”, “10”, and “11” of the number of bits for every two bits held by the register 63. A control signal is output to the bias control circuits 61 and 62 to change the peak value of the pulse signal Sout.

  As a result, the pulse signal Sout can be multi-valued and information for a plurality of bits can be transmitted with one pulse, so that the communication speed can be increased. Although the example in which the peak value of the pulse signal Sout is changed in four stages by changing the bias voltage Vbias in four stages and the information for two bits is multi-valued is shown, the stage of voltage change of the bias voltage Vbias is shown. Information of 3 bits or more may be multi-valued by increasing the number. Further, instead of the delay unit 11, the delay unit 11a, or the delay unit 11b and the setting switch 13 may be used.

(Fifth embodiment)
Next, a radio transmission apparatus and radio transmission circuit according to the fifth embodiment of the present invention will be described. FIG. 17 is a block diagram illustrating an example of a configuration of a wireless transmission device 1d according to the fifth embodiment of the present invention. In the wireless transmission device 1d and the wireless transmission circuit 4d shown in FIG. 17, when the operating power supply voltage VDD is changed in the driver units 81 and 82 shown in FIG. 2, the peak values of the signals S21 and S22 change, and the pulse signal Sout Using the change in amplitude, multi-level modulation is performed by expressing information of a plurality of bits as a peak value of the pulse signal Sout. As a result, for example, a wireless transmitter configured to transmit one bit using eight short pulse signals can transmit data of a plurality of bits using the same eight short pulse signals to increase the transmission speed. To do.

  The wireless transmission circuit 4d shown in FIG. 17 is different from the wireless transmission circuit 4c shown in FIG. 15 in the following points. That is, the wireless transmission circuit 4 d shown in FIG. 17 is different in that it includes VDD control circuits 64 and 65 instead of the bias control circuits 61 and 62. The modulation circuit 6 b outputs a control signal to the VDD control circuits 64 and 65 in order to change the operation power supply voltage VDD based on a plurality of bits of data temporarily stored by the register 63. The VDD control circuits 64 and 65 are power supply circuits that change the operation power supply voltage VDD supplied to the driver units 81 and 82 in accordance with a control signal from the modulation circuit 6b.

  Since other configurations and operations are the same as those of the wireless transmission device 1c shown in FIG. 15 except for the following operations, the description thereof will be omitted, and the characteristic operations of the present embodiment will be described below. In the following description, an example in which 2 bits are multi-valued will be described. FIG. 18 is a signal waveform diagram for explaining the operation of the wireless transmission circuit 4d. First, the clock signal CLK1 generated based on the oscillation frequency of the crystal oscillator OSC1 by the oscillation circuit 2 is output to the modulation circuit 6b and the data generation unit 3.

  Then, the transmission data SD1 is output from the data generator 3 to the register 63 in synchronization with the clock signal CLK1, and the register 63 holds the data every two bits. In FIG. 18, transmission data SD1 represents one bit with four clocks of the clock signal CLK1, and represents “0” at a low level and “1” at a high level.

  Then, for every two bits held by the register 63, the modulation circuit 6b sets the operation power supply voltage VDD in four stages according to the bit pattern “00”, “01”, “10”, “11” of the number of bits. A control signal is output to the VDD control circuits 64 and 65 to change the pulse signal Sout to the peak value of the pulse signal Sout.

  As a result, the pulse signal Sout can be multi-valued and information for a plurality of bits can be transmitted with one pulse, so that the communication speed can be increased. Although the example in which the peak value of the pulse signal Sout is changed in four stages by changing the operating power supply voltage VDD in four stages and the information for two bits is multi-valued has been shown, Information of 3 bits or more may be multi-valued by increasing the number of voltage change steps.

  Further, the bias control circuits 61 and 62 may be further provided, and the peak value of the pulse signal Sout may be changed to be multi-valued by a combination of voltage changes of the operation power supply voltage VDD and the bias voltage Vbias. Further, instead of the delay unit 11, the delay unit 11a, or the delay unit 11b and the setting switch 13 may be used.

It is a block diagram which shows an example of a structure of the wireless transmission device and wireless transmission circuit which concern on the 1st Embodiment of this invention. FIG. 2 is a circuit diagram illustrating an example of a configuration of a pre-driver circuit and a driver unit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a configuration of a step recovery diode circuit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a configuration of a differential output unit illustrated in FIG. 1. FIG. 3 is a signal waveform diagram for explaining the operation of the wireless transmission device 1 shown in FIG. 1. It is explanatory drawing which shows an example of the waveform of a Gaussian pulse. It is explanatory drawing which shows energy distribution of a Gaussian pulse. FIG. 20A is a signal waveform diagram illustrating an example of a pulse signal waveform output from a bandpass filter in the wireless transmission circuit according to the background art illustrated in FIG. 19. FIG. 2B is a signal waveform diagram illustrating a signal waveform of the pulse signal Sout output from the wireless transmission circuit illustrated in FIG. 1. It is a block diagram which shows an example of a structure of the radio transmission apparatus and radio transmission circuit which concern on the 2nd Embodiment of this invention. It is explanatory drawing which shows an example of the wiring patterns A and B shown in FIG. It is sectional drawing which shows an example of the cross section of the wiring patterns A and B shown in FIG. 10 is a timing chart showing signal delays due to wiring patterns A and B shown in FIG. 9. It is a block diagram which shows an example of a structure of the wireless transmission device and wireless transmission circuit which concern on the 3rd Embodiment of this invention. It is a circuit diagram which shows an example of a structure of the delay part shown in FIG. It is a block diagram which shows an example of a structure of the radio transmission apparatus and radio transmission circuit which concern on the 4th Embodiment of this invention. FIG. 16 is an explanatory diagram for describing an operation of the wireless transmission circuit illustrated in FIG. 15. It is a block diagram which shows an example of a structure of the wireless transmission device and wireless transmission circuit which concern on the 5th Embodiment of this invention. It is explanatory drawing for demonstrating operation | movement of the radio | wireless transmission circuit shown in FIG. It is a block diagram which shows the structure of the wireless transmission circuit of the ultra wide band communication system which concerns on background art. It is a graph which shows the spectrum mask prescribed | regulated by the US Federal Communications Commission.

Explanation of symbols

1, 1a, 1b, 1c, 1d Radio transmission device 2 Oscillation circuit 3 Data generation unit 4, 4a, 4b, 4c, 4d Radio transmission circuit 5 Antenna 6, 6a, 6b Modulation circuit 10 Differential output unit 11, 11a, 11b Delay unit 13 Setting switch 61, 62 Bias control circuit 63 Register 64, 65 VDD control circuit 71, 72 Pre-driver circuit 81, 82 Driver unit 91, 92 Step recovery diode circuit 93 High pass filter 94 Voltage-current conversion element A, B Wiring Pattern C1, C2, C3, C4 Capacitor QN1, QP1, QN2, QP2 Transistor SRD Step recovery diode SW1, SW2, SW3, SW4 Switch

Claims (7)

In a wireless transmission circuit that transmits transmission data by a wireless signal using a pulse,
A modulation unit that outputs a pulse signal according to a logical value of each bit in the transmission data;
A first step recovery diode that generates a first modulated signal that generates a high-frequency signal component based on the pulse signal output from the modulator;
A delay unit that delays the pulse signal output from the modulation unit by a predetermined delay time;
A second step recovery diode that generates a second modulated signal that generates a high-frequency signal component based on the pulse signal delayed by the delay unit;
A radio transmission circuit comprising: a differential output unit that generates a difference signal by taking a difference between the first and second modulation signals generated by the first and second step recovery diodes. The radio transmission circuit according to claim 1, wherein a delay time by the delay unit is set to ½ of a pulse width of the radio signal. The wireless transmission circuit according to claim 1, wherein the delay unit is configured using a transmission line that generates a propagation delay time corresponding to the delay time. The wireless transmission circuit according to claim 1, wherein the delay unit is configured using a series circuit of a plurality of switches and capacitors connected to the signal path. The modulation unit changes the bias voltage supplied to the step recovery diode in accordance with the bit pattern of the number of bits for each preset number of bits in the transmission data, thereby changing the pulse of the radio signal pulse. The wireless transmission circuit according to claim 1, wherein a peak value is changed. A first step is provided between the modulation unit and the first and second step recovery diodes to increase the drive currents in the pulse signals output from the modulation unit to the first and second step recovery diodes, respectively. A first driver portion and a second driver portion;
The modulation unit changes the power supply voltage for operation of the first and second driver units according to a bit pattern of the number of bits for each preset number of bits in the transmission data, whereby the radio signal The radio transmission circuit according to claim 1, wherein a peak value of a pulse for use is changed. In a wireless transmission device that transmits transmission data by a wireless signal using a pulse,
A data generation unit for generating the transmission data;
Based on the transmission data generated by the data generation unit, a wireless transmission circuit that outputs a pulse for a wireless signal representing the transmission data;
An antenna that radiates pulses output by the wireless transmission circuit;
The wireless transmission circuit according to claim 1, wherein the wireless transmission circuit is the wireless transmission circuit according to claim 1.

Images