JP4574784B2 - Semiconductor device and layout method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to layout how the semiconductor device and the semiconductor device mounted with a memory such as a dynamic RAM.
[0002]
[Prior art]
Improves soft error resistance due to alpha rays, cuts off electromagnetic wave noise radiated from other electronic components and noise from the logic circuit in a semiconductor device that has a memory circuit and logic circuit such as dynamic RAM mounted on a single chip As a means for realizing effective utilization of the metal wiring area on the memory circuit section, the memory circuit section is covered with a metal pattern connected to a constant potential such as a ground potential, and metal wiring is provided in an empty area on the metal pattern. It has been proposed to configure (for example, JP-A-11-274424).
[0003]
[Problems to be solved by the invention]
However, when a metal pattern that covers the memory circuit portion is formed on the memory circuit portion configured by n-layer wiring, and further a wiring pattern region is formed on the metal pattern, the number of layer wiring layers in the entire chip is at least When the (n + 2) layer is required and the wiring of the logic part is composed of (n + 1) layers, the memory part cannot be used as a wiring area. Even when the wiring of the logic part is composed of (n + 2) layers, only one layer of wiring on the memory part can be used, so the degree of freedom of wiring layout is reduced.
[0004]
Thus, when a logic part and a memory part with a relatively small number of wiring layers are mounted, there is a problem that the memory part cannot be used as a wiring area or cannot be used effectively.
[0005]
In general, the number of wiring layers in the memory unit is smaller than the number of wiring layers in the logic unit. However, when automatic layout is performed using an automatic placement and routing tool, It is common to recognize the shape data and pin information of each macro block and perform wiring between macro blocks, and prohibit wiring between macro blocks within each macro block. Since the part cannot be used as a wiring region, there is a problem that the chip area increases. Further, there is a problem that the design man-hour increases even when the layout design is performed manually and the memory section is effectively used as a wiring area.
[0006]
Accordingly, an object of the present invention, the upper memory unit can be effectively utilized as a wiring area, to provide a layout how the semiconductor device and the semiconductor device can be reduced and the chip area.
[0007]
Another object of the present invention is to provide a layout how the semiconductor device and a semiconductor device which can realize a significant reduction of the number of design steps.
[0008]
[Means for Solving the Problems]
The semiconductor device according to claim 1 is a semiconductor device having a memory part having a memory cell array region on one chip and a logic part, wherein a memory circuit formed in the memory part is composed of n-layer wiring, and the logic part includes The logic circuit to be formed is formed with (n + m) layer wiring, and a metal pattern is formed in a shape covering at least the memory cell array region in the (n + 1) layer on the memory circuit, and a metal wiring pattern connected to the logic portion is formed. Formed in the same wiring layer as the metal pattern , the memory cell array region is arranged in a matrix, and the word line backing region is arranged adjacently between the memory cell array regions arranged in the matrix and connected to the logic unit. a plurality of metal wiring pattern that is characterized by being formed on the (n + 1) th layer on the word line backing region Than is.
[0009]
According to the semiconductor device of claim 1, for example, the metal pattern supplies at least a constant potential to the memory unit, and at least one of the metal wiring patterns is necessary when electrically connected to the pad unit or the logic circuit unit. A stable and constant potential can be supplied to the location. In addition, alpha rays incident on the chip surface from the package resin or from the outside can be attenuated by the metal pattern provided on the memory cell to reduce the frequency of occurrence of soft errors inside the memory cell. In addition to being able to perform stable operation, the same wiring layer as the metal pattern provided on the memory cell and the DRAM block can be used effectively as a wiring area between the logic circuit blocks. A wiring pattern with a high degree of freedom can be formed.
[0011]
In addition, since the memory circuit on which no metal pattern is formed can be used as a wiring region between the logic circuit and the pad portion, the wiring length can be shortened and the layout area can be reduced, and the characteristics of the logic circuit portion can be improved and the chip area can be reduced. .
[0012]
Layout method of a semiconductor device according to the second aspect, when it row automatic layout by using the layout data, the n layer memory macro formed of wire, the layout data only when (n + 1) th layer of automatic wiring applying the recognition data that may be used as the shape data, a layout method of a semiconductor device that uses an area other than the area covered by the shape data as an automatic wiring layout region, and the memory macro recognition data of shapes including memory macro, A logical product of the memory macro recognition data and the automatic wiring prohibited region recognition data is obtained from the automatic wiring prohibited region recognition data, and this logical product is used as memory macro shape data .
[0013]
According to the layout method of the semiconductor device according to claim 2, limits on the memory macro can be used as a wiring region, the automatic placement and routing tools can be easily applied, it can be shortened and reduced chip area of design time.
[0015]
In addition, for example, by inputting a wiring prohibition area designating layer to a DRAM macro and using it as the shape data of the DRAM macro, it can be easily applied to an automatic placement and routing tool, so that the design man-hour can be greatly reduced.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0023]
(Embodiment 1)
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.
[0024]
FIG. 1 is a block diagram showing the configuration of the first embodiment. As shown in FIG. 1, reference numeral 1 denotes a semiconductor device having a DRAM block 2, a logic circuit block 3, and a pad group 4 which are memory portions. The DRAM block 2 includes a memory cell block 5 including a sense amplifier group and a memory cell group, a row decoder unit 6, a column decoder unit 7, a memory control circuit unit 8 including a substrate potential generation circuit and a reference potential generation circuit, and a read amplifier unit 9. It is composed of The logic circuit block 3 is assumed to be composed of a CMOS circuit. A region 10 indicated by a dotted line is a region where an aluminum layer is formed, and an aluminum layer is formed on the DRAM block 2 so as to cover at least the memory cell group. The aluminum layer formed in the region 10 is fixed to the ground node or the power supply node. Reference numerals 11 and 12 denote aluminum wirings for connecting the memory block 2, the logic block 3, and the pad group 4 to each other. Of these, 11 is an aluminum signal wiring formed of the same wiring layer as the aluminum layer covering at least the memory cell group, and 12 is an aluminum signal wiring formed of a wiring layer above the signal wiring 11.
[0025]
Actually, the connection relationship among the DRAM block 2, the logic block 3, and the pad group 4 is connected in accordance with the specification, and only a part thereof is shown in the drawing.
[0026]
Next, the configuration of the DRAM block will be described with reference to FIG.
[0027]
FIG. 2 is a block diagram showing an example of the configuration of the DRAM block 2 shown in FIG. 1. A memory cell block 5 including a sense amplifier group and a memory cell group, a row decoder unit 6, a column decoder unit 7, a substrate potential generating circuit, The memory control circuit unit 8 includes a reference potential generation circuit, and a read amplifier unit 9. Further, the memory cell block 5 includes a memory cell array region 13 having a plurality of memory cells arranged in a matrix, a sense amplifier region 14 having a plurality of sense amplifiers, and a word line backing region 15. A region 10 indicated by a dotted line is an aluminum layer formation region, and an aluminum layer is formed so as to cover the memory cell array region 13. Reference numerals 11 and 12 denote aluminum wirings for connecting the memory block 2, the logic block 3, and the pad group 4 described in FIG. Among these, 11 is an aluminum signal wiring formed of the same wiring layer as the aluminum layer forming region, and 12 is an aluminum signal wiring formed of a wiring layer above the signal wiring 11.
[0028]
Incidentally, the sense amplifier amplifies data of the memory cell selected by the address signal, and is intended to latch word line backing region 15 is disposed adjacent to the memory cell array region 13, the backing of the word line This is a region provided for performing
[0029]
FIG. 3 shows a part of a cross section of the semiconductor device 1 shown in FIG. 1, and shows a cross-sectional structure of a layer above the semiconductor substrate. A memory cell array region 13 is formed in the A portion, a sense amplifier region 14 and a word line backing region 15 are formed in the B portion, and a logic circuit block 3 is formed in the C portion. The DRAM block 2 has a two-layer wiring structure (first layer wiring and second layer wiring) as shown in A and B, and the logic circuit block 3 has a three-layer wiring structure (first layer wiring to third layer wiring). Eye wiring).
[0030]
16 is a semiconductor substrate, 17 is an element isolation region, 18 is a diffusion layer, 19 (a) is a DRAM word line, 19 (b) is a gate electrode of an n-channel transistor of a sense amplifier driving circuit in the sense amplifier region, 19 (c) ) Is the gate electrode of the p-channel transistor of the sense amplifier drive circuit in the sense amplifier region. Reference numeral 20 denotes a cell plate electrode of the DRAM memory cell, 21 denotes a storage electrode of the DRAM memory cell, and the cell plate electrode 20 and the storage electrode 21 form a cylindrical stack type memory cell. Further, in FIG. 3, both the bit line 22 (a) of the DRAM block and the wiring 22 (b) of the logic circuit block are formed of the first layer aluminum. Similarly, the word line 23 (a) of the DRAM block and the sense amplifier The control signal 23 (b) and the logic circuit block wiring 23 (c) are both formed of second-layer aluminum. Aluminum 24 (a) and 24 (b) (corresponding to the region 10 in which the aluminum layer is formed in FIG. 2) covering the entire memory cell array region, the wiring 24 (c) in the word line backing region, and the wiring of the logic circuit block Both 24 (d) are formed of the third layer aluminum. Both the DRAM block wiring 25 (a) and the logic circuit block wiring 25 (b) are formed of fourth-layer aluminum. Reference numeral 26 denotes a package resin.
[0031]
Here, the wiring 24 (c) in the word line backing region is formed of the same wiring layer as the aluminum 24 (a) and 24 (b) covering the entire memory cell array region, and the connection between the logic circuit blocks and the logic circuit block Is used to connect the pad area and the pad area. Further, the wiring 25 (a) of the DRAM block can be freely formed on the memory block.
[0032]
Although not shown in FIG. 3, the word line 19 (a) of the DRAM block and the word line 23 (a) formed of the second aluminum are connected in parallel at the word line backing region 15 and are effective. Wiring resistance is kept low. Also, a stable ground level is supplied from the aluminum 24 (a) covering the entire memory cell array region to the diffusion layer, which is the source region of the n-channel transistor of the sense amplifier driving circuit, via the inter-wiring contact, and the aluminum 24 (b) Has a function of supplying a stable power supply level to the diffusion layer which is the source region of the p-channel transistor of the sense amplifier driving circuit through the inter-wiring contact.
[0033]
Note that the potential applied to the aluminum patterns 24 (a) and 24 (b) is not limited to the ground level or the power supply level, and the same effect can be obtained even if a constant potential generated in the chip is given. it can.
[0034]
In the above embodiment, aluminum is used as the material for the wiring layer. However, the present invention is not limited to this, and other metals such as copper may be used.
[0035]
Further, the total number of metal wirings is also arbitrary. In the first embodiment, the DRAM block has a two-layer wiring structure and the logic circuit block has a four-layer wiring structure. When the number of wirings of the DRAM circuit block is n (n = 1, 2, 3,...), It is most effective to use the (n + 2) layer as the logic circuit block.
[0036]
Further in the first embodiment shows a semiconductor device using a DRAM as a structure of the memory cell array 5, also SRAM or flash memory have a structure that employs a memory cell array, the present invention It goes without saying that applies. Further, the configuration of the logic circuit block 3 is not limited to a CMOS circuit but may be a Bi-CMOS configuration.
[0037]
In the first embodiment, the aluminum patterns 24 (a) and 24 (b) cover only the memory cell array region. However, like the memory cell, the sense amplifier region or dynamic Even if it is applied to the circuit section, the same effect can be obtained.
[0038]
In the semiconductor device configured as described above, the frequency of occurrence of a soft error in the DRAM block 2 because α rays incident on the chip surface from the package resin 26 or from the outside are attenuated by the aluminum pattern 24 (a) or 24 (b). Is reduced.
[0039]
Further, the wiring 24 (c) in the word line backing region is formed of the same wiring layer as the aluminum 24 (a) and 24 (b) covering the entire memory cell array region, and the connection between the logic circuit blocks and the logic circuit block Since it is used for connection to the pad area, the DRAM block can be used effectively as a wiring area for the logic circuit block, the layout area can be reduced, and the wiring length of the logic circuit block can be reduced. It is possible to improve performance such as higher speed and lower power consumption.
[0040]
As described above, the semiconductor device according to the first embodiment is formed in the memory portion in the semiconductor device having the memory portion and the logic portion including the memory cell array region, the sense amplifier region, the decoder region, and the memory control circuit region on one chip. The memory circuit to be formed is composed of n layer wiring, and the logic circuit formed in the logic portion is composed of (n + m) layer (where n = 1, 2, 3,..., M = 1, 2, 3,...) Wiring. , to form at least a metal pattern covering the memory cell array portion, at least one metal wire in the same wiring layer and the metal pattern covering the memory cell array portion in the memory circuit (n + 1) th layer of the wiring layer The metal pattern supplies at least a constant potential to the memory portion, and at least one of the metal wirings is electrically connected to the pad portion or the logic circuit portion.
[0041]
With this configuration, it is possible to supply a stable and constant potential to a necessary place, and the metal pattern attenuates alpha rays incident from the package resin or the outside, so that the frequency of occurrence of soft errors inside the memory cell is reduced. . Furthermore, since the memory circuit on which no metal pattern is formed can be used as a wiring area between the logic circuit and the pad part, the wiring length can be shortened and the layout area can be reduced, and the characteristics of the logic circuit part can be improved and the chip area can be reduced. .
[0042]
(Embodiment 2)
Next, the layout method of the semiconductor device and the configuration of the DRAM macro according to the second embodiment of the present invention will be described with reference to FIGS. 4, 5A, and 5B.
[0043]
FIG. 4 is a block diagram illustrating a layout configuration according to the second embodiment. In FIG. 4, 27 is the layout area of the entire chip of the semiconductor device, 28 is the shape data of the DRAM macro, 29 is the shape data of the logic circuit block, and 30 is the shape data of the pad portion. The frame data is input according to the macro library specification for the purpose of recognizing the shape of the macro block in each macro block so that it can be generated using a wiring tool.
[0044]
Reference numeral 10 denotes an aluminum pattern (a region where an aluminum layer is formed) covering the memory cell region shown in the first embodiment. Reference numeral 31 denotes an aluminum fuse region, which cuts a specific fuse in the aluminum fuse region 31 with a laser beam or the like to form a fuse group capable of switching the circuit operation. Generally, this fuse group is formed in the uppermost layer of aluminum wiring used in the chip. Reference numeral 32 denotes a third-layer aluminum wiring prohibited area that is input so as to cover the aluminum pattern 10 that covers the memory cell area. Reference numeral 33 denotes an aluminum wiring all-layer wiring prohibited area that is input so as to cover the fuse area 31.
[0045]
5A and 5B show macroblock shape data recognized by the automatic placement and routing tool, and FIG. 5A shows shape data for the third-layer aluminum wiring. 5 (b) shows shape data for the fourth-layer aluminum wiring. In FIG. 5A, reference numeral 28 denotes DRAM macro shape data, which is data for recognizing the shape of the DRAM macro when the first and second layer aluminum wirings are provided. The DRAM macro shape data 28 is a predetermined layer and is input as DRAM macro layout data. Unlike the logic circuit block shape data, the DRAM macro shape data 28 uses a layer dedicated to the DRAM section.
[0046]
As shown in FIG. 5A, only when the third-layer aluminum wiring is performed, the third-layer aluminum wiring prohibition region 32 and the fuse region 31 that are input so as to cover the aluminum pattern 10 covering the memory cell region are covered. The aluminum wiring all-layer wiring prohibition area 33 input in the form is used as DRAM macro shape data.
[0047]
In addition to the DRAM portion, DRAM macro shape data 28 and all aluminum wiring layers are provided so that no problem occurs even if the third-layer aluminum wiring prohibition region 32 and the aluminum wiring all-layer wiring prohibition region 33 exist. The logical product of the wiring prohibited area 33 is used as shape data for the third layer aluminum wiring of the DRAM macro that is recognized by the automatic placement and routing tool.
[0048]
Further, as shown in FIG. 5B, only when the fourth-layer aluminum wiring is performed, the aluminum wiring all-layer wiring prohibition area 33 input so as to cover the fuse area 31 is used as the shape data of the DRAM portion. In addition to the DRAM unit, the logical product of the DRAM macro shape data 28 and the aluminum wiring all-layer wiring prohibited area 33 is automatically arranged so that no problem occurs even if the aluminum wiring all-layer wiring prohibiting area 33 exists. The shape data for the 4-layer aluminum wiring of the DRAM macro recognized by the wiring tool is used.
[0049]
In the layout method of the semiconductor device configured as described above, on the DRAM block formed with the two-layer aluminum wiring structure, the third and fourth layer aluminum wirings are limited, and the wiring area between the logic blocks Furthermore, since it can be easily applied to an automatic placement and routing tool, the design period can be shortened, the chip area can be reduced, and the performance of the logic circuit block can be easily improved.
[0050]
In the second embodiment, aluminum is used as the material for the wiring layer. However, the present invention is not limited to this, and other metals such as copper may be used.
[0051]
Furthermore, the total number of metal wirings is also arbitrary, and in the second embodiment, the DRAM block has a two-layer wiring structure and the logic circuit block has a four-layer wiring structure, but is not particularly limited.
[0052]
(Embodiment 3)
Next, a semiconductor device layout method and a DRAM macro configuration according to a third embodiment of the present invention will be described with reference to FIG.
[0053]
FIG. 6 is a block diagram illustrating the configuration of the third embodiment. Note that components similar to the layout configuration of the semiconductor device described with reference to FIGS. 1 to 5 are denoted by the same reference numerals and description thereof is omitted. Reference numeral 34 in FIG. 6 denotes a third aluminum wiring layer group configured as DRAM macro layout data. Note that the third aluminum wiring layer group 34 is a floating pattern that is not connected to other potentials in the DRAM macro alone, and is used for connection between the logic circuit blocks and between the pads and the logic circuit blocks. The third aluminum layer 34 is composed of the same wiring layer as the aluminum pattern 10 covering the memory cell region in the DRAM macro, and is operatively provided on the second layer aluminum wiring fixed to the power source or the ground node. It is configured in a stable region.
[0054]
Further, by adding a unique signal name and DRAM block shape data 28 to the third aluminum wiring layer group 34, it can be easily applied to an automatic placement and routing tool, in addition to the effect of reducing the design man-hours and the chip size. The adverse effects of the DRAM block and the logic circuit block due to noise and the like can be suppressed, and the circuit operation of both the DRAM block and the logic circuit block can be stabilized.
[0055]
The DRAM block occupies a large proportion of the entire chip, and the third aluminum wiring layer group 34 is generally wired in parallel in the DRAM block, and a data bus between the logic circuit blocks. It is likely to be used as a line. Therefore, by setting the width and interval of the aluminum wiring of the third aluminum wiring layer group 34 to a dimension about twice or more of the design rule and laying out at an equal pitch, the capacitance between adjacent wirings of the third aluminum wiring layer group 34 can be reduced. Reduction and coupling noise can be reduced, and more stable operation of the logic circuit block can be realized.
[0056]
Furthermore, a plurality of types of metal wiring patterns having different wiring widths and wiring intervals can be formed.
[0057]
【The invention's effect】
According to the semiconductor device of claim 1, for example, the metal pattern supplies at least a constant potential to the memory unit, and at least one of the metal wiring patterns is necessary when electrically connected to the pad unit or the logic circuit unit. A stable and constant potential can be supplied to the location. In addition, alpha rays incident on the chip surface from the package resin or from the outside can be attenuated by the metal pattern provided on the memory cell to reduce the frequency of occurrence of soft errors inside the memory cell. In addition to being able to perform stable operation, the same wiring layer as the metal pattern provided on the memory cell and the DRAM block can be used effectively as a wiring area between the logic circuit blocks. A wiring pattern with a high degree of freedom can be formed.
[0058]
In addition, since the memory circuit on which no metal pattern is formed can be used as a wiring region between the logic circuit and the pad portion, the wiring length can be shortened and the layout area can be reduced, and the characteristics of the logic circuit portion can be improved and the chip area can be reduced. .
[0059]
According to the layout method of the semiconductor device according to claim 2, limits on the memory macro can be used as a wiring region, the automatic placement and routing tools can be easily applied, it can be shortened and reduced chip area of design time.
[0060]
In addition, for example, by inputting a wiring prohibition area designating layer to a DRAM macro and using it as the shape data of the DRAM macro, it can be easily applied to an automatic placement and routing tool, so that the design man-hour can be greatly reduced.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram viewed from a plane showing a configuration of a first embodiment of the present invention;
FIG. 2 is an explanatory diagram viewed from above showing a configuration of a DRAM block according to the first embodiment of the present invention;
FIG. 3 is a partial sectional view showing the configuration of the first exemplary embodiment of the present invention.
FIG. 4 is an explanatory diagram viewed from a plane showing a configuration of a second embodiment of the present invention.
5A is an explanatory diagram showing shape data for the third layer aluminum wiring of the DRAM block of the second embodiment, and FIG. 5B is an explanatory diagram showing shape data for the fourth layer aluminum wiring; FIG.
FIG. 6 is an explanatory diagram showing a configuration of a third exemplary embodiment of the present invention.
FIG. 7 is an explanatory diagram showing a configuration of a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 DRAM block 3 Logic circuit block 4 Pad group 5 Memory cell block 6 Row decoder part 7 Column decoder part 8 Memory control circuit part 9 Read amplifier part 10 Aluminum pattern 11 3rd layer aluminum wiring 12 4th layer aluminum wiring 13 Memory cell array region 14 Sense amplifier region 15 Word line backing region 16 Semiconductor substrate 17 Element isolation region 18 Diffusion layer 19 (a) DRAM word line 19 (b) Gate electrode 19 (c) of n channel transistor of sense amplifier driving circuit Sense P-channel transistor gate electrode 20 of amplifier driving circuit cell plate electrode 21 of DRAM memory cell storage node electrode 22 of DRAM memory cell bit line 22 (b) of DRAM block first layer aluminum wiring 23 of logic circuit block ( ) Word line backing wiring 23 (b) of DRAM block Sense amplifier control signal 23 (c) Second layer aluminum wiring 24 (a), 24 (b) of logic circuit block Third layer aluminum wiring 24 (c) covering the memory cell array ) Third-layer aluminum wiring 24 (d) in the word line backing region Third-layer aluminum wiring 25 (a) in the logic circuit block Fourth-layer aluminum wiring 25 (b) in the DRAM block Fourth-layer aluminum wiring 26 in the logic circuit block Package resin 27 Chip layout area 28 DRAM macro shape data 29 Logic circuit block shape data 30 Pad portion shape data 31 Aluminum fuse area 32 Third layer aluminum wiring prohibited area 33 Aluminum wiring all layer prohibited area 34 Third layer aluminum wiring Group

Claims (2)

A semiconductor device having a memory portion and a logic portion having a memory cell array region on one chip,
The memory circuit formed in the memory unit is configured by n-layer wiring, the logic circuit formed in the logic unit is formed by (n + m) layer wiring, and at least the (n + 1) layer on the memory circuit A metal pattern is formed in a shape covering the memory cell array region, and a metal wiring pattern connected to the logic part is formed of the same wiring layer as the metal pattern ,
The memory cell array regions are arranged in a matrix, and word line backing regions are arranged adjacently between the memory cell array regions arranged in a matrix.
A plurality of metal wiring patterns connected to the logic part are formed in the (n + 1) th layer on the word line backing region. In performing automatic layout using layout data, recognition data that can be used as shape data of the layout data is applied only to the (n + 1) -th layer automatic wiring in a memory macro formed by n-layer wiring, A layout method of a semiconductor device that uses an area other than an area covered with shape data as an automatic wiring layout area,
A memory macro recognition data of the shape including the memory macros, more automatic wire protected area recognition data, obtains a logical product of the memory macro recognition data and the automatic wire protected area recognition data, the memory macro logical product A method for laying out a semiconductor device, characterized by :

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