JP2001257266A - Semiconductor device, layout method therefor and layout constitution - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, in a semiconductor device which hybridly mounts a memory such as DRAM and logic circuits, a metal pattern covering memory cell regions is laid on the memory to form wiring regions among the logic circuits on the metal pattern, but it is effective only when the number of wiring layers of logic parts is larger by two layers or more than the number of wiring layers of the memory. SOLUTION: A metal pattern 10 is laid on a region covering the almost of memory cell regions in a DRAM block 2, metal wirings 11 are formed from the same wiring layer as the metal pattern 10, the metal pattern 10 is to feed desired parts of the memory block with a fixed potential, and the metal wirings 11 interconnect logic circuit blocks 3 or pads 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a dynamic RA.
The present invention relates to a semiconductor device equipped with a memory such as M, a layout method and a layout configuration of the semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device having a memory circuit unit such as a dynamic RAM and a logic circuit unit mounted on one chip, improvement in soft error resistance due to α-rays, electromagnetic wave noise radiated from other electronic components, and logic circuit unit As a means for realizing both the isolation of noise from noise and the effective use of the metal wiring area on the memory circuit section, the memory circuit section is covered with a metal pattern connected to a constant potential such as a ground potential, and an empty space on the metal pattern is provided. It has been proposed to form a metal wiring in a region (for example, Japanese Patent Application Laid-Open No. H11-274424).

[0003]

However, when a metal pattern covering the memory circuit portion is formed on the memory circuit portion formed by the n-layer wiring and a wiring pattern region is further formed on the metal pattern, the entire chip is formed. In (2), at least (n + 2) layers are required, and when the wiring of the logic section is composed of (n + 1) layers, the memory section cannot be used as a wiring area. Further, even when the wiring of the logic part is configured by the (n + 2) layer,
Since only one layer of wiring on the memory unit can be used, the degree of freedom in wiring layout is reduced.

As described above, when a logic section and a memory section having a relatively small number of wiring layers are mounted, there is a problem that the memory section cannot be used as a wiring area or cannot be used effectively.

Although the number of wiring layers in the memory section is generally smaller than the number of wiring layers in the logic section, when the automatic layout is performed using the automatic placement and routing tool, Generally, wiring between macro blocks is performed by recognizing the shape data of macro blocks and pin information of each macro block, and wiring between macro blocks is prohibited in each macro block. Since the tool cannot use the memory area as a wiring area, there is a problem that the chip area increases. Further, even when the layout is manually designed and the memory area is effectively used as a wiring area, there is a problem that the number of design steps increases.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device, a layout method and a layout structure of a semiconductor device, which can effectively utilize a memory area as a wiring area and reduce a chip area.

Another object of the present invention is to provide a semiconductor device, a layout method of the semiconductor device, and a layout configuration which can realize a great reduction in design man-hours.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor device having a memory portion including a memory cell array region, a sense amplifier region, a decoder region, and a memory control circuit region and a logic portion on a single chip. The memory circuit formed in the memory section is formed by n-layer wiring, the logic circuit formed in the logic section is formed by (n + m) -layer wiring, and at least the memory cell array A metal pattern is formed in a shape covering the region, and a metal wiring pattern connected to the logic portion is formed in the same wiring layer as the metal pattern.

According to the semiconductor device of the present invention, for example, the metal pattern supplies a constant potential to at least the memory section, and at least one of the metal wiring patterns is electrically connected to the pad section or the logic circuit section. Thus, a stable constant potential can be supplied to a required portion. Moreover, α-rays incident on the chip surface from the package resin or from the outside can be attenuated by the metal pattern provided on the memory cell, reducing the frequency of soft errors occurring inside the memory cell. A stable operation can be performed, and the same wiring layer as the metal pattern provided on the memory cell can be effectively used on the DRAM block as a wiring area between logic circuit blocks. A wiring pattern having a high degree of freedom can be formed.

According to a second aspect of the present invention, in the semiconductor device shown in FIG. 1, a plurality of logic units connected to a logic unit are provided on a word line lining region arranged adjacent to a memory cell array region arranged in a matrix. This is for forming a metal wiring pattern.

According to the semiconductor device of the second aspect, in addition to the same effects as those of the first aspect, the memory circuit on which the metal pattern is not formed can be used as a wiring area between the logic circuit and the pad portion. It is possible to shorten the layout and the layout area, improve the characteristics of the logic circuit section, and reduce the chip area.

According to a third aspect of the present invention, there is provided a semiconductor device layout method for performing an automatic layout using layout data, wherein a (n + 1) th layer is included in a memory macro formed by n-layer wirings. In this method, recognition data that can be used as shape data of layout data is applied only at the time of automatic wiring, and an area other than the area covered by the shape data is used as an automatic wiring layout area.

According to the semiconductor device layout method of the present invention, the memory macro can be restricted and used as a wiring area, and the automatic placement and routing tool can be easily applied.
The design period and the chip area can be reduced.

According to a fourth aspect of the present invention, in the semiconductor device layout method according to the third aspect, the memory macro recognition data and the automatic wiring prohibited area are obtained from the memory macro recognition data having a shape including the memory macro and the automatic wiring prohibited area recognition data. The logical product of the recognition data is obtained, and this logical product is used as the shape data of the memory macro.

According to the layout method of a semiconductor device according to the fourth aspect, in addition to the same effects as those of the third aspect, for example, DR
Input the wiring prohibited area designation layer to the AM macro, and
By using the data as the shape data of the M macro, it can be easily applied to an automatic placement and routing tool, so that the number of design steps can be significantly reduced.

According to a fifth aspect of the present invention, there is provided a semiconductor device having a memory section including a memory cell array area and a logic section,
The memory circuit formed in the memory macro of the memory unit is configured by n-layer wiring, and the (n + 1) th layer on the memory macro is
A metal pattern is formed so as to cover at least the memory cell array region, and a plurality of metal wiring patterns connected to the logic portion are formed in the same wiring layer as the metal pattern.

According to the layout configuration of the semiconductor device according to the fifth aspect, for example, an aluminum pattern covering a memory cell region is provided in an operatively stable region in a DRAM macro for use as a wiring between logic circuit blocks. By configuring the aluminum pattern composed of the same wiring layer as the data of the DRAM macro, it is possible to suppress the adverse effects of the noise and the like between the DRAM block and the logic circuit block. A stable circuit operation can be realized.

According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, a plurality of metal wiring patterns are formed adjacent to and parallel to each other, and have a size larger than a minimum size defined by a design rule.

According to the layout configuration of the semiconductor device according to the sixth aspect, in addition to the same effects as those of the fifth aspect, the capacitance between adjacent wirings and the coupling noise are reduced, and the operation of the logic circuit block is more stable. Can be realized.

According to a seventh aspect of the present invention, in the semiconductor device according to the fifth aspect, the plurality of metal wiring patterns form a plurality of types having different wiring widths and wiring intervals.

According to the layout structure of the semiconductor device according to the seventh aspect, the same effect as that of the fifth aspect can be obtained.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of the first embodiment. As shown in FIG. 1, reference numeral 1 denotes a semiconductor device having a DRAM block 2, a logic circuit block 3, and a pad group 4, which are memory units. The DRAM block 2 includes a memory cell block 5 including a sense amplifier group and a memory cell group, a row decoder section 6, a column decoder section 7, a memory control circuit section 8 including a substrate potential generation circuit and a reference potential generation circuit, and a read amplifier section 9. It is composed of
The logic circuit block 3 is assumed to be constituted by a CMOS circuit. A region 10 indicated by a dotted line is a region where an aluminum layer is formed, and an aluminum layer is formed on the DRAM block 2 so as to cover at least the memory cell group. The aluminum layer formed in region 10 is fixed to a ground node or a power supply node. 11 and 1
Reference numeral 2 denotes an aluminum wiring connecting the memory block 2, the logic block 3, and the pad group 4 to each other. Of these, 11 is an aluminum signal wiring formed of the same wiring layer as the aluminum layer covering at least the memory cell group, and 12 is a signal wiring 1
This is an aluminum signal wiring formed in a wiring layer above the first wiring layer.

The connection between the DRAM block 2, the logic block 3, and the pad group 4 is actually connected in accordance with the specifications, and only a part of the connection is shown in the drawings.

FIG. 2 shows the structure of the DRAM block.
This will be described with reference to FIG.

FIG. 2 is a block diagram showing an example of the structure of the DRAM block 2 shown in FIG. 1. The memory cell block 5 includes a sense amplifier group and a memory cell group, a row decoder unit 6, a column decoder unit 7, a substrate potential. Memory control circuit section 8 including a generation circuit and a reference potential generation circuit, read amplifier section 9
It is composed of Further, the memory cell block 5
Are a memory cell array region 13 having a plurality of memory cells arranged in a matrix, a sense amplifier region 14 having a plurality of sense amplifiers, and a word line lining region 15.
It is composed of A region 10 indicated by a dotted line is a region where an aluminum layer is formed, and the aluminum layer is formed so as to cover the memory cell array region 13. Reference numerals 11 and 12 are aluminum wirings for connecting the memory block 2, the logic block 3, and the pad group 4 described with reference to FIG. Of these, 11 is an aluminum signal wiring formed in the same wiring layer as the above-mentioned aluminum layer forming region, and 12 is an aluminum signal wiring formed in a wiring layer above the signal wiring 11.

The sense amplifier amplifies and latches the data of the memory cell selected by the address signal. The word line lining region 15 is arranged adjacent to the memory cell array region 13 and the word line This is an area provided for backing the above.

FIG. 3 shows a part of a cross section of the semiconductor device 1 shown in FIG. 1, and shows a cross-sectional structure of a layer above the semiconductor substrate. The memory cell array region 13 is formed in the portion A, the sense amplifier region 14 and the word line lining region 15 are formed in the portion B, and the logic circuit block 3 is formed in the portion C. The DRAM block 2 has a two-layer wiring structure (first-layer wiring and second-layer wiring) as shown in FIGS.
It has a layer wiring structure (first-layer wiring to third-layer wiring).

16 is a semiconductor substrate, 17 is an element isolation region,
18 is a diffusion layer; 19 (a) is a DRAM word line;
(B) is the gate electrode of the n-channel transistor of the sense amplifier drive circuit in the sense amplifier area, 19
(C) is the gate electrode of the p-channel transistor of the sense amplifier drive circuit in the sense amplifier area. 2
0 is the cell plate electrode of the DRAM memory cell, 21 is the DRA
The storage electrode of the M memory cell is shown, and the cell plate electrode 20 and the storage electrode 21 form a cylindrical stack type memory cell. Further, in FIG.
The bit line 22 (a) of the block and the wiring 22 (b) of the logic circuit block are both formed of the first layer of aluminum. Similarly, the word line 23 (a) of the DRAM block and the sense amplifier control signal 23 (b) are formed. ) And the wiring 23 (c) of the logic circuit block are both formed of the second layer aluminum. Aluminum 24 (a) and 24 (b) covering the entire memory cell array region (corresponding to the region 10 in which the aluminum layer is formed in FIG. 2), wiring 24 (c) for the word line lining region, and wiring for the logic circuit block 24 (d)
Are both formed of a third-layer aluminum. The wiring 25 (a) of the DRAM block and the wiring 25 (b) of the logic circuit block are both formed of the fourth layer aluminum.
26 denotes a package resin.

Here, the wiring 24 in the word line lining area
(C) Aluminum 24 covering the entire memory cell array area
It is formed of the same wiring layer as (a) and (b), and is used for connection between logic circuit blocks and connection between the logic circuit block and the pad region. Also, D
The wiring 25 (a) of the RAM block can be freely formed on the memory block.

Although not shown in FIG.
The word line 19 (a) of the block and the word line 23 (a) formed of the second aluminum are connected in parallel in the word line lining region 15, so that the effective wiring resistance is kept low. Aluminum 24 covering the entire memory cell array area
From (a), a stable ground level is supplied to the diffusion layer, which is the source region of the n-channel transistor of the sense amplifier driving circuit, via the inter-wiring contact.
From (b), it has a function of supplying a stable power supply level to the diffusion layer, which is the source region of the p-channel transistor of the sense amplifier driving circuit, via the inter-wiring contact.

The aluminum patterns 24 (a) and 24 (a)
The potential applied to 4 (b) is not limited to the ground level or the power supply level, and the same effect can be obtained by giving a self-generated constant potential inside the chip.

Further, in the above embodiment, the description has been made using aluminum as the material of the wiring layer. However, the present invention is not limited to this, and other metals such as copper may be used.

Further, the total number of metal wirings is arbitrary. In the first embodiment, the DRAM block has a two-layer wiring structure, and the logic circuit block has a four-layer wiring structure. When the number of wirings of the DRAM circuit block is n (n = 1,
In the case of (2, 3 ...) layers, the logic circuit block is (n
+2) layer is the most effective.

Further, in the first embodiment, a semiconductor device using a DRAM is shown as the structure of the memory cell array section 5. However, even if the SRAM or flash memory has a structure using a memory cell array, the present invention is not limited to this. It goes without saying that the invention is applied. Further, the configuration of the logic circuit block 3 is not limited to the one configured by the CMOS circuit, and may be a Bi-CMOS configuration.

In the first embodiment, the aluminum patterns 24 (a) and 24 (b) cover only the memory cell array region. However, like the memory cells, the sense amplifier region is susceptible to noise. The same effect can be obtained by applying the present invention to a dynamic circuit section.

In the semiconductor device configured as described above, the α-rays incident on the chip surface from the package resin 26 or the outside are exposed to the aluminum pattern 24 (a) or 24.
(B), the frequency of occurrence of soft errors in the DRAM block 2 is reduced.

The wiring 24 in the word line backing region
(C) Aluminum 24 covering the entire memory cell array area
(A) and (b) are formed in the same wiring layer and are used for connection between logic circuit blocks and connection between the logic circuit block and the pad region. Since it can be used effectively and the layout area can be reduced, and the wiring length of the logic circuit block can be reduced,
This has the effect of improving the performance of the logic circuit block, such as high speed and low power consumption.

As described above, the semiconductor device of the first embodiment is a semiconductor device having a memory portion including a memory cell array region, a sense amplifier region, a decoder region, a memory control circuit region and a logic portion on one chip. The memory circuit formed in the section is configured by n-layer wiring,
A logic circuit formed in the logic section is composed of (n + m) -layer (here, n = 1, 2, 3,..., M = 1, 2, 3,...) Wiring, and a (n + 1) -th wiring on the memory circuit A metal pattern covering at least the memory cell array portion with a layer;
At least one metal wiring is formed in the same wiring layer as the metal pattern covering the memory cell array, the metal pattern supplies a constant potential to at least the memory part, and at least one of the metal wirings is a pad part or a logic circuit. It is electrically connected to the unit.

According to this configuration, a stable constant potential can be supplied to a required portion, and the metal pattern attenuates α-rays incident from the package resin or the outside. Reduced. Further, since a memory circuit on which a metal pattern is not formed can be used as a wiring region between a logic circuit and a pad portion, the wiring length and the layout area can be reduced, and the characteristics of the logic circuit portion can be improved and the chip area can be reduced. .

(Embodiment 2) Next, a layout method of a semiconductor device and a DRAM according to a second embodiment of the present invention
The configuration of the macro will be described with reference to FIGS. 4 and 5A and 5B.

FIG. 4 is a block diagram showing a layout configuration according to the second embodiment. In FIG. 4, reference numeral 27 denotes a layout area of the entire chip of the semiconductor device, and reference numeral 28 denotes a DRAM.
Macro shape data, 29 is logic circuit block shape data, 30 is pad shape data. Each macro block has a macro block shape data so that one-chip layout data can be generated using an automatic placement and routing tool. Is frame data input in accordance with the macro library specification for the purpose of recognizing.

Reference numeral 10 denotes the first embodiment.
This is an aluminum pattern (a region where an aluminum layer is formed) covering the memory cell region. Reference numeral 31 denotes an aluminum fuse region, which cuts a specific fuse in the aluminum fuse region 31 by a laser beam or the like to form a group of fuses capable of switching circuit operations. Generally, this fuse group is formed in the uppermost layer of the aluminum wiring used in the chip. 32 is an aluminum pattern 10 covering the memory cell area.
Is the third layer aluminum wiring prohibited area input in a form that covers the area.
Reference numeral 33 denotes an aluminum wiring all-layer wiring prohibition region input so as to cover the fuse region 31.

FIGS. 5A and 5B show the shape data of a macro block to be recognized by the automatic placement and routing tool. FIG. 5A shows the shape data for the third-layer aluminum wiring. FIG. 5B shows the shape data for the fourth-layer aluminum wiring. In FIG. 5A, reference numeral 28 denotes DRAM macro shape data, which is data for recognizing the shape of the DRAM macro at the time of the first and second aluminum wiring layers.
The shape data 28 of the DRAM macro is inputted as layout data of the DRAM macro in a predetermined layer. Unlike the shape data of the logic circuit block, a layer dedicated to the DRAM section is used.

As shown in FIG. 5 (a), the third-layer aluminum wiring prohibited area 3 inputted in the form of covering the aluminum pattern 10 covering the memory cell area only when the third-layer aluminum wiring is performed.
2 and the aluminum wiring all-layer wiring prohibition region 33 input so as to cover the fuse region 31 are used as DRAM macro shape data.

It should be noted that the DRAM macro shape data 28 and the aluminum macro-shape data are stored so that no problem occurs even if the third-layer aluminum wiring prohibited area 32 and the aluminum wiring all-layer wiring prohibited area 33 exist in addition to the DRAM section. Wiring all layer wiring prohibited area 3
DRA that recognizes the logical product of 3 by the automatic placement and routing tool
Shape data for the third layer aluminum wiring of the M macro is used.

As shown in FIG. 5B, only when the fourth layer of aluminum wiring is performed, the aluminum wiring all-layer wiring prohibited area 33 input so as to cover the fuse area 31 is used as the shape data of the DRAM section. . The logical product of the DRAM macro shape data 28 and the aluminum wiring all-layer wiring prohibited area 33 is automatically arranged so that no problem occurs even if the aluminum wiring all-layer wiring prohibited area 33 exists in addition to the DRAM part. It is assumed that the wiring tool recognizes DRAM macro shape data for four-layer aluminum wiring.

In the layout method of the semiconductor device having the above-described configuration, the third and fourth layers of aluminum wiring are limited on the DRAM block formed by the two-layer aluminum wiring structure, and the It can be used as a wiring area and can be easily applied to automatic placement and routing tools, shortening the design period, reducing the chip area,
The performance of the logic circuit block can be easily improved.

In the second embodiment, aluminum is used as the material of the wiring layer. However, the present invention is not limited to this, and another metal such as copper may be used.

Further, the total number of metal wirings is also arbitrary. In the second embodiment, the DRAM block has a two-layer wiring structure and the logic circuit block has a four-layer wiring structure, but is not particularly limited.

(Embodiment 3) Next, a layout method and a DRA of a semiconductor device according to a third embodiment of the present invention.
The configuration of the M macro will be described with reference to FIG.

FIG. 6 is a block diagram showing the configuration of the third embodiment. Note that the same configuration as the layout configuration of the semiconductor device described with reference to FIGS.
The same reference numerals are given and the description is omitted. 34 in FIG.
Is a third aluminum wiring layer group configured as layout data of a DRAM macro. The third aluminum wiring layer group 34 is a floating pattern that is not connected to other potentials by the DRAM macro alone and is used for connection between logic circuit blocks and between pads and logic circuit blocks. In the DRAM macro, the third aluminum layer 34 is an aluminum pattern 10 covering the memory cell region.
And is formed in an operationally stable region such as on a second-layer aluminum wiring fixed to a power supply or a ground node.

Further, by adding a signal name unique to the third aluminum wiring layer group 34 and the DRAM block shape data 28, the present invention can be easily applied to an automatic placement and routing tool, reducing the number of design steps and the chip size. In addition to the effect, D
An adverse effect of the RAM block and the logic circuit block on each other due to noise or the like can be suppressed, and the circuit operations of both the DRAM block and the logic circuit block can be stabilized.

The DRAM block accounts for a large proportion of the whole chip, and the third aluminum wiring layer group 34
In general, wiring is performed in parallel in the RAM block, and there is a high possibility that the RAM block is used as a data bus line between logic circuit blocks. Therefore, the width and the interval of the aluminum wiring of the third aluminum wiring layer group 34 are set according to the design rule 2.
By laying out at least twice the size and laying out at an equal pitch, it is possible to reduce the capacitance between adjacent wirings of the third aluminum wiring layer group 34 and reduce coupling noise, thereby realizing more stable operation of the logic circuit block. Can be.

Further, a plurality of types of metal wiring patterns having different wiring widths and wiring intervals can be formed.

[0057]

According to the semiconductor device of the present invention, for example, the metal pattern supplies a constant potential to at least the memory section, and at least one of the metal wiring patterns is electrically connected to the pad section or the logic circuit section. When done
A stable constant potential can be supplied to a required portion.
Moreover, α-rays incident on the chip surface from the package resin or from the outside can be attenuated by the metal pattern provided on the memory cell, reducing the frequency of soft errors occurring inside the memory cell. A stable operation can be performed, and the same wiring layer as the metal pattern provided on the memory cell can be effectively used on the DRAM block as a wiring area between logic circuit blocks. A wiring pattern having a high degree of freedom can be formed.

According to the semiconductor device of the second aspect, in addition to the same effects as those of the first aspect, since the memory circuit on which the metal pattern is not formed can be used as a wiring area between the logic circuit and the pad portion, the wiring length can be reduced. It is possible to shorten the layout and the layout area, improve the characteristics of the logic circuit section, and reduce the chip area.

According to the layout method of the semiconductor device according to the third aspect, the memory macro can be restricted and used as a wiring area, and the automatic placement and routing tool can be easily applied.
The design period and the chip area can be reduced.

According to the layout method of a semiconductor device according to the fourth aspect, in addition to the same effects as those of the third aspect, for example, DR
Input the wiring prohibited area designation layer to the AM macro, and
By using the data as the shape data of the M macro, it can be easily applied to an automatic placement and routing tool, so that the number of design steps can be significantly reduced.

According to the layout structure of the semiconductor device according to the fifth aspect, for example, an aluminum pattern covering a memory cell region is used in an operationally stable region in a DRAM macro for use as a wiring between logic circuit blocks. By configuring the aluminum pattern composed of the same wiring layer as the data of the DRAM macro, it is possible to suppress the adverse effects of the noise and the like between the DRAM block and the logic circuit block. A stable circuit operation can be realized.

According to the layout structure of the semiconductor device according to the sixth aspect, in addition to the same effects as those of the fifth aspect, the capacitance between adjacent wirings and the coupling noise are reduced, and the operation of the logic circuit block is more stable. Can be realized.

According to the layout configuration of the semiconductor device according to the seventh aspect, the same effect as that of the fifth aspect can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram viewed from a plane showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a plan view showing the configuration of the DRAM block according to the first embodiment of the present invention;

FIG. 3 is a partial cross-sectional view showing a configuration of the first exemplary embodiment of the present invention.

FIG. 4 is a plan view showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5A is an explanatory view showing shape data for a third-layer aluminum wiring of the DRAM block according to the second embodiment;
(B) is an explanatory view showing shape data for the fourth-layer aluminum wiring.

FIG. 6 is an explanatory diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a configuration of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 DRAM block 3 Logic circuit block 4 Pad group 5 Memory cell block 6 Row decoder part 7 Column decoder part 8 Memory control circuit part 9 Read amplifier part 10 Aluminum pattern 11 Third layer aluminum wiring 12 Fourth layer aluminum wiring 13 Memory cell array area 14 Sense amplifier area 15 Word line lining area 16 Semiconductor substrate 17 Element isolation area 18 Diffusion layer 19 (a) DRAM word line 19 (b) Gate electrode of n-channel transistor of sense amplifier drive circuit 19 (c) Sense Gate electrode of p-channel transistor of amplifier drive circuit 20 Cell plate electrode of DRAM memory cell 21 Storage node electrode of DRAM memory cell 22 (a) Bit line of DRAM block 22 (b) First layer of logic circuit block Lumi wiring 23 (a) word line backing lines of DRAM blocks 23 (b) a sense amplifier control signal 23 (c) a second layer aluminum wiring 24 of the logic circuit block (a), 24 (b) Third covering the memory cell array
Layer aluminum wiring 24 (c) Third layer aluminum wiring of word line lining area 24 (d) Third layer aluminum wiring of logic circuit block 25 (a) Fourth layer aluminum wiring of DRAM block 25 (b) Logic circuit block Fourth layer aluminum wiring 26 Package resin 27 Chip layout area 28 DRAM macro shape data 29 Logic circuit block shape data 30 Pad part shape data 31 Aluminum fuse area 32 Third layer aluminum wiring prohibited area 33 Aluminum wiring all layer prohibited area 34 Third layer aluminum wiring layer group

Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme coat II (Reference) H01L 21/8242 F-term (Reference) 5F038 AV06 BH10 BH19 CA03 CD02 CD03 CD05 DF11 EZ20 5F064 AA04 BB02 BB14 BB23 BB35 CC12 CC15 DD20 EE05 EE23 EE26 EE33 EE52 FF27 FF32 FF42 5F083 AD24 AD48 BS00 ER22 GA02 GA05 GA09 GA18 GA28 JA36 JA37 LA11 LA26 ZA01 ZA12 ZA27

Claims (7)

[Claims] 1. A semiconductor device having a memory portion having a memory cell array region and a logic portion on one chip, wherein a memory circuit formed in the memory portion is formed of n-layer wiring and formed in the logic portion. Logic circuit is (n
+ M) layer wiring, and (n +
1) A metal pattern is formed on a layer so as to cover at least the memory cell array region, and a metal wiring pattern connected to the logic portion is formed of the same wiring layer as the metal pattern. Semiconductor device. 2. The semiconductor according to claim 1, wherein a plurality of metal wiring patterns connected to a logic portion are formed on a word line lining region arranged adjacent to a memory cell array region arranged in a matrix. apparatus. 3. A layout method of a semiconductor device for performing an automatic layout using layout data, wherein a shape of the layout data is included only in an (n + 1) th layer of automatic wiring in a memory macro formed by n-layer wiring. A method of laying out a semiconductor device, characterized by applying recognition data that can be used as data and using an area other than an area covered by the shape data as an automatic wiring layout area. 4. Based on memory macro recognition data having a shape including a memory macro and automatic wiring prohibited area recognition data,
4. The layout method according to claim 3, wherein a logical product of the memory macro recognition data and the automatic wiring prohibited area recognition data is obtained, and the logical product is used as the shape data of the memory macro. 5. A layout configuration of a semiconductor device having a memory portion including a memory cell array region and a logic portion, wherein a memory circuit formed in a memory macro of the memory portion is formed of n-layer wiring, and In the (n + 1) th layer, a metal pattern is formed so as to cover at least the memory cell array region, and a plurality of metal wiring patterns connected to the logic unit are formed in the same wiring layer as the metal pattern. A layout configuration of a semiconductor device characterized by the above-mentioned. 6. The layout configuration of a memory macro according to claim 5, wherein a plurality of metal wiring patterns are formed adjacent to and parallel to each other and have a size larger than a minimum size defined by a design rule. 7. The layout configuration of a memory macro according to claim 5, wherein the plurality of metal wiring patterns form a plurality of types having different wiring widths and wiring intervals.