JP4569081B2 - Display device and projection display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix display device including a pixel portion in which pixel circuits for writing pixel data through switching elements, for example, are arranged in a matrix.
[0002]
[Prior art]
A display device, for example, an active matrix liquid crystal display device in which liquid crystal cells are arranged in a matrix in a display region as a pixel display element (electro-optical element) is characterized by being thin and low power consumption. It is applied to a wide range of electronic devices such as PDAs (Personal Digital Assistants), mobile phones, digital cameras, video cameras, display devices for personal computers, and display panels of projection display devices (projectors).
[0003]
In this active matrix display device, pixel circuits for writing pixel data through a switching element such as a thin film transistor (TFT) as an active element are arranged in a matrix in a display area.
[0004]
By the way, in an active matrix display device such as a liquid crystal display device that uses an active element such as a transistor for controlling each pixel, for example, when a voltage holding active element is used, It is generally known that the retention characteristic depends on the added retention capacity.
In particular, it is known that in a projector using a liquid crystal display device in which strong light is incident, the retention characteristic when the pixel transistor is turned off is deteriorated by the energy of light and a leak current is generated.
[0005]
For this reason, in the liquid crystal display device, the DC (direct current level) of the voltage (hereinafter, common voltage) VCOM applied to the common electrode for driving the liquid crystal is determined in consideration of the deterioration of the holding characteristics due to light, and the DC voltage is applied to the liquid crystal. The occurrence of flicker is prevented and the occurrence of flicker is suppressed as much as possible (see, for example, Patent Document 1).
In addition, this leakage characteristic varies depending on the DC level of the drive voltage, and a method for correcting this has been proposed (see, for example, Patent Document 2).
[0006]
[Patent Document 1]
JP 2002-189460 A
[Patent Document 2]
JP 2001-201732 A
[0007]
[Problems to be solved by the invention]
However, since the above-described leakage current also depends on the amount of light incident on the display element, even if the DC level of the common voltage COM applied to the common electrode is adjusted to the state where flicker is suppressed at the beginning of shipment. As the amount of light from the backlight or lamp decreases due to aging, this leakage current itself also decreases, deviating from the optimum VCOM level, and as a result, a DC voltage is applied to the liquid crystal, thereby degrading the liquid crystal itself. It can also be a cause.
In Patent Document 1 and Patent Document 2 described above, this is not considered at all.
Naturally, it is conceivable that a deviation due to a difference from the state at the time of shipment also occurs in the change in characteristics due to the secular change and temperature change of the leak current itself.
[0008]
An object of the present invention is to provide a display device and a projection display device that can suppress the occurrence of flicker due to aging and temperature change, and can prevent image quality deterioration due to aging and temperature change.
[0009]
[Means for Solving the Problems]
  In order to achieve the above object, a first aspect of the present invention includes a display element whose display state is changed by a voltage applied between a first electrode and a second electrode, and a switching transistor, and the switching transistor When is in a conductive state,A fixed voltage is applied to the second electrode of the display element;Display signal for video signalFirst electrode ofBased on the monitor result of the pixel circuit, the leakage current monitor unit that monitors the leakage current of the switching transistor, and the leakage current monitor unit,A gradation offset that offsets the center voltage of the video signal so that the flicker is minimized for each gradation of the video signal supplied to the pixel circuit.A correction circuit,The gradation offset correction circuit, based on a monitoring result of the leakage current monitoring unit corresponding to the gradation of the video signal, a leak data memory that stores in advance a leak amount value for each gradation of the video signal; An offset data memory in which offset data of the center voltage of the video signal corresponding to the leak amount data stored in the leak data memory is stored in advance, and the video signal when the video signal is input to the pixel circuit The leak amount at that time is read from the leak data memory from the gradation of the video signal, the offset data corresponding to the read leak amount is read, the center voltage of the video signal is moved based on the read offset data, and the center voltage A video signal with an offset added to the pixel circuit.
[0010]
  According to a second aspect of the present invention, there is provided a display element whose display state is changed by a voltage applied between the first electrode and the second electrode, and a switching transistor, and the switching transistor is in a conductive state. ,A fixed voltage is applied to the second electrode of the display element;Display signal for video signalofAn effective pixel unit in which a plurality of pixel circuits are arranged in a matrix and written to the first electrode; a leak current monitor unit that is arranged in the vicinity of the effective pixel unit and monitors the leakage current of the switching transistor; Based on the monitoring result of the leakage current monitoring unit,A gradation offset that offsets the center voltage of the video signal so that the flicker is minimized for each gradation of the video signal supplied to the pixel circuit.A correction circuit,The gradation offset correction circuit, based on a monitoring result of the leakage current monitoring unit corresponding to the gradation of the video signal, a leak data memory that stores in advance a leak amount value for each gradation of the video signal; An offset data memory in which offset data of the center voltage of the video signal corresponding to the leak amount data stored in the leak data memory is stored in advance, and the video signal when the video signal is input to the pixel circuit The leak amount at that time is read from the leak data memory from the gradation of the video signal, the offset data corresponding to the read leak amount is read, the center voltage of the video signal is moved based on the read offset data, and the center voltage A video signal with an offset added to the pixel circuit.
[0011]
  Preferably,The gradation offset correction circuit performs an interpolation process from the leakage amount data of the measured gradation before and after the gradation that is different from the gradation that is measured and monitored by the leakage current monitoring unit. Ask for quantity.
[0012]
  Preferably,The gradation offset correction circuit does not perform the interpolation process when the gradations measured and monitored by the leakage current monitoring unit are all gradations..
[0013]
  Preferably,The leakage current monitoring unit includes a monitoring transistor having the same characteristics as the switching transistor of the pixel circuit, writes a video signal of a specific gradation during a blanking period in the vertical direction, and then holds it for one field period. The leak amount in the state where the gray level is maintained is detected, and the leak amount data is stored in the leak data memory..
[0014]
  According to a third aspect of the present invention, there is provided a projection-type display device that irradiates a predetermined area of a display panel with light and projects an image formed on the display panel onto a light projection surface, the display panel including at least a first display panel. A display element whose display state is changed by a voltage applied between the first electrode and the second electrode, and a switching transistor, and when the switching transistor is in a conductive state,A fixed voltage is applied to the second electrode of the display element;Display signal for video signalofAn effective pixel unit in which a plurality of pixel circuits are arranged in a matrix and written to the first electrode; a leak current monitor unit that is arranged in the vicinity of the effective pixel unit and monitors the leakage current of the switching transistor; In addition, based on the monitoring result of the leakage current monitoring unit,A gradation offset that offsets the center voltage of the video signal so that the flicker is minimized for each gradation of the video signal supplied to the pixel circuit.Having a correction circuit,The gradation offset correction circuit, based on a monitoring result of the leakage current monitoring unit corresponding to the gradation of the video signal, a leak data memory that stores in advance a leak amount value for each gradation of the video signal; An offset data memory in which offset data of the center voltage of the video signal corresponding to the leak amount data stored in the leak data memory is stored in advance, and the video signal when the video signal is input to the pixel circuit The leak amount at that time is read from the leak data memory from the gradation of the video signal, the offset data corresponding to the read leak amount is read, the center voltage of the video signal is moved based on the read offset data, and the center voltage A video signal with an offset added to the pixel circuit.
[0015]
According to the present invention, the leakage current monitoring unit monitors the leakage current of the non-conducting switching transistor by, for example, irradiating light, and supplies the monitoring result to the correction circuit.
In the correction circuit, based on the monitoring result of the leakage current monitoring unit, the voltage applied to the display element so as to remove the voltage fluctuation component held in the display element due to current leakage, for example, the video signal applied to the second electrode The voltage whose polarity is alternately changed every time writing is performed or the video signal voltage applied to the first electrode is corrected.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In the present embodiment, a projection type video display apparatus mainly using a three-plate type liquid crystal panel will be described as an example.
[0017]
First embodiment
FIG. 1 is a block diagram showing a first embodiment of a three-plate liquid crystal projection type video display device.
[0018]
The display device 100 includes liquid crystal panel modules 101R, 101G, and 101B with built-in shift registers, a timing generator (TG) 102, liquid crystal drivers 103R, 103G, and 103B, a video signal processing circuit 104, and leak current monitoring units 105R, 105G, 105B and a VCOM voltage generation circuit 106 as a correction circuit.
[0019]
The liquid crystal panel module 101R receives the video signal that has been AC-inverted for driving the liquid crystal panel by the liquid crystal driver 103R, and controls the horizontal and vertical write transfer by the timing pulse TP generated by the timing generator 102, and the video signal is predetermined. Write to the pixel circuit.
The liquid crystal panel module 101G receives the video signal that has been AC-inverted for driving the liquid crystal panel by the liquid crystal driver 103G, and controls the horizontal and vertical writing transfer by the timing pulse TP generated by the timing generator 102, and the video signal is predetermined. Write to the pixel circuit.
The liquid crystal panel module 101B receives a video signal that has been AC-inverted for driving the liquid crystal panel by the liquid crystal driver 103B, and controls the horizontal and vertical writing transfer by the timing pulse TP generated by the timing generator 102 to output the video signal in a predetermined manner. Write to the pixel circuit.
[0020]
As shown in FIG. 2, the liquid crystal panel module 101 (R, G, B) includes an effective pixel portion 1011, a vertical drive circuit (VDRV) 1012, and a horizontal drive circuit (HDRV) 1013.
[0021]
In the effective pixel portion 1011, a plurality of pixel circuits PXLC are arranged in an m × n matrix.
As shown in FIG. 2, each pixel circuit PXLC includes a TFT (thin film transistor) 101 (hereinafter referred to as a pixel transistor TFT101) as a switching element, and a pixel electrode connected to a drain electrode (or source electrode) of the pixel transistor TFT101. The liquid crystal cell LC101 is connected to the (first electrode), and the storage capacitor Cs101 is connected to one of the drain electrodes of the TFT 101.
For each of these pixel circuits PXLC, scanning lines 1014-1 to 1014-m are wired along the pixel arrangement direction for each row, and signal lines 1015-1 to 1015-n are arranged for each column. It is wired along the direction.
The gate electrode of the pixel transistor TFT101 of each pixel circuit PXLC is connected to the same scanning line 1014-1 to 1014 -m in each row unit. In addition, the source electrode (or drain electrode) of each pixel circuit PXLC is connected to the same signal line 1015-1 to 1015-n for each column.
Further, in a general liquid crystal display device, the storage capacitor line Cs is independently wired, and the storage capacitor Cs101 is formed between the storage capacitor line and the connection electrode. Cs is a common electrode (second electrode). A common voltage VCOM to be applied to the same voltage and an in-phase pulse are input and used as a storage capacitor.
The other electrode of the storage capacitor Cs101 of each pixel circuit PXLC is connected to a common voltage VCOM supply line 1016 whose polarity is inverted during one horizontal scanning period (1H).
[0022]
Each scanning line 1014-1 to 1014-m is driven by a vertical driving circuit 1012, and each signal line 1015-1 to 1015-n is driven by a horizontal driving circuit 1013.
[0023]
Based on the timing pulse TP supplied from the timing generator 102, for example, the vertical start pulse VST for instructing the start of vertical scanning, the vertical clock VCK (or the vertical clocks VCK and VCKX having opposite phases to each other), A process of sequentially selecting each pixel circuit PXLC connected to the scanning lines 1014-1 to 1014-m in units of rows by scanning in the vertical direction (row direction) every field period is performed.
That is, the vertical drive circuit 1012 applies the scan pulse SP1 to the scan line 1014-1 to select the pixels in each column of the first row, and applies the scan pulse SP2 to the scan line 1014-2. A pixel in each column in the second row is selected. Similarly, scanning pulses SP3,..., SP10m are sequentially applied to the scanning lines 1014-3,.
[0024]
The horizontal driving circuit 103 includes a timing pulse TP supplied from the timing generator 102, for example, a horizontal start pulse HST for instructing the start of horizontal scanning, a horizontal clock HCK serving as a reference for horizontal scanning (or horizontal clocks HCK and HCKX having opposite phases to each other). ), The video signal VR input by the liquid crystal driver 103R is sampled sequentially every 1H (H is a horizontal scanning period), and line-by-row by the vertical drive circuit 1012 via the signal lines 1015-1 to 1015 -n. Write processing is performed on each pixel circuit to be selected.
[0025]
As described above, the liquid crystal panel modules 101R, 101G, and 101B according to the present embodiment have a plurality of pixel circuits, and use MOS transistors (TFTs) as switching elements for voltage control.
In general, when driving the liquid crystal, it is necessary to perform alternating current, so in each pixel circuit PXLC, the polarity of the voltage applied to point a (first electrode side) and point b (second electrode side) in FIG. 2 is written. Each time, the polarity is changed alternately to drive.
Then, a DC voltage is input to the counter electrode to which the common voltage VCOM shown in FIG. 2 is applied, and a higher voltage side than the DC voltage is set to + and a lower voltage side is set to −.
Here, one of the causes of flicker is that the light transmittance varies within one field because the voltage written to the pixel varies within one field due to a leakage current when the transistor is off.
Therefore, in order to make the flicker inconspicuous, the drive is performed to switch the polarity applied to the liquid crystal for each line, which is usually one line inversion.
[0026]
As shown in FIGS. 3 (A) and 3 (B), this driving method is shown in FIGS. 3 (A) and 3 (B). After the first line at the uppermost stage in the first field is applied with a positive polarity, the second line is-, and thereafter. In the second field, on the contrary, the first line on the uppermost stage is applied with the polarity of-, and then the second line is alternately applied with + and then with-and +.
As described above, the voltage written in the pixel may fluctuate due to the leak current as a factor causing flicker. This leak current increases when the pixel transistor is irradiated with light, and the voltage fluctuates. It is known that the amount changes.
In the first embodiment, the leakage current monitoring units 105R, 105G, and 105B that monitor and detect the leakage current are provided in the liquid crystal panel modules 101R, 101G, and 101B. As an example, the detected current fluctuation amount And the optimum value of the common voltage VCOM are taken to generate the optimum common voltage VCOM. A specific configuration will be described later in detail.
[0027]
The timing generator 102 is a driving timing pulse for the liquid crystal panel modules 101R, 101G, and 101B based on the horizontal synchronization signal VSYNC and the vertical synchronization signal VSYNC of the video signal, and is a timing for controlling horizontal and vertical write transfer. A pulse TP is generated and supplied to the liquid crystal panel modules 101R, 101G, and 101B.
The timing generator 102, for example, as the timing pulse TP, for example, a horizontal start pulse HST for instructing the start of horizontal scanning, a horizontal clock HCK serving as a reference for horizontal scanning (or horizontal clocks HCK and HCKX having opposite phases to each other), and the start of vertical scanning. And a vertical clock VCK (or vertical clocks VCK and VCKX having opposite phases to each other) as a reference for vertical scanning.
The timing generator 102 generates a clock CLK for the liquid crystal drivers 103R, 103G, and 103B and supplies it to the liquid crystal drivers 103R, 103G, and 103B.
[0028]
The liquid crystal driver 103R receives the video signal R, which has been subjected to predetermined processing by the video signal processing circuit 104, and the clock CLK from the timing generator 102, and exchanges the video signal R with predetermined timing in order to drive the liquid crystal panel module 101R. Inverted and supplied to the liquid crystal panel module 101R as a video signal VR.
[0029]
The liquid crystal driver 103G receives the video signal G that has been subjected to the predetermined processing by the video signal processing circuit 104 and the clock CLK from the timing generator 102, and the video signal G is exchanged at a predetermined timing to drive the liquid crystal panel module 101G. Inverted and supplied to the liquid crystal panel module 101G as a video signal VG.
[0030]
The liquid crystal driver 103B receives the video signal B, which has been subjected to predetermined processing by the video signal processing circuit 104, and the clock CLK from the timing generator 102, and exchanges the video signal B with predetermined timing in order to drive the liquid crystal panel module 101B. Inverted and supplied to the liquid crystal panel module 101B as the video signal VB.
[0031]
The video signal processing circuit 104 receives the video signals R, G, B, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC, performs predetermined processing such as adjustment of the sample hold position, and sends the video signal R to the video driver 103R. The video signal G is supplied to the video driver 103G, and the video signal G is supplied to the video driver 103B.
[0032]
The leak current monitor unit 105R includes, for example, a transistor 1051 having the same characteristics as the pixel transistor TFT101 that constitutes each pixel circuit PXLC, and is disposed in the vicinity of the effective pixel unit 1011 of the liquid crystal panel module 101R. The leakage current of the transistor TFT101 is monitored, and the detection result is output to the VCOM voltage generation circuit 106 as a signal S105R.
[0033]
The leak current monitor unit 105G includes, for example, a transistor 1051 having the same characteristics as the pixel transistor TFT101 that constitutes each pixel circuit PXLC, and is disposed in the vicinity of the effective pixel unit 1011 of the liquid crystal panel module 101G. The leakage current of the transistor TFT101 is monitored, and the detection result is output to the VCOM voltage generation circuit 106 as a signal S105G.
[0034]
The leak current monitor unit 105B includes, for example, a transistor 1051 having the same characteristics as the pixel transistor TFT101 that constitutes each pixel circuit PXLC, and is disposed in the vicinity of the effective pixel unit 1011 of the liquid crystal panel module 101B. The leakage current of the transistor TFT101 is monitored, and the detection result is output to the VCOM voltage generation circuit 106 as a signal S105B.
[0035]
As the leakage amount detection transistor 1051, the same transistor used in the normal pixel circuit as described above is arranged outside the effective pixel region of the video, but the location is particularly specified. However, the vicinity of effective pixels irradiated with light that causes leakage is desirable. It is desirable that the change due to the temperature characteristic is in the vicinity of the temperature that is relatively close to the effective pixel.
As the leak amount detection transistor 1051, for example, as shown in FIG. 4, a transistor whose gate is biased at the ground potential GND and is always off is used.
[0036]
The VCOM voltage generation circuit 106 receives the leakage current detection signals S105R, 105G, and 105B from the leakage current monitoring units 105R, 105G, and 105B and correlates the amount of fluctuation of the leakage current with the optimum value of the common voltage VCOM, respectively. A common voltage VCOM is selected and supplied to the corresponding liquid crystal panel modules 101R, 101G, and 101B.
[0037]
Here, the optimum common voltage VCOM will be described.
Normally, the VCOM adjustment is performed so that the area of the hatched portion shown in FIG. 5 is equal so that the effective voltage applied to the pixel does not include a DC component.
However, as described above, when the leak characteristics of the pixel transistors differ due to aging and temperature changes, the effective voltage applied to the pixel is as shown by the broken line in FIG. 5 and deviates from the optimum VCOM.
In the present embodiment, by monitoring the leakage current itself, the deviation from the optimum VCOM is corrected, and the occurrence of flicker due to secular change or temperature change is suppressed.
[0038]
For example, as shown in FIG. 4, the VCOM voltage generation circuit 106 detects leakage current, digitizes the leakage current data 1061 (R, G, B), and data on the optimum VCOM value corresponding to each leakage current value. Has a memory block 1062 (R, G, B) and a VCOM voltage generation block 1063 (R, G, B).
[0039]
Next, the operation according to the above configuration will be described.
[0040]
The video signals R, G, and B, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC are input to the video signal processing circuit 104, where predetermined processing is performed on the input video signals R, G, and B. The video signal R is supplied to the video driver 103R, the video signal G is supplied to the video driver 103G, and the video signal G is supplied to the video driver 103B.
In addition, the timing generator 102 generates driving timing pulses TP for the liquid crystal panel modules 101R, 101G, and 101B based on the horizontal synchronizing signal VSYNC and the vertical synchronizing signal VSYNC of the video signal, and supplies them to the liquid crystal panel modules 101R, 101G, and 101B. Supplied. In the timing generator 102, a clock CLK for the liquid crystal drivers 103R, 103G, and 103B is generated and supplied to the liquid crystal drivers 103R, 103G, and 103B.
[0041]
In the liquid crystal driver 103R, the video signal R that has been subjected to predetermined processing by the video signal processing circuit 104 and the clock CLK from the timing generator 102 are received and the video signal R drives the liquid crystal panel module 101R at a predetermined timing. The AC signal is inverted and supplied to the liquid crystal panel module 101R as a video signal VR.
Similarly, in the liquid crystal driver 103G, the video signal G that has been subjected to predetermined processing by the video signal processing circuit 104 and the clock from the timing generator 102 are received, and the video signal G has a predetermined value for driving the liquid crystal panel module 101G. The AC signal is inverted at the timing and supplied to the liquid crystal panel module 101G as a video signal VG.
In the liquid crystal driver 103B, the video signal B that has been subjected to predetermined processing by the video signal processing circuit 104 and the clock from the timing generator 102 are received, and the video signal B is AC at a predetermined timing in order to drive the liquid crystal panel module 101B. Inverted and supplied to the liquid crystal panel module 101B as the video signal VB.
[0042]
In each of the liquid crystal display panels 101R, 101G, and 101B, the liquid crystal drivers 103R, 103G, and 103B are used for driving the liquid crystal panel while controlling horizontal and vertical write transfer by the timing pulse TP generated by the timing generator 102, respectively. Video signals VR, VG, and VB that have been AC-inverted are written into a predetermined pixel circuit.
[0043]
As described above, in a state where signals are written in the liquid crystal panel modules 101R, 101G, and 101B, a leak occurs in the actual pixel transistor TFT101 due to light irradiation and temperature characteristics, and a leak current Il equivalent to or proportional to the leak current Il The current also flows through the leakage amount detection transistors 1051 of the leakage current monitoring units 105R, 105G, and 105B.
This leakage current Il is input to the VCOM voltage generation circuit 106 as detection signals S105R, S105G, and S105B.
In the VCOM voltage generation circuit 106, the current detection block 1061 detects a leak current based on the detection signals S105R, S105G, and S105B, and converts it into digital data. This digital data is input to the memory block 1062 storing the data of the common voltage VCOM, and the optimum VCOM data corresponding to the leak amount digital data is read to the VCOM voltage generation block 1063.
Based on this VCOM data, the common voltage VCOM is actually generated by the VCOM generation block 1063 and supplied to the corresponding liquid crystal panel modules 101R, 101G, and 101B.
Here, when the amount of incident light or temperature changes, the amount of leakage current changes, and the digital data indicating the amount of leakage changes accordingly. Then, the VCOM data corresponding to the digital data after the change is read, and the optimum common voltage VCOM voltage is generated at that time.
[0044]
As described above, according to the present embodiment, the transistor 1051 having the same characteristics as that of the pixel transistor TFT 101 constituting the pixel circuit PXLC is formed, and the vicinity of the effective pixel portion 1011 of the liquid crystal panel module 101 (R, G, B). A leakage current monitoring unit 105 (R, G, B) that monitors the leakage current of the pixel transistor TFT101 due to light irradiation by the transistor 1051 and outputs the detection result as a signal S105 (R, G, B); In response to the leakage current detection signal S105 (R, G, B) from the leakage current monitor unit 105 (R, G, B), the respective values of fluctuation of the leakage current and the optimum value of the common voltage VCOM are correlated to obtain the optimum common. A VCO that selects the voltage VCOM and supplies it to the corresponding liquid crystal panel module 101 (R, G, B) Since there is provided a voltage generating circuit 106, it is possible to suppress the generation of flicker due to aging and temperature change, there is an advantage that it is possible to prevent image degradation due to aging and temperature changes.
[0045]
In the first embodiment, the leakage current monitor unit 105 is arranged in all three liquid crystal panel modules and is configured to adjust the common voltage VCOM supplied to each module to an optimum value. Various modes are possible, such as arranging the liquid crystal monitor modules in one or two liquid crystal monitor modules and adjusting the common voltage VCOM to an optimum value.
[0046]
Second embodiment
FIG. 6 is a block diagram showing a second embodiment of the three-plate liquid crystal projection type video display device.
[0047]
The display device 100A according to the second embodiment is different from the display device 100 according to the first embodiment described above in that instead of adjusting the common voltage VCOM to the optimum value based on the leakage current monitoring result, the common voltage VCOM is changed. Is fixed, and instead, an offset is added to the center voltage of the video signal so that the flicker is minimized for each gradation of the video signal.
[0048]
For this reason, the gradations that receive the detection signals S105AR, S105AG, and S105AB of the leak current monitor circuits 105AR, 105AG, and 105AB, respectively, and add offset data to the output video signals VR, VG, and VB of the liquid crystal drivers 103R, 103G, and 103B. Offset correction circuits 107R, 107G, and 107B are provided on the video signal output lines of the liquid crystal drivers 103R, 103G, and 103B.
The reason why the gradation offset correction circuit 107 (R, G, B) is provided, and a specific configuration example and function will be described below.
[0049]
More strictly speaking, the amount of leakage current from the pixel transistor depends on the actually written voltage, and therefore differs depending on the gradation of the video signal.
For this reason, the optimum value of the common voltage VCOM may differ depending on the gradation of the video signal to be written.
Therefore, in the second embodiment, the amount of leak at each gradation is detected, so that any flicker occurs at any gradation and the flicker is minimized.
[0050]
FIG. 7 is a block diagram illustrating a configuration example of the gradation offset correction circuit 107 (R, G, B).
[0051]
As shown in FIG. 7, the gradation offset correction circuit 107 receives the detection signal S105A (R, G, B) of the leak current monitor circuit 105A (R, G, B), detects the leak amount, and detects the leak. Digitization block 1071 for digitizing data, memory block 1072 storing a leak amount value for each gradation, interpolation calculation block 1073 for calculating a leak amount for each gradation of a video signal, memory for storing an offset amount for the leak amount A block 1074 and an operation block 1075 which is an offset addition / subtraction circuit for video signals are included.
[0052]
The leak current monitor circuit 105A (R, G, B) in the second embodiment is not always used with the monitoring transistor turned off as in the first embodiment, but in the vertical direction. A specific gradation is actually written during the blanking period, and thereafter, the same writing as a normal effective pixel is performed for holding for one field period. In this state where the specific gradation is held, the leak amount in that case is detected, and the leak amount data is stored in the memory block 1072 via the digitizing block 1071.
Further, the same operation is performed for other gradations, and stored in another address of the memory. In this way, leak amount data in several gradations is stored in the memory block 1072.
After the leak amount data is stored, when the video signal is actually input, the leak amount at that time is read from the data stored in the memory block 1072 from the gradation of the video signal, or the leak amount is determined. When the gradation is different from the measured one, the interpolation calculation block 1073 obtains it by interpolation calculation from the leak amount data at the measured gradation before and after that.
Of course, when the leak amount is measured for all gradations, no interpolation calculation is required. As a result, the leak amount data of the input video signal can be obtained. However, since the video signal fluctuates dynamically, the common voltage VCOM is given as a DC voltage, and therefore it is impossible to adjust the optimum VCOM for each gradation. .
Therefore, the common voltage VCOM is fixed, and instead, an offset is added to the center voltage of the video signal so that the flicker is minimized for each gradation of the video signal. This offset data is stored in the memory of the memory block 1074. The offset data corresponding to the leak amount data calculated by the interpolation calculation block 1073 is read from the memory block 1074, and the center voltage of the video signal is moved in the calculation block 1075 based on the offset data, so that the gradation of the video signal is obtained. Regardless of this, it is possible to obtain an image always having the minimum flicker.
[0053]
According to the second embodiment, in addition to the effects of the first embodiment described above, the occurrence of flicker due to aging and temperature change can be suppressed with higher accuracy, and image quality deterioration due to aging and temperature change can be suppressed. There are advantages that can be prevented.
[0054]
Note that the first and second embodiments are of course only examples, and the minimum flicker is always possible regardless of the circuit configuration as long as it is possible to read data correlated with effective pixels over time and temperature changes. It is clear that an image can be obtained with
[0055]
In the above embodiment, the case where the present invention is applied to an active matrix liquid crystal display device using a liquid crystal cell as a display element (electro-optical element) of each pixel has been described as an example. The present invention is not limited, and the present invention can be applied to all active matrix display devices such as an active matrix EL display device using an electroluminescence (EL) element as a display element of each pixel.
[0056]
Third embodiment
In the third embodiment, a configuration example of a projection type liquid crystal display device (liquid crystal projector) to which the display device of FIGS. 1 and 6 can be applied will be described.
[0057]
FIG. 8 is a block diagram showing a system configuration of a projection liquid crystal display device to which the active matrix display device according to the present invention can be applied as a display panel (LCD).
[0058]
The projection-type liquid crystal display device 200 according to this example includes a video signal source (VSRC) 201, a system board (SYSBRD) 202, and an LCD panel (PNL) 203.
In this system configuration, the system board 202 performs signal processing such as adjustment of the sample hold position on the video signal output from the video signal source 201. The system board 202 includes a timing generator 102, a liquid crystal driver 103 (R, G, B), a video signal processing circuit 104, a VCOM voltage generation circuit 106, or a gradation offset correction circuit 107 (R, G) shown in FIG. , B).
As the LCD panel 203, liquid crystal panel modules 105 (R, G, B) or 105A (R, G, B) provided corresponding to R (red), G (green), and B (blue), respectively, are used. It is done.
[0059]
FIG. 9 is a schematic configuration diagram showing an example of the configuration of the optical system of the projection type color liquid crystal display device.
In the optical system 300 of the projection type color liquid crystal display device of FIG. 9, white light emitted from the light source 301 is only a specific color component, for example, a B (blue) light component having the shortest wavelength by the first beam splitter 302. Are transmitted, and the light components of the remaining colors are reflected. The B light component transmitted through the first beam splitter 302 has its optical path changed by the mirror 303 and is irradiated to the B LCD panel 305B through the lens 304.
For the light component reflected by the first beam splitter 302, for example, the G (green) light component is reflected by the second beam splitter 306, and the R (red) light component is transmitted. The G light component reflected by the second beam splitter 306 is applied to the G LCD panel 305G through the lens 307.
The R light component transmitted through the second beam splitter 306 is changed in optical path by mirrors 308 and 309 and irradiated to the R LCD panel 305R through the lens 310.
Each of the LCD panels 305R, 305G, and 305B includes a first substrate in which a plurality of pixels are arranged in a matrix, a second substrate that is opposed to the first substrate with a predetermined interval, and these It has a liquid crystal layer held between the substrates and a filter layer corresponding to each color.
The R, G, and B lights that have passed through the LCD panels 305R, 305G, and 305B are combined by a cross prism 311. The combined light emitted from the cross prism 311 is projected onto the screen 313 by the projection prism 312.
[0060]
In the projection type liquid crystal display device having the above configuration, the liquid crystal panel module 105 (R, G, B) or 105A (R, G, B) according to the above-described embodiment is used as the LCD panels 305R, 305G, 305B.
[0061]
In general, it is known that the brightness of the white lamp used in the projection display device decreases while being used. For this reason, when the common voltage VCOM is adjusted when the leakage current of the pixel transistor of the liquid crystal panel is in the initial state, the leakage current from the pixel transistor changes due to a decrease in lamp brightness due to secular change or a temperature condition different from the adjustment time. The direct current component is applied to the liquid crystal that deviates from the optimum VCOM, and flicker should occur. As described above, in the apparatus of the third embodiment, the first or second embodiment is used. Since the projection display device 100 or 100A is applied, the occurrence of flicker due to secular change or temperature change can be suppressed, and deterioration of image quality due to secular change or temperature change can be prevented.
[0062]
There are two types of projection type liquid crystal display devices: a rear type and a front type. Generally, a rear type projection type liquid crystal display device is a projection TV for moving images, and a front type projection type liquid crystal display device is a data projector. Although being used, the dot matrix driving type active matrix liquid crystal display device according to the above-described embodiment can be applied to any type. Further, here, a case where the present invention is applied to a color projection type liquid crystal display device has been described as an example, but the present invention can be similarly applied to a monochrome projection type liquid crystal display device.
[0063]
【The invention's effect】
As described above, according to the present invention, it is possible to suppress the occurrence of flicker due to secular change or temperature change, and to prevent image quality deterioration due to secular change or temperature change.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a three-plate liquid crystal projection type video display device.
FIG. 2 is a circuit diagram illustrating a configuration example of the liquid crystal panel module of FIG.
FIG. 3 is a diagram for explaining an example of 1-line inversion display;
FIG. 4 is a circuit diagram showing a configuration example of a leakage current monitor circuit and a VCOM voltage generation circuit according to the first embodiment.
FIG. 5 is a diagram for explaining an effective voltage applied to a pixel;
FIG. 6 is a block diagram showing a second embodiment of a three-plate liquid crystal projection type image display device.
FIG. 7 is a circuit diagram illustrating a specific configuration example of a gradation offset correction circuit according to a second embodiment.
FIG. 8 is a block diagram showing a system configuration of a projection liquid crystal display device to which the active matrix liquid crystal display device according to the present invention can be applied as a display panel (LCD).
FIG. 9 is a schematic configuration diagram showing an example of the configuration of an optical system of a projection color liquid crystal display device to which the active matrix liquid crystal display device according to the present invention can be applied as a display panel (LCD).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100,100A ... Liquid crystal display device, 101R, 101G, 101B ... Liquid crystal panel module, 102 ... Timing generator (TG), 103R, 103G, 103B ... Liquid crystal driver, 104 ... Video signal processing circuit, 105R, 105G, 105B ... Leakage current Monitor unit 106 ... VCOM voltage generation circuit 107 ... Leak current correction circuit 1011 ... Effective pixel unit 1012 ... Vertical drive circuit (VDRV) 1013 ... Horizontal drive circuit (HDRV) 1014-1 to 104-m ... Scanning Lines, 1015-1 to 1015 -n, signal lines, 1016, VCOM supply lines, PXLC, pixel circuits, TFT 101, pixel transistors (switching elements), LC 101, liquid crystal cells, Cs 101, holding capacitors, 200, projection type liquid crystal display devices 201 ... Video signal source VSRC), 202 ... system board (SYSBRD), 203 ... LCD panel (PNL), 300 ... optical system, 301 ... light source, 302 ... first beam splitter, 303, 308, 309 ... mirror, 304, 307, 310 ... Lens, 305R, 305G, 305B ... LCD panel, 306 ... second beam splitter, 311 ... cross prism, 312 ... projection prism, 313 ... screen.

Claims (9)

A display element whose display state is changed by a voltage applied between the first electrode and the second electrode; and a switching transistor. When the switching transistor is in a conductive state, the second electrode of the display element A pixel circuit to which a fixed voltage is applied and a video signal is applied and written to the first electrode of the display element;
A leakage current monitoring unit for monitoring the leakage current of the switching transistor;
A gradation offset correction circuit that offsets the center voltage of the video signal so as to minimize flicker for each gradation of the video signal supplied to the pixel circuit based on the monitoring result of the leak current monitor unit; Have
The gradation offset correction circuit is
Based on the monitoring result of the leakage current monitoring unit according to the gradation of the video signal, a leak data memory that stores in advance a leak amount value for each gradation of the video signal;
An offset data memory that stores in advance offset data of the center voltage of the video signal corresponding to the leak amount data stored in the leak data memory,
The leak amount at that time is read from the leak data memory from the gradation of the video signal when the video signal is input to the pixel circuit, the offset data corresponding to the read leak amount is read, and the read offset A display device that moves a center voltage of a video signal based on data and supplies a video signal with an offset to the center voltage to the pixel circuit . The gradation offset correction circuit is
The leak amount is obtained by performing interpolation processing from leak amount data at the gradations measured before and after the gradation that is different from the gradation that is measured and monitored by the leak current monitoring unit . Display device. The gradation offset correction circuit is
The display device according to claim 2, wherein the interpolation processing is not performed when the gradations measured and monitored by the leakage current monitoring unit are all gradations . The leakage current monitor unit
Including a monitoring transistor having the same characteristics as the switching transistor of the pixel circuit,
A video signal having a specific gradation is written during the blanking period in the vertical direction, and then held for one field period. The leak amount in a state where the specific gradation is maintained is detected, and the leak amount data is The display device according to claim 1 , wherein the display device is stored in a data memory . A display element whose display state is changed by a voltage applied between the first electrode and the second electrode; and a switching transistor. When the switching transistor is in a conductive state, the second electrode of the display element An effective pixel portion in which a plurality of pixel circuits are arranged in a matrix, and a fixed voltage is applied to the display element, and a video signal is applied to the first electrode of the display element and is written.
A leakage current monitoring unit that is disposed in the vicinity of the effective pixel unit and monitors a leakage current of the switching transistor;
A gradation offset correction circuit that offsets the center voltage of the video signal so as to minimize flicker for each gradation of the video signal supplied to the pixel circuit based on the monitoring result of the leak current monitor unit ; Have
The gradation offset correction circuit is
Based on the monitoring result of the leakage current monitoring unit according to the gradation of the video signal, a leak data memory that stores in advance a leak amount value for each gradation of the video signal;
An offset data memory that stores in advance offset data of the center voltage of the video signal corresponding to the leak amount data stored in the leak data memory,
The leak amount at that time is read from the leak data memory from the gradation of the video signal when the video signal is input to the pixel circuit, the offset data corresponding to the read leak amount is read, and the read offset A display device that moves a center voltage of a video signal based on data and supplies a video signal with an offset to the center voltage to the pixel circuit . The gradation offset correction circuit is
6. The leak amount is obtained by performing interpolation processing from the leak amount data at the gradations measured before and after the gradation that is different from the gradation that is measured and monitored by the leak current monitoring unit . Display device. The gradation offset correction circuit is
If the gradations measured and monitored by the leakage current monitor unit are all gradations, the interpolation processing is not performed.
The display device according to claim 6 . The leakage current monitor unit
Including a monitoring transistor having the same characteristics as the switching transistor of the pixel circuit,
A video signal having a specific gradation is written during the blanking period in the vertical direction, and then held for one field period. The leak amount in a state where the specific gradation is maintained is detected, and the leak amount data is The display device according to claim 5 , wherein the display device is stored in a data memory . A projection display device that irradiates light on a predetermined area of a display panel and projects an image formed on the display panel onto a light projection surface,
The display panel is at least
A display element whose display state is changed by a voltage applied between the first electrode and the second electrode; and a switching transistor. When the switching transistor is in a conductive state, the second electrode of the display element An effective pixel portion in which a plurality of pixel circuits are arranged in a matrix, and a fixed voltage is applied to the display element, and a video signal is applied to the first electrode of the display element and is written.
A leakage current monitoring unit that is disposed in the vicinity of the effective pixel unit and monitors the leakage current of the switching transistor, and
A gradation offset correction circuit that offsets the center voltage of the video signal so that the flicker is minimized for each gradation of the video signal supplied to the pixel circuit based on the monitoring result of the leak current monitor unit. ,
The gradation offset correction circuit is
Based on the monitoring result of the leakage current monitoring unit according to the gradation of the video signal, a leak data memory that stores in advance a leak amount value for each gradation of the video signal;
An offset data memory that stores in advance offset data of the center voltage of the video signal corresponding to the leak amount data stored in the leak data memory,
The leak amount at that time is read from the leak data memory from the gradation of the video signal when the video signal is input to the pixel circuit, the offset data corresponding to the read leak amount is read, and the read offset A projection display device that moves a center voltage of a video signal based on data and supplies a video signal with an offset to the center voltage to the pixel circuit .

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