JP4565693B2 - MOS-FET amplifier circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS-FET amplifier circuit, and more particularly to a MOS-FET amplifier circuit that amplifies an input signal by an amplification MOS-FET whose operating point is set by a drain current flowing between the source and drain when there is no input.
[0002]
[Prior art]
The drain current _IDQ when no signal (for example, a high frequency signal) is input to the MOS-FET is determined by the magnitude of the gate-source voltage _VGS . Characteristic between the voltage _{V GS} and the drain current _{I DQ} between the gate and source of the MOS-FET, _i.e., that indicates the V GS _{-I DQ} characteristic diagrams 4. In this case, the electrical characteristics of the MOS-FET differ depending on the magnitude (operating point) of the drain current _IDQ . Therefore, in the amplifier to use the MOS-FET is best in order to obtain the electrical characteristics of the MOS-FET, the optimum value and the drain current _{I DQ} of MOS-FET (i.e., the gate-source according to FIG voltage V _GS is set to an optimal value).
[0003]
[Problems to be solved by the invention]
However, even if the gate-source voltage V _GS is fixed to an optimal value in order to set the drain current _IDQ to an optimal value in this way, a hot carrier phenomenon occurs in the MOS-FET. As the time elapses, the drain current I _DQ gradually deviates from the optimum value. FIG. 5 shows this phenomenon. In this case, even if the gate-source voltage V _GS is set optimally, the magnitude of the drain current _IDQ decreases as time h elapses.
[0004]
Thus, even if the drain current _IDQ is once set to an optimum value, the magnitude of the drain current _IDQ changes with the passage of time, and the optimum MOS-FET electrical characteristics cannot be obtained. Therefore, when the drain current I _DQ at the time of no signal input is to be set to an optimum value regardless of the passage of time, the gate-source voltage V _GS of the MOS-FET is changed with the passage of time. There is a need. In addition, the above-described temporal change in the electrical characteristics of the MOS-FET differs depending on whether the MOS-FET has a signal input or not, and must be taken into consideration.
[0005]
The present invention has been made to solve the above-mentioned problem, and amplifying by keeping the drain current of an amplifying MOS-FET for amplifying an input signal optimally so as not to be influenced by the passage of time by a simple circuit. An object of the present invention is to provide a MOS-FET amplifier circuit that can keep its function optimal.
[0006]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention provides a MOS-FET amplifier circuit that amplifies an input signal by an amplification MOS-FET whose operating point is set by a drain current flowing between the source and drain when there is no input. A simulation MOS-FET for simulating the operation of the amplification MOS-FET, a constant drain current is passed through the simulation MOS-FET, and the gate-source voltage of the simulation MOS-FET is detected, And a monitoring control circuit that applies a gate-source voltage of the amplification MOS-FET corresponding to the detected gate-source voltage to the gate of the amplification MOS-FET.
[0007]
According to such a configuration, the monitoring control circuit of the MOS-FET amplifier circuit detects the gate-source voltage of the simulating MOS-FET that keeps flowing the optimum drain current, and based on this, detects the amplification MOS-FET. The gate-source voltage can be determined and applied to the gate gate of the amplifying MOS-FET, and the amplifying MOS-FET operates at an optimum drain current.
[0008]
In the embodiment of the present invention, in the MOS-FET amplifier circuit 100 that amplifies an input signal by the amplifying MOS-FET 1 whose operating point is set by the drain current flowing between the source and the drain when there is no input, A simulation MOS-FET 2 for simulating the operation of the MOS-FET 1 and a simulation MOS-FET 2 in which a constant drain current I _DQ2 is passed through the simulation MOS-FET 2 regardless of the passage of time and changes with the passage of time. The gate-source voltage V _GS2 of the FET ₂ is detected, and the gate-source voltage V _GS1 for the amplification MOS-FET 1 corresponding to the detected gate-source voltage V _GS2 is applied to the gate of the amplification MOS-FET 1 And a monitoring control circuit 3.
[0009]
In the present invention, the monitoring control circuit includes an input signal supply circuit for supplying an input signal to the gate of the simulation MOS-FET, and an analog hold for holding a gate-source voltage applied to the amplification MOS-FET. Circuit, an analog hold circuit, and a switch disposed between the gates of the simulation MOS-FETs. In normal times, the switch is turned off and the simulation MOS-FETs are switched from the input signal supply circuit. When the drain current is set, the input signal from the input signal supply circuit to the simulation MOS-FET is stopped, the switch is turned on, and the gate / source of the simulation MOS-FET Hold the voltage across the analog hold circuit.
[0010]
According to such a configuration, the monitoring control circuit normally turns off the switch, gives an input signal from the input signal supply circuit to the gate of the simulation MOS-FET, and simulates the MOS-FET for simulation. Therefore, when the drain current is set, the input signal from the input signal supply circuit to the simulating MOS-FET is stopped and the switch is turned on. Thus, when the voltage between the gate and source of the simulation MOS-FET is held in the analog hold circuit, an optimum drain current flows through the amplification MOS-FET.
[0011]
In the embodiment of the present invention, the supervisory control circuit holds an input signal supply circuit 20 for supplying an input signal to the gate of the simulation MOS-FET 2 and a gate-source voltage applied to the amplification MOS-FET 1. An analog hold circuit 19 and a switch 18 disposed between the analog hold circuit 19 and the gate of the simulation MOS-FET 2. In normal operation, the switch 18 is turned off and the input signal supply circuit 20 is turned off. The input signal SB is given to the gate of the simulation MOS-FET 2 from the input, and when the drain current is set, the input signal SB from the input signal supply circuit 20 to the simulation MOS-FET 2 is stopped and the switch 18 is turned on for simulation. To the analog hold circuit 19 To equity.
[0012]
In the present invention, the amplification MOS-FET and the simulation MOS-FET are set to have the same time-dependent change, and the monitor control circuit is configured to simulate the simulation MOS-FET that changes over time. The same gate-source voltage as that of the FET is applied to the gate of the amplifying MOS-FET.
[0013]
According to such a configuration, the monitoring control circuit of the MOS-FET amplifier circuit can be configured simply.
[0014]
In the present invention, the simulation MOS-FET is formed together in a semiconductor chip on which the amplification MOS-FET is formed.
[0015]
According to such a configuration, it is possible to easily set the environment so that the amplification MOS-FET and the simulation MOS-FET change with time.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a first embodiment of a MOS-FET amplifier circuit according to the present invention, FIG. 2 is a graph showing the operation of the monitoring control circuit of the MOS-FET amplifier circuit of FIG. 1, and FIG. 1 is a circuit diagram showing a second embodiment of the present invention in which the MOS-FET amplifier circuit of FIG.
[0017]
Embodiment 1 FIG.
1 includes a MOS-FET 1 for amplifying an input signal SA (for example, a high-frequency input signal), a MOS-FET 2 for simulating a change in operation of the MOS-FET 1, and a MOS-FET 2 The monitoring control circuit 3 is configured to control the MOS-FET 1 so that the setting of the MOS-FET 1 is optimally regarded as that the MOS-FET 1 also changes with time according to the change. Yes.
[0018]
In the MOS-FET amplifier circuit 100 of FIG. 1, it is assumed that the MOS-FET 1 for amplification and the MOS-FET 2 for simulation are selected under the same conditions, and those that change with time are selected. . Such a selection can be realized structurally, for example, by forming them on the same semiconductor chip even if their current capacities are different. However, in actual use, since the input signal SA is applied to the MOS-FET 1, it is necessary to apply a similar input signal to the MOS-FET 2.
[0019]
The reason for this is that, as shown in FIG. 2, the gate-source voltages V _GS1 and V _GS2 to be applied to the MOS-FET 1 and the MOS-FET 2 to which the input signal is applied as time passes are parallel lines L1. The gate-source voltage V _GS2 to be applied to the MOS-FET 2 to which no input signal is applied is parallel to the gate-source voltage V _GS1 of the MOS-FET 1. For example, in this case, the circuit configuration becomes complicated (this can be easily understood by referring to the description of the embodiment in FIG. 3).
[0020]
For this reason, in the MOS-FET amplifying circuit 100 of FIG. 1, the monitoring control circuit 3 causes the MOS-FET 1 and the MOS-FET 2 to have optimum drain currents I _DQ1 and I _DQ2 flowing in the MOS-FET 1 and the MOS-FET 2, respectively. The initial values of the gate-source voltages V _GS1 and V _GS2 are set in the FET 1 and the MOS-FET 2 respectively, and thereafter the gate-source voltage V along the lines L1 and L2 shown in FIG. _It is preferable to control to change _GS1 and _VGS2 .
[0021]
In this case, the gate-source voltages V _GS1 and V _GS2 are controlled intermittently (for example, every hour or periodically every day) at appropriate intervals. That is, when the gate-source voltages V _GS1 and V _GS2 are not controlled, the operation of the MOS-FET 2 is separated from the operation of the MOS-FET 1, and the gate of the MOS-FET 2 is the same as that for the gate of the MOS-FET 1. Input a high frequency signal. When the gate-source voltage V _GS2 of the MOS-FET ₂ is checked, the input of the high-frequency signal is stopped, the gate-source voltage V _GS2 of the MOS-FET ₂ is detected, and the gate corresponding to the detected gate-source voltage V _GS2 A source voltage V _GS1 (see FIG. 2) is applied to the gate of the MOS-FET 1. Therefore, the optimum drain current I _DQ1 flows through the MOS-FET 1.
[0022]
Embodiment 2. FIG.
Next, a more specific MOS-FET amplifier circuit 200 according to the second embodiment will be described with reference to FIG. In FIG. 3, the portions other than the MOS-FETs 1 and 2 correspond to the monitoring control circuit 3 in FIG. Therefore, the monitoring control circuit in FIG. 3 includes operational amplifiers 4, 5, 6, semi-fixed resistor 7, drain current setting fixed resistor 8 (resistance value Rs), and fixed resistors (hereinafter referred to as R) 9, 10. 11, 11, 12, 13, 14, 15, 16, 17, a switch 18, an analog hold circuit 19, and an input signal supply circuit 20.
[0023]
During normal times when the gate-source voltage V _GS1 is not set, the switch 18 is turned off, and the high-frequency input signal SB is supplied from the input signal supply circuit 20 to the gate of the MOS-FET 2. Therefore, the MOS-FET 2 performs the same operation as the MOS-FET 1. When the gate-source voltage V _GS1 of the MOS-FET 2 is set, the high-frequency input signal SB from the input signal supply circuit 20 to the gate of the MOS-FET 2 is stopped, the switch 18 is turned on, and on the line L2 in FIG. The gate-source voltage V _GS2 is held in the analog hold circuit 19. The voltage held in the analog hold circuit 19 generates the gate-source voltage V _GS1 on the line L1 in FIG. 2 corresponding to the gate-source voltage V _GS2 via the operational amplifiers 5 and 6 and the resistors, It is given to the gate of the MOS-FET 1.
[0024]
The operation of the MOS-FET amplifier circuit 200 shown in FIG. 3 will be further described.
At the initial time, the switch 18 and the high frequency input signal SB are turned off, and the reference voltage Vref is set to a desired value. That is, the reference voltage Vref is set so that the optimum drain current I _DQ2 flows through the MOS-FET ₂ . In this case, the drain current I _DQ2 is expressed by the following equation (1)
I _DQ2 = (Vcc−Vref) / Rs (1)
Determined according to.
[0025]
As is apparent from the right side of equation (1), once Vref is fixed, the other Vcc and Rs (resistance values of the bias current setting fixed resistor) are also fixed, so that the MOS-FET 2 changes with time. Even if it occurs, the drain current _IDQ2 remains at an optimum value. If the drain-source voltage of the MOS-FET ₂ is V _D2 , the following equation (2)
Vcc = V _D2 + _IDQ2 · Rs (2)
Holds.
[0026]
As can be seen from the above formulas (1) and (2), the drain current I _DQ2 is kept constant regardless of the passage of time, and the drain-source voltage V _D2 is also kept constant. It can be seen that the gate-source voltage V _GS2 is automatically changed. Therefore, it is understood that the gate-source voltage V _GS1 may be generated in proportion to the gate-source voltage V _GS2 and applied to the gate of the MOS-FET 1.
[0027]
The high frequency input signal SB is stopped (because the high frequency input signal SB is input to the MOS-FET 2, the drain current I _DQ2 varies and the gate-source voltage V _GS2 also varies), and the switch 18 Is turned on, and the gate-source voltage V _GS2 is held in the analog hold circuit 19, the output voltage of the operational amplifier 5 is expressed by the following equation (3).
_Vout1 =-(R12 / R11) _.VGS2 (3)
It is represented by
[0028]
Therefore, the output of the operational amplifier 6 is given by the following equation (4)
_Vout2 =-(R16 / R15) _.Vout1
+ {R13 (R15 + R16) / R15 (R14 + R13)} · V1 (4)
It is represented by Therefore, when R15 = R16 is set, the equation (4) becomes the following equation (5):
V _out2 = −V _out1
+ {2R13 / (R14 + R13)} · V1 (5)
It is represented by
[0029]
In the above equation (5), almost no current flows through the gate of the MOS-FET.
V _out2 = V _GS1 (6)
it is conceivable that. Therefore, when substituting equation (3) and equation (6) into equation (5),
V _GS1 = (R12 / R11) · V _GS2
+ {2R13 / (R14 + R13)} · V1 (7)
It is represented by
[0030]
As shown by lines L1 and L2 in FIG. 2, when V _GS1 and V _GS2 are parallel, R11 and R12 may be equalized, and V _GS1 is adjusted by adjusting {2R13 / (R14 + R13)} · V1. The initial value may be set. Further, if the MOS-FET 2 (which may include a monitoring circuit) is formed in the same semiconductor chip as the MOS-FET 1, the change over time is the same, so R11 = R12 and V1 = 0 (ground potential). Thus, the following equation (8) can also be set.
V _GS1 = V _GS2 (8)
[0031]
Therefore, as a typical example to which the present invention is applied, the MOS-FET 2 is formed in the semiconductor chip forming the MOS-FET 1 (the size is reduced, and the environment such as temperature is the same for both), The supervisory control circuit is configured as shown in FIG.
When R15 = R16 is set in the monitoring control circuit, one end of R14 is set to the voltage V1 as the ground potential, and the drain current _IDQ2 of the MOS-FET 2 is set to an optimum value by adjusting the semi-fixed resistor 7, the gate of the MOS-FET 1 is set. , An optimal gate-source voltage V _GS1 is given according to equation (8). In this case, the MOS-FET 1 is automatically provided with the optimum gate-source voltage V _GS2 so that the optimum drain current I _DQ2 flows even if time elapses. The optimum gate-source voltage V _GS1 is given through the monitoring control circuit, and even if time passes, the optimum drain current I _DQ1 flows through the MOS-FET 1, and the MOS-FET amplifier circuit is optimum. Will continue to perform their functions.
[0032]
【The invention's effect】
As described in detail above, the MOS-FET amplifier circuit of the present invention uses the supervisory control circuit to detect the gate-source voltage of the simulating MOS-FET that keeps flowing the optimum drain current, and based on it. The gate-source voltage of the amplifying MOS-FET can be determined and applied to the gate gate of the amplifying MOS-FET, and the amplifying MOS-FET can be operated at an optimal drain current that compensates for changes over time. Can do.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a MOS-FET amplifier circuit according to the present invention;
2 is a graph for explaining the operation of the monitoring control circuit of the MOS-FET amplifier circuit of FIG. 1; FIG.
FIG. 3 is a circuit diagram showing a second embodiment of the present invention in which the MOS-FET amplifier circuit of FIG. 1 is further embodied.
FIG. 4 is a graph showing how the drain current I _DQ changes when the gate-source voltage V _GS is changed in the MOS-FET.
FIG. 5 is a graph showing how the drain current I _DQ changes with time when the gate-source voltage V _GS is kept constant in the MOS-FET.
[Explanation of symbols]
1, 2 MOS-FET
3 Monitoring control circuit 4, 5, 6 Operational amplifier 7 Semi-fixed resistor 8 Drain current setting fixed resistor 9, 10, 11, 12, 13, 14, 15, 16, 17 Fixed resistor 18 Switch 19 Analog hold circuit 20 Input signal supply Circuit 100, 200 MOS-FET amplifier circuit

Claims (2)

In a MOS-FET amplifier circuit for amplifying an input signal by an amplification MOS-FET whose operating point is set by a drain current flowing between the source and drain when there is no input,
A simulation MOS-FET for simulating the operation of the amplification MOS-FET, the simulation MOS-FET changing with time under the same conditions as the amplification MOS-FET,
The simulation MOS-FET includes a simulation bias circuit for causing a constant drain current to flow, and detects a gate-source voltage of the simulation MOS-FET, and corresponds to the detected gate-source voltage. A monitoring control circuit that applies a gate-source voltage of the amplification MOS-FET to the gate of the amplification MOS-FET;
The environment is set so that the amplification MOS-FET and the simulation MOS-FET change with time under similar conditions, and the monitoring control circuit inputs an input signal to the gate of the simulation MOS-FET. An input signal supply circuit for supplying a voltage, an analog hold circuit for holding a gate-source voltage applied to the amplification MOS-FET, a switch disposed between the analog hold circuit and the gate of the simulation MOS-FET, In the normal state, the switch is turned off, the input signal is supplied from the input signal supply circuit to the gate of the simulation MOS-FET, and when the drain current is set, the simulation MOS is supplied from the input signal supply circuit. -The input signal to the FET is stopped, the switch is turned on, and the simulation MOS-FET The gate-source voltage is held by the analog-hold circuit, giving the same gate-source voltage and the gate-source voltage of simulated for MOS-FET as a function of time in the gate of the amplifying MOS-FET MOS- FET amplifier circuit. MOS-FET amplifier circuit according to claim 1 which together form the simulated MOS-FET for in a semiconductor chip in which the amplifying MOS-FET is formed.

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