JP4563486B2 - Cyclic snoop to identify eviction candidates for higher level cache - Google Patents

Abstract

A computer system having patrol snoop sequencer that sequences through addresses of cache lines held in a higher level cache, making snoop reads using those addresses to a lower level cache. If a particular cache line held in the higher level cache is not held in the lower level cache, the particular cache line is identified as an eviction candidate in the higher level cache when a new cache line must be loaded into the higher level cache.

Description

  The present invention generally relates to multi-level caches. More specifically, the present invention identifies cache lines in the upper level cache that are eviction candidates in the upper level cache when a new cache line must be loaded into the upper level cache. About that.

  Today's computer systems typically use a multilevel cache. For example, a very fast but relatively small first level cache is typically implemented on the same semiconductor chip as the processor and provides data to the processor in one or two processor cycles. . The first level cache (L1 cache) is typically implemented using static random access memory (SRAM), which is very fast but not as compact as larger and slower memory. The first level cache must also be relatively small to limit the length of control, address, and signal interconnections. In today's computer systems, a second level cache (L2 cache) is often implemented on the same semiconductor chip as the processor. Second level caches are also often built using SRAM memory. The second level cache typically has a larger capacity for both the physical area and the amount of data stored than the first level cache. The second level cache is typically slower to access (read or write) than the first level cache. Today's computer systems also include a third level cache (L3 cache) that holds more data than the second level cache and takes more time to access. In many cases, the third level cache is implemented using dynamic random access memory (DRAM), but SRAM memory may also be used in the design of the third level cache.

  The cache stores data in blocks called cache lines. For example, in various computer systems, a cache line can be 64 bytes, 128 bytes, 256 bytes, etc. A cache line is stored at a cache line location in the cache based on the address of the cache line and the permutation logic coupled to the cache. A cache directory coupled to the cache maintains state information and tag information for each cache line stored in the cache.

  When the processor requests a piece of data at a particular address, the computer system checks whether the data is stored in the first level cache. The particular address is presented in a first level cache directory that determines whether data is stored in the first level cache. If a cache line containing a piece of data exists in the first level cache, the data is fetched from the first level cache for use by the processor, which is a cache hit in the first level cache. Known as. If the cache line containing the piece of data is not held in the first level cache, the first level cache reports a cache miss. A request is then made to the second level cache. If the second level cache holds a particular piece of data, the cache line containing the particular piece of data is fetched from the second level cache and stored in the first level cache. In many implementations, a particular piece of data is made available to the processor at the same time that the cache line containing the particular piece of data is written to the first level cache. If a particular piece of data is not held in the second level cache, a request is made to the third level cache. If a particular piece of data is held in the third level cache, the cache line containing the particular piece of data is fetched from the third level cache, and the second level cache and the first level cache And is available for use by the processor. If a cache miss occurs in the third level cache, further requests are issued to the fourth level cache if a fourth level cache exists, or to main memory.

  Because the lower level cache holds less data than the upper level cache, many cache line locations in the upper level cache are mapped to fewer cache line locations in the lower level cache. In today's computer systems, caches are typically designed with associtivity. Associability means that a particular cache line is mapped to a particular set (row) in the cache, but the replacement logic that supports the cache is for multiple classes (cache line locations) in that set. A specific cache line can be placed in either. A particular class in a particular set is a cache line location. For example, in the case of a 4-level associative second-level cache, replacement logic selects which of the four classes store a particular cache line that maps to a particular set.

  When a cache line is written from the higher level cache to the cache, the cache line must be evicted (either written to the higher level cache or the data in the cache line has not changed In case it is simply overwritten).

  In an associative cache, a replacement algorithm selects which cache lines in the set are replaced. For example, if the cache is 8-way associative, ie has 8 classes per set, a new cache with an address mapped to that set by evicting one of the 8 cache lines • You must make room for the line.

  A number of replacement algorithms have been implemented in various computer systems. A least recently used (LRU) algorithm based on the idea that a more recently used cache line is more likely to be needed again than a less recently used cache line has been widely used. It was. The problem with the LRU algorithm is that a particular cache line may appear unused for a relatively long time for two reasons. The first reason is that the processor no longer needs the data in a particular cache line and loads another cache line to overwrite that particular cache line. The second reason is that the processor frequently uses data in a particular cache line and does not update the upper level cache for a while. For a higher level cache, a particular cache line appears to be an eviction candidate based on the LRU algorithm, but the data in a particular cache line is frequently used as explained for the second reason If so, the eviction will include eviction from the lower level cache, which is inefficient when the upper level cache evicts a particular cache line. Because data in a particular cache line is frequently used, the processor simply needs to request the cache line again and wait until the cache line is taken from a higher level than the higher level cache become.

Because of the LRU problem described above, many computer systems with multi-level caches are effectively eviction candidates where the upper level cache is the preferred eviction candidate for which cache line of the set in the upper level cache. We have implemented a pseudo-random eviction algorithm for the upper level cache that does not know if it exists and allows only one cache line to be randomly selected from the set for eviction. Unfortunately, the pseudo-random eviction algorithm evicts cache lines that are frequently used by the processor, and the evicted cache lines are fetched from a higher level memory than the higher level cache. In many cases, the processor is made to wait until it reaches.
IBM Technical Disclosure Bulletin, IBM
Corp. New York, US, vol.34, no.6 1 November 1991 pages 59-60, XP600228351 ISSN:
0018-8689 discloses MRU update control for multi-level cache. In this document, it is the lower level cache that sends the MRU update request to the upper level cache, not the upper level cache that performs a snoop read to the lower level cache.

  Accordingly, a need exists for a method and apparatus that provides an improved eviction scheme in a high level cache.

  The present invention provides a method and apparatus for enhancing the performance of a computer system by improving cache line replacement.

  In one embodiment, the cache line in the upper level cache is identified as not existing in the lower level cache. Such cache lines are marked as eviction candidates because cache lines in the higher level cache that do not exist in the lower level cache need not be stored in the higher level cache. When a higher level cache has to replace a cache line in a set with a large number of classes, the cache line marked as an eviction candidate is replaced by the cache line not marked as an eviction candidate. Evicted preferentially.

  In one embodiment of the present invention, a cyclic snoop sequencer of a memory controller having a higher level cache is configured to perform a directory entry from the higher level cache directory when the higher level cache directory is not in use. Is read. The cyclic snoop sequencer uses information from the upper level cache directory to snoop read the lower level cache directory when the processor memory bus and lower level cache directory are not in use . If the lower level cache directory reports a cache miss for a particular snoop read, the cyclic snoop sequencer will shout the corresponding cache line when the higher level cache directory is not in use. Update the state information in the higher level cache directory to identify it as a candidate. A snoop read is a lower level cache directory that can determine from a cyclic snoop sequencer associated with the upper level cache whether a particular cache line in the upper level cache exists in the lower level cache. Any command that is sent to, which does not cause eviction in the lower level cache.

  The cyclic snoop sequencer in the memory controller uses the time that the upper level cache directory, the processor memory bus, and the lower level cache directory are not in use, in the upper level cache directory. Cycle through entries looking for cache line eviction candidates. Replacement logic in the memory controller is no longer needed in the higher level cache, before the cache line still needed in the higher level cache in some environments, using eviction candidate information Evict the cache line

  In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings, which form a part hereof and in which are shown by way of illustration specific embodiments in which the invention may be practiced. It should be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

  The present invention provides a method and apparatus for determining eviction candidates in a higher level cache. In a hierarchical cache system (ie, a cache system having a higher level cache and a lower level cache), all cache lines in the lower level cache are also present in the higher level cache. However, certain cache lines in the upper level cache may not exist in the lower level cache. For example, a processor may request first data in a first cache line that must be loaded into a lower level cache. The processor reads the first data. Thereafter, the processor may request second data in a second cache line that must be loaded into the lower level cache. Since the first cache line was not changed, the second cache line is simply overwritten by the first cache line. Prior methods and apparatus do not notify the upper level cache that the first cache line is no longer in the lower level cache.

  Embodiments of the present invention allow the upper level cache to "snoop read" to the lower level cache using the cache directory entry of the upper level cache during times when the cache directory and bus are not in use. Make it possible to do. A snoop read is a lower level cache directory that can determine from a cyclic snoop sequencer associated with the upper level cache whether a particular cache line of the upper level cache exists in the lower level cache. Any command sent to, which does not cause cache line eviction in the lower level cache. If a snoop read causes a cache hit in the lower level cache, the cache line addressed by the cache directory entry from the higher level cache is still present in the lower level cache. If a snoop read causes a cache miss in the lower level cache, the cache line addressed by the cache directory entry from the higher level cache does not exist in the lower level cache and is A cache line addressed by a cache directory entry in the cache is marked as an eviction candidate. Cache lines in sets in higher level caches marked as eviction candidates are selected for eviction prior to cache lines in sets in higher level caches not marked as eviction candidates . Some caches use state information that includes an “invalid” state. A cache line having an invalid state is typically the first cache line to be evicted.

  Referring now to FIG. 1, a computer system 100 is shown in sufficient detail to describe an embodiment of the present invention. It will be appreciated that the computer system further includes a disk memory, a network interface, a user interface, and the like.

  Computer system 100 includes one or more processors 105, shown as processors 105A and 105B. Each processor 105 further includes an L2 cache 110, an associated L2 cache directory, and replacement logic 109. The replacement logic 109 selects which cache line in the L2 cache 110 is to be replaced (evicted) when a replacement with a new cache line is requested. Processor 105A is shown to include L2 cache 110A, L2 cache directory 111A, and replacement logic 109A, and processor 105B includes L2 cache 110B, L2 cache directory 111B, and replacement logic 109B. Shown to include. It will be appreciated that in many computer systems the L2 cache is shared by more than one processor. Processors 105A and 105B are coupled to memory controller 130 by processor memory bus 115A and processor memory bus 115B. It will be appreciated that some processors are coupled to the memory controller using a common bus instead of a separate bus (115A, 115B) as shown. The processor memory bus is collectively referred to as the processor memory bus 115.

  The memory controller 130 includes an L3 cache 132 and an L3 cache directory 136 similar to those used in existing computer systems. The memory controller 130 further includes a cyclic snoop sequencer 134. Replacement logic 133 within memory controller 130 implements a cache line replacement method that uses information stored in L3 cache directory 136 by cyclic snoop sequencer 134. As will be described in more detail below, the cyclic snoop sequencer 134 has resources (L3 cache directory 136, memory processor bus 115, and L2 cache directory 111) idle (ie, not accessed). ) Use time. The cyclic snoop sequencer 134 performs snoop reads using addresses in the L3 cache directory 136 using these idle times of those resources. The cyclic snoop sequencer cycles through the L3 cache directory entry for the cache line (using the cache line address) to determine which cache lines in the L3 cache 132 are not in the L2 caches 110A and 110B. And all such cache lines are recorded as eviction candidates in the L3 cache 132.

  Memory controller 130 is coupled to memory 150 via bus 116. The memory 150 of the computer system 100 is the main memory of the computer system 100. In another embodiment of computer system 100, memory 150 may be a level 4 (L4) cache.

  FIG. 2 shows the processor memory bus 115. It will be appreciated that there are many configurations that are implemented to communicate between the processor 105 and the memory controller 130. The processor memory bus 115 is shown to include a command / status 116, an address 117, and data 118. Command / status 116 is used to transfer commands (eg, read, write) and status (cache miss, cache hit, and in some embodiments, snoop read). The address 117 is used for transferring an address. For example, when the processor 105 requires data at a specific address and the data does not exist in the L2 cache 110, the specific address is transmitted to the memory controller 130 by the address 117. Data is transferred by data 118. For example, the modified cache line is written from the L2 cache 110 to the L3 cache 132. The cache line is sent from the L3 cache 132 to the L2 cache 110 in response to a request from the processor 105. It will be appreciated that in many implementations the information is multiplexed onto a particular processor memory bus 115. For example, if data 118 is 8 bytes wide but the cache line is 64 bytes wide, 8 cycles are required to transfer the cache line. Similarly, in some computer systems, address 117 uses the same physical line as data 118, but is multiplexed.

  FIG. 3A shows the L3 cache 132 in more detail. For illustration purposes, the L3 cache 132 is an 8-way set association, ie each set (line) is from class 0 to 7 (class 0, class 3 and class 7 are indicated by arrows). 8 classes are included. The L3 cache 132 is shown to have N sets (set 0 to N-1) of set 0, set 2 and set N-1 indicated by arrows. A particular cache line is mapped to a particular set of L3 caches 132 using a portion of the cache line address. The replacement logic 133 of the memory controller 130 determines to which class a particular cache line is placed. A particular cache line can be placed in one of eight classes each time a particular cache line is loaded into the cache 132. Several cache line locations for cache lines are shown in FIG. 3A and are referenced by sets and columns. For example, cache line location 132-00 is set 0, class 0 of L3 cache 132. Similarly, cache line location 132-03 is set 0, class 3 of L3 cache 132. Cache lines 132-07 and 132-23 are shown with similar naming conventions. The cache line of the L3 cache 132 must be mapped to the L2 cache 110 shown in FIG. 3B. The L2 cache 110 is smaller than the L3 cache 132 and is typically designed with fewer associations (ie fewer classes) than the L3 cache 132. For illustration purposes, subset 132A of L3 cache 132 (indicated by an arrow and a first shading pattern in FIG. 3A) is mapped to set 1 of L2 cache 110 (in FIG. 3A, an arrow and a second shading pattern). Subset 132B (indicated by) is mapped to set 3 of L2 cache 110.

  It will be appreciated that this mapping is exemplary only, and that there are many ways to map a particular cache line location in the higher level cache to the lower level cache. For example, FIG. 3C shows one example of mapping. An address, such as the 32-bit address used by processor 105, has a portion that is used to identify the cache line bits. If the cache line contains 128 bytes, the part labeled “Bytes in the cache line” in FIG. 3C will have 7 bits. The portion named “L2 index” contains as many bits as necessary to determine which set of L2 cache 110 the cache line will be mapped to. For example, if the L2 cache 110 has 1024 sets, the L2 index in FIG. 3C requires 10 bits. The portion named “L2 tag” is the tag portion of the address that must be stored in the tag field of the L2 cache directory, as described with reference to FIGS. 5A-5C. The L3 cache 132 is larger than the L2 cache 110, i.e. holds more cache lines. Since the cache line held in the L2 cache 110 has the same number of bytes as the cache line held in the L3 cache 132, the “bytes in the cache line” portion of the address is stored in the L3 cache 132. The same part of the address for the cache line. The address part named “L3 index” shown in FIG. 3C has more bits than the address part named “L2 index”. For example, if the L3 cache 132 has 4096 sets, the L3 index shown in FIG. 3C requires 12 bits. The address portion “L3 tag” shown in FIG. 3 must be stored in a tag entry in the L3 cache directory, as described below. Other mapping techniques “hash” the portion of the address. Any mapping is considered.

  In FIG. 3B, the L2 cache 110 is shown as having M sets (0 to M-1), and the L2 cache 110 is 4-way set associative, ie, class 0 to class 3 4 Shown to have two classes. Subsets 132A and 132B are shown as described above. Cache line location 110-00 (L2 cache 110 set 0, class 0) and cache line location 110-23 (L2 cache 110 set 2, class 3) are set / class naming as described above for L3 cache 132. Shown to represent rules.

  4A and 4B show specific cache lines for L3 cache 132 and L2 cache 110. FIG. Cache lines A, B, C, D, E, F, G, and H are stored in set 0 of L3 cache 132, as shown in FIG. 4A. Cache line A is stored in 110-10 of L2 cache 110 (using the above naming convention), cache line C is stored in 110-12 of L2 cache 110, and cache line F is 110 -31. In the example of FIGS. 4A and 4B, the cache lines B, D, E, G, and H do not exist in the L2 cache 110. Cache lines W, X, Q, R, and S are locations in L2 cache 110 that have addresses mapped to set 1 (W and X) or set 3 (Q, R, and S) (Not shown) must also exist in the L3 cache 132. Note that all cache lines present in the L2 cache 110 also exist in the L3 cache 132. However, not all cache lines of L3 cache 132 need to be in L2 cache 110. As described above, if the first cache line has not changed, the L2 cache 110 can simply overwrite the first cache line with the newly fetched cache line. The L2 cache 110 does not notify the L3 cache 132 that the first cache line has been overwritten.

  3A, FIG. 3B, FIG. 4A, FIG. 4B and its description above focus on the physical location of the cache lines of L3 cache 132 and L2 cache 110. FIG. The cache directory 111 (shown as cache directories 111A and 111B in FIG. 1) tracks the address of the cache line stored in the L2 cache 110 and the state of the cache line stored in the L2 cache 110. Used for. The cache directory 136 (FIG. 1) is used to track the address of the cache line stored in the L3 cache 132 and the state of the cache line stored in the L3 cache 132.

  An exemplary L2 cache directory 111 is shown in FIG. 5A. The L2 cache directory 111 includes a cache directory array 112 having four entry columns, and each of the entry columns 70 corresponds to a class of the L2 cache 110 (FIG. 3B). The L2 cache directory array 112 has M rows 113, each of which corresponds to one set in the M sets of L2 cache 110 (FIG. 3B). An L2 cache directory entry 76 (one L2 cache directory entry is indicated by shading, symbol “76”, and an arrow) is stored at each intersection of row 113 and entry column 70. An L2 cache directory entry is stored in the cache directory array 112 for each cache line stored in the L2 cache 110. It will be appreciated that the L3 cache directory 136 is similarly configured.

  Each L2 cache directory entry 76 includes a status field 73 and a tag field 72. The status field 73 holds status information regarding the corresponding cache line. In many computer systems, the status field indicates that the corresponding cache line is (1) modified, (2) exclusive, (3) shared, or (4) invalid ( 4 bits that mean invalid). Such state information is called MESI state information. An exemplary status field 73 is shown in FIG. 5B. However, for an embodiment of the present invention, in FIG. 5C, an exemplary status field 74 having MESI status information but also having an “X” bit is shown. The “X” bit in the status field 74 is used to flag a cache line identified as an eviction candidate, as described below. The tag field 72 holds the tag portion of the cache line address. Many variations of MESI state are used to enhance cache coherency, and it is recognized that the present invention is not limited to any particular implementation of MESI or any other coherency protocol. I want to be.

  The cache directory 111 further includes an address register 90 that holds an address sent by the address 117 to the L2 cache directory 111 to see if the cache line with that address is in the L2 cache directory 111. The address sent to the L2 cache directory 111 by the address 117 may be generated from the processor 105 or the memory controller 130. The first address portion 92 is used to select one of the M rows of the L2 cache directory array 112. The tag portion 91 of the address of the address register 90 is sent to the comparison unit 80 by a signal 93. Tag 72 is read from the selected row of L2 cache directory array 112 by signals 81A, 81B, 81C, and 81D and compared to the tag portion of the address. A cache hit is reported by signal 82 if one of the tags sent by signals 81A, 81B, 81C, and 81D is equal to the tag portion of the address. A cache miss is reported by signal 82 if none of the tags sent by signals 81A, 81B, 81C, and 81D are equal to the tag portion of the address. State information for each directory is typically read from the L2 cache directory array 112 at the same time as the tag 72.

  With the above description regarding the operation of the L3 cache 132, L3 cache directory 136, L2 cache 110, and L2 cache directory 111 in mind, returning to FIG. 1, the operation of the cyclic snoop sequencer 134 will be described.

  A cyclic snoop sequencer 134 is coupled to each of the L3 cache directory 136 and the processor memory bus 115 (processor memory bus 115A and 115B shown in FIG. 1). The cyclic snoop sequencer 134 initializes the directory index and addresses the first line of the L3 cache directory 136. The L3 cache directory 136 is read with its index when the L3 cache directory 136 is not used. When accessed, the L3 cache directory 136 returns eight entries corresponding to the eight classes shown in the L3 cache 132 in FIG. 3A. The cyclic snoop sequencer 134 executes processing for determining which of the cache lines of the L3 cache 132 does not exist in the L2 cache 110 as necessary. The cyclic snoop sequencer 134 generates a cyclic snoop address using a tag stored for each entry in the L3 cache directory along with the index. The cyclic snoop address is sent by the processor memory bus 115 to the L2 cache directory 111 when the processor memory bus 115 is idle. When the L2 cache directory 111 is idle, a snoop read of the L2 cache directory 111 is performed. If the L2 cache directory 111 reports an L2 cache miss by signal 82, the cache line corresponding to the cyclic snoop address does not exist in the L2 cache 111. Signal 82 is coupled to cyclic snoop 134 by command / status 116 of processor memory bus 115. Cyclic snoop sequencer 134 updates the corresponding entry in L3 cache directory 136 by asserting bit "X" in status field 74, thereby identifying the cache line as an eviction candidate. If L2 cache directory 111 reports an L2 cache hit by signal 82, the corresponding cache line still exists in L2 cache 111, and cyclic snoop sequencer 134 identifies the cache line. The corresponding entry in the L3 cache directory 136 is not updated to identify it as an eviction candidate. The cyclic snoop sequencer 134 repeats the snoop read for each indexed row entry in the L3 cache directory 136 and then increments the index value to access the next row in the L3 cache directory 136. . When the last line of the L3 cache directory 136 is complete, the index is reset to access the first line again. In an embodiment of the present invention, the cyclic snoop sequencer accesses the L3 cache directory 136 only when the L3 cache directory is idle and the processor memory memory only when the processor memory bus 115 is idle. There is no performance penalty for identifying eviction candidates because a snoop read is sent over the bus 115 and the L2 cache directory 111 is accessed only when the L2 cache directory 111 is idle. .

  The cache line must not be evicted from the L2 cache 110 by a snoop read. Since many cache lines of the L2 cache 110 are used by the processor, performance degradation may occur if the cache line is evicted by a snoop read. To prevent snooping reads from causing unwanted eviction, the replacement logic 109 (FIG. 1) of the processor 105 interprets the commands on the command / status 116 as snoop reads asserted by the cyclic snoop sequencer 134. The snoop read can be easily identified by recognizing the snoop read and suppressing any attempt to evict the cache line of the lower level cache in response to the snoop read command.

  In one embodiment, the cyclic snoop sequencer 134 should use the state 74 information from the currently considered entry in the L3 cache directory 136 to perform a snoop read for the currently considered entry. Judge whether. If the state 74 indicates that the cache line corresponding to the current entry has changed (eg, using a specific MESI state implementation), the corresponding cache line is present in the L2 cache 110. Therefore, no snoop reading is performed. If state 74 indicates that the cache line corresponding to the current entry is shared, a snoop read is performed because the corresponding cache line may or may not exist in the L2 cache 110. . Various implementations of cache coherency using MESI handle different “exclusive” states. For example, some implementations may define "exclusive" as meaning that only one processor has a cache line but may not have changed that cache line. Yes, if another processor requests a cache line, “exclusive” is changed to “shared”, and like “shared”, such a cache line is It may not exist in the lower level cache, and a snoop read is one that includes a cache entry having an “exclusive” state. In other implementations of MESI, “exclusive” may mean that a cache line is used and should not be an eviction candidate. If state 74 indicates that the cache line corresponding to the current entry is invalid, no snoop read is performed. Typically, the invalid state occurs only at computer system startup. If the cache line is invalid, replacement logic 133 replaces the corresponding cache line, and if the status field indicates that the cache line is invalid, no snoop read is required.

  If a cache line marked as an eviction candidate is accessed by the processor 105 before being evicted, the cache line is marked again so that it is not an eviction candidate (ie, FIG. It will be seen that the bit “X” shown in state 74 at 5C is deasserted).

  FIG. 1 shows that the L3 cache 132 supports two processors 105A, 105B having L2 caches 110A, 110B, respectively. In one embodiment, the memory controller 130 keeps track of which L2 cache 110 a particular cache line was sent to and that L2 cache 110 to which that cache line was sent has that particular cache line. It is only necessary to determine whether it exists. In the second embodiment, the memory controller 130 does not keep track of which L2 cache 110 a particular cache line has been sent to, and in which L2 cache 110 a particular cache line exists. Each of the L2 caches 110 must always be checked.

  It will be appreciated that although L3 and L2 cache systems have been used to illustrate the upper and lower level caches, the present invention is not limited to L3 and L2 level caches. For example, the cyclic snoop sequencer associated with the L2 cache 110 and the L2 cache directory 111 can perform the same function for the level 1 cache of the processor 105 (level 1 cache is not shown).

  Embodiments of the invention can also be expressed as methods. FIG. 6 shows a flowchart of the method 300. Method 300 begins at step 302. In step 304, the index of the upper level cache directory row is initialized to zero. In step 306, it is checked whether the upper level cache directory is being used. If a higher level cache directory is being used, control is simply returned to step 306. If the upper level cache directory is not in use, control passes to step 308. In step 308, the entry in the upper level cache directory is read and a cyclic snoop address is generated using the entry's index and tag information. Typically, all entries in the upper level cache directory row are read in parallel. In that case, the cyclic snoop sequencer stores the entries read in parallel and then processes each entry in the row. For example, FIG. 5A shows an L2 cache directory array 112 having four entries per line. The L3 cache 132 is shown as having eight classes (FIG. 3A), so the L3 cache directory 136 includes an L3 cache directory array with eight entries per line (L3 cache directory). The directory is not shown, but the design of the L3 cache directory 136 is described as being designed similarly to the L2 cache directory 111).

  In step 310, when the lower level cache directory is not in use, the lower level cache directory is snoop read using the cyclic snoop address generated in step 308. In step 312, if the snoop read does not report a cache hit in the lower level cache, the entry is marked to flag the corresponding cache line as an eviction candidate. Step 316 determines whether the entry used for the last snoop read is the last entry in the upper level cache directory. If it is not the last entry, the index value is advanced in step 318 and control passes to step 306. If it is the last entry, the index value is reset to 0 in step 320 and control passes to step 306.

  The method 350 shown in FIG. 7 is similar to the method 300 (FIG. 6), but includes more details about an exemplary cache design using MESI state rules.

  Method 350 begins at step 352. Step 354 initializes an index corresponding to a particular row in the upper level cache directory. Step 356 checks whether the upper level cache directory is being used. If so, step 356 branches and simply returns to step 356 to wait for a time when the upper level cache directory is not in use.

  If step 356 determines that the upper level cache directory is not in use, control passes to step 381. Step 381 reads the upper level cache directory for status information regarding one or more entries of the upper level cache directory array. As before, the cache directory typically reads all directory information for a particular row accessed by the index. Step 381 transfers control to step 382. Step 382 checks which entry read in step 381 has an invalid state. Invalid states are rare and generally only appear at computer system startup. An invalid state for an entry means that the corresponding cache line does not contain what is needed by the processor 105 and may be overwritten and no snoop read need be performed. If the cache entry read in step 381 is invalid, step 382 transfers control to step 366. If the entry read in step 381 is not invalid, step 382 transfers control to step 384. Step 384 checks whether any state is shared. If not, the corresponding cache line is used in the lower level cache, the corresponding higher level cache line is not marked as an eviction candidate, and control passes to step 366. If the entry has a shared state, step 384 transfers control to step 358 which generates an address using the index and tag information from the directory entry read in step 381. Step 360 performs a snoop read of the lower level cache when the processor memory bus 115 is unused and when the lower level cache directory is unused. If the snoop response is a hit, the corresponding cache line is in the lower level cache and is not an eviction candidate. If the snoop response is not a hit (ie, a miss), control passes to step 364 as an eviction candidate by setting status information in the directory entry used to generate the snoop read. Flag the cache line. As mentioned above, the cache line can be flagged as an eviction candidate using the status bit “X” of the entry. Next, step 364 transfers control to step 386 to check whether there are more entries in the current row of the entry having the shared state read in step 381. If so, control passes to step 358, otherwise control passes to step 366.

  Step 366 checks whether all entries in the upper level cache directory have been considered, i.e. the index will handle more than the number of rows in the upper level cache directory array. If all entries are not considered, the value of the index is increased in step 368, and if all entries are considered, the index is reinitialized to 0 in step 370. Steps 368 and 370 return control to step 356 to read the entry using the unused time of the higher level cache directory, find the entry that has the shared state, and to determine the resource (upper level cache directory, memory. When the processor bus and lower level cache directory) are idle, it sends a snoop read request to the lower level cache directory and determines whether a shared cache line exists in the lower level cache. The method of judging by hit or miss responses from the cache directory is continued. If the shared cache line does not exist in the lower level cache, the cache line of the upper level cache is marked as an eviction candidate.

  The method 400 shown in FIG. 8 is a known, eg, but not limited to, LRU replacement algorithm and pseudo-random replacement algorithm, with eviction candidates identified by the snoop readout embodiment of the present invention described above as a method and apparatus. We show how the replacement selection of the replacement algorithm is improved.

  Method 400 begins at step 402. In step 404, the upper level cache receives a request for new cache line data requesting eviction of the cache line of the upper level cache. In step 406, the upper level cache determines the cache directory array row that contains an entry containing the status and tag information for the class in which the new cache line is located. In step 408, the line determined in step 406 is read from the cache directory array.

  In step 410, it is checked whether the requested cache line exists in the higher level cache. If so, in step 412, it is checked whether the requested cache line is marked as an eviction candidate. If the requested cache line is marked as an eviction candidate, control passes to step 414 which unmarks the requested cache line from the eviction candidate. Step 414 transfers control to step 416. If step 412 determines that the requested cache line is not marked as an eviction candidate, control passes to step 416. Step 416 copies the requested cache line to the lower level cache. Control transfers from step 416 to step 426 and the method ends. If step 410 determines that the requested cache line does not exist in the higher level cache, control passes to step 420.

  In step 420, if any entry on the line read in step 408 has an invalid state, control passes to step 421 and the requested cache line corresponds to the invalid state entry from step 420. It is written to the upper level cache class, which evicts (actually overwrites) the invalid cache line. Step 421 then transfers control to step 426 and process 400 ends. If step 420 detects that the entry does not have a state indicating an invalid cache line, control passes to step 422.

  In step 422, the state of the row entry in the upper level cache directory array read in step 408 is checked to see if any entry is marked as an eviction candidate. This step only examines each entry in turn until a first eviction candidate is found. If an eviction candidate is found, control passes to step 423 and the requested cache line is written to a cache line that is found to be an eviction candidate. Step 423 transfers control to step 426 and the process ends. If step 422 does not find an entry marked as an eviction candidate, control passes to step 424. Step 424 performs any of a number of known replacement algorithms, such as an LRU algorithm or a pseudo-random replacement algorithm.

1 is a block diagram of a computer system that includes one or more processors, a memory controller, and memory. Figure 2 shows the processor memory bus shown in Figure 1 in more detail. (A) A block diagram of a higher level cache is shown. (B) A block diagram of the lower level cache is shown. (C) shows exemplary addresses having L2 and L3 tag portions, L2 and L3 index portions, and portions used to determine bytes within a cache line. (A) A high level cache with exemplary cache lines stored in a set. (B) A lower level cache with exemplary cache lines stored in a set. (A) shows an exemplary cache directory. (B) shows an exemplary status field of a cache directory entry. (C) An exemplary status field of a cache directory entry having bits indicating eviction candidates. 3 is a flowchart of a first method for determining eviction candidates in a higher level cache. FIG. 6 is a flowchart of a second method for determining eviction candidates in a higher level cache. It is a flowchart of the method of supplementing a cache replacement algorithm using eviction candidate information.

Claims (5)

A method for cache line replacement in a computer system that includes an upper level cache and a lower level cache, each having a directory, comprising :
To identify cache lines for higher level caches that do not exist in the lower level cache,
Determining a first time that the upper level cache directory is idle;
Reading a cache entry from the upper level cache directory during the first time; and
Using the tag field of the cache entry read from the upper level cache directory to generate the address of the corresponding cache line of the upper level cache;
Determining a second time that the lower level cache directory is idle;
During the second time, and performing a snoop read of the lower level cache directory using the address of the cache line in the higher level cache,
Identifying the cache line as an eviction candidate if the result of the snoop read was not a cache hit ;
Determining the first time, the reading step, the generating step, the second time determining step, and the snoop reading step for subsequent cache entries in the upper level cache directory. And repeating the identifying step ;
A method comprising the steps of: Read the state information of the cache entry from the upper level cache directory and if the state information indicates that the corresponding cache line is invalid or changed, the lower level cache The method of claim 1 , wherein the next cache entry is read from the upper level cache directory without performing a snoop read of the directory . Receiving a request for data from the upper level cache;
Check whether a particular cache line containing the data exists in the higher level cache;
If the specific cache line is present in the upper level cache and the specific cache line is identified as not present in the lower level cache, it is present in the lower level cache. The method according to claim 1 or 2 , further comprising the step of: de-identifying the cache line that was not to be identified . Receiving a request for data from the upper level cache;
Check whether a particular cache line containing the data exists in the higher level cache;
Evicting a cache line that is identified as an invalid cache line or eviction candidate for the higher level cache if the specific cache line is not present in the higher level cache; 4. The method of claim 3, comprising. A high-level cache;
Patrol snoop sequencer,
A computer system comprising a memory controller comprising:
A lower level cache coupled to the memory controller;
Evicting a first cache line identified as not present in the lower level cache in the memory controller instead of a second cache line present in the lower level cache Logic and
Further comprising
The memory controller further comprises an upper level cache directory coupled to the cyclic snoop sequencer and holding an entry for each cache line of the upper level cache;
Each of the entries includes a status field and a tag field for each cache line of the upper level cache;
The entry for each cache line of the upper level cache further includes an identification field that holds information regarding whether a particular cache line of the upper level cache is not present in the lower level cache;
The cyclic snoop sequencer is configured to identify cache lines of the higher level cache that are not present in the lower level cache;
The traveling snoop sequencer is
Reading the cache entry from the upper level cache directory when the upper level cache directory is idle;
Using the tag field of the cache entry to generate the address of the corresponding cache line of the upper level cache;
When the lower level cache directory is idle, perform a snoop read of the lower level cache directory;
If the result of the snoop read is not a cache hit, write information identifying the cache line as an eviction candidate in the identification field;
Repeating the cache entry read, address generation, snoop read, and identification field write for subsequent cache entries in the upper level cache directory;
Configured as
Computer system.

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