JP4558812B2 - Intermittent receiver - Google Patents

Description

  The present invention relates to an intermittent receiving apparatus that estimates a transmission timing of a transmitting-side radio station at a receiving-side radio station, sets a reception standby period, and performs power on / off control during that period.

FIG. 9 shows a configuration example of a conventional wireless terminal.
In the figure, a transmission circuit 41 of a base station 40 and a reception circuit 51 of a wireless terminal 50 that are wirelessly connected operate according to reference clocks 42 and 52, respectively. Here, if the frequency of the reference clock 42 of the base station 40 is fh ′ and the frequency of the reference clock 52 of the wireless terminal 50 is fh (= fh′−Δfh), the receiving circuit 51 uses an AFC (automatic frequency control) circuit. Thus, the frequency error Δfh of the own apparatus with respect to the reference clock 42 of the base station 40 is corrected, and reception processing is performed with frequency synchronization.

  Further, the intermittent reception control circuit 53 of the wireless terminal 50 that performs intermittent reception control with the base station 40 estimates the reception standby period using the reference clock 52 or a standby clock 54 provided separately, during which reception is performed. The power of the circuit 51 is turned off to reduce power consumption. Then, control for starting up the power supply of the receiving circuit 51 is performed slightly before the timing at which the transmission frame arrives again (Patent Document 1).

  In general, there is a frequency error between the reference clock 52 or the standby clock 54 that determines the reception standby period in the wireless terminal 50 and the reference clock 42 that determines the transmission timing in the base station 40. It is necessary to turn on the power supply of the receiving circuit 51 by providing an allowance time assuming minutes. In particular, when a low-speed and low-power standby clock 54 is used instead of the reference clock 52 in order to reduce power consumption during the reception standby period, a sufficient margin time corresponding to a decrease in frequency accuracy is further provided. It is necessary to provide.

On the other hand, a method for shortening the margin time of the wireless terminal 50 by using a high-accuracy oscillation circuit during the reception standby period has also been proposed (Patent Document 2). However, there is a trade-off between an increase in power consumption due to the high-precision oscillator circuit and a reduction in power consumption due to a reduction in margin time.
Japanese Patent No. 3325434 JP-A-5-14222

  In order to reduce the power consumption of the wireless terminal 50 that performs intermittent reception, the method using the standby clock 54 with low speed and low power consumption during the reception standby period has a large frequency error with the base station 40 and corresponds to the transmission signal. Thus, the estimated reception standby period becomes inaccurate. Therefore, it is necessary to start up the power supply of each circuit while the power is turned off by providing a sufficiently long margin time, and the power consumption reduction effect is offset by that amount.

  The present invention provides an intermittent receiver capable of improving the setting accuracy of a reception standby period while using a standby clock, shortening a margin time when restarting a reception operation, and enhancing the power consumption reduction effect by intermittent reception. The purpose is to do.

  The first invention is provided in the other radio station that generates a frame composed of a transmission frame and a reception frame synchronized with a reference clock in one radio station and receives a signal transmitted at the timing of the transmission frame. In an intermittent reception device that sets an intermittent reception interval that is an integer p times the frame interval and turns on and off the power of the reception circuit at a timing according to the intermittent reception interval, a standby clock that is slower than the reference clock, and one of the wireless stations A frame timing detection circuit that receives a transmitted signal and detects a frame timing synchronized with a transmission frame; and a frame timing interval over k frames (k is an integer of 1 or more) is counted with a standby clock, and the number of clocks n A frame timing interval measuring circuit for measuring a frame timing interval of k frames represented by: Enter the frame timing interval k frames represented by the lock number n, and a discontinuous reception control circuit for setting a wait BEARING clock of the clock number ((n / k) * p) as an intermittent reception interval.

  The second invention is provided in the other radio station that generates a frame composed of a transmission frame and a reception frame synchronized with a reference clock in one radio station and receives a signal transmitted at the timing of the transmission frame. In an intermittent reception device that sets an intermittent reception interval that is an integer p times the frame interval and turns on and off the power of the reception circuit at a timing according to the intermittent reception interval, the standby clock that is slower than the reference clock and the standby clock that is faster A frame timing detection circuit that receives a signal transmitted from one radio station and detects a frame timing synchronized with a transmission frame, and a frame timing interval over k frames (k is an integer of 1 or more). It counts with the standby clock, and in addition, the frame timing and the phase error between the standby clock are A frame timing interval measuring circuit for measuring a frame timing interval of k frames represented by the sum of the respective clock numbers, and a frame timing interval of k frames represented by the sum of the respective clock numbers. The number of clocks q obtained by converting the number of clocks obtained by accumulating the phase error represented by the number of high-speed clocks at the intermittent reception interval to the number of standby clocks is calculated, and the number of standby clocks (( n / k) * p + q).

  The intermittent reception control circuit may measure the frame timing interval corresponding to the intermittent reception interval with the standby clock and set the frame timing interval as the next intermittent reception interval.

  The intermittent receiving device of the first invention has a configuration in which an oscillator or an oscillator constituting a standby clock is surrounded by a material having low heat conduction characteristics. The intermittent receiving device of the second invention has a configuration in which an oscillator or an oscillator constituting the standby clock and the high-speed clock is surrounded by a material having low heat conduction characteristics.

  In a radio station equipped with the intermittent receiving device of the present invention, a signal transmitted from one radio station is received to detect frame timing, the frame timing interval is measured by the number of standby clocks, and the intermittent reception interval is further measured. Is estimated as the number of standby clocks, the activation timing of the reception circuit of the radio station corresponding to the intermittent reception interval can be accurately controlled. As a result, while using a low power standby clock, it is possible to shorten the time for which the power of the receiving circuit is turned on in advance corresponding to the intermittent reception interval, and as a result, the power consumption in intermittent reception can be reduced. Can be reduced.

  In addition, by measuring the phase error between the frame timing measured with the low-speed standby clock and the standby clock using the high-speed clock, and correcting the number of clocks at the intermittent reception interval estimated from the frame timing interval, further reception The start timing of the circuit can be accurately controlled.

  In addition, by measuring the frame timing interval corresponding to the intermittent reception interval with the standby clock and setting it as the next intermittent reception interval, even if the frequency of the standby clock changes due to temperature, the timing error due to it is reduced. can do.

  In addition, by configuring the oscillator or oscillator constituting the standby clock or high-speed clock with a material with low thermal conductivity characteristics, the temperature change of the oscillator or oscillator is moderated against the surrounding rapid temperature change, A standby clock and a high-speed clock can be operated stably. Thereby, the estimation of the intermittent reception interval based on the measurement of the filter timing interval and the accuracy of the actually measured value of the frame timing interval corresponding to the intermittent reception interval can be improved.

(First embodiment)
FIG. 1 shows a first embodiment of the intermittent receiving apparatus of the present invention.
In FIG. 1, a transmission circuit 41 of a base station 40 generates a frame composed of a transmission frame and a reception frame synchronized with a reference clock (fh ′) 42, and transmits a transmission signal addressed to the wireless terminal 10 at the timing of the transmission frame. To do. FIG. 2 (a) shows an operation example of the base station 40, and shows the relationship between the reference clock fh ′, the frame, and the transmission signal. The frame interval Tf ′, which is the time length of one frame, is a constant value determined by the wireless system.

  The wireless terminal 10 includes a frame timing detection circuit 13 in the reception circuit 12, and further includes a standby clock 14, a frame timing interval measurement circuit 20, and an intermittent reception control circuit 21. The frame timing detection circuit 13 receives the transmission signal from the base station 40 and detects the frame timing flt synchronized with the transmission frame. The frame timing interval measurement circuit 20 measures the interval of the frame timing flt detected by the frame timing detection circuit 13 with the standby clock (fl) 14. The intermittent reception control circuit 21 estimates an intermittent reception interval that is an integral multiple of the measured frame timing interval Tflt, and controls the power-on / off timing of the reception circuit 12 according to the estimation.

  FIG. 2B shows an example of the operation of the frame timing interval measurement circuit 20 of the wireless terminal 10 and shows the measurement principle of the frame timing interval Tflt of one frame. The frame timing flt is a timing indicating the start point of the frame. For example, the frame timing flt can be obtained by frame synchronization using the preamble of the header portion of the received signal. Generally, when detecting the frame timing, a high-speed clock with a short period built in the receiving circuit 12 is used, so that a time error between the frame timing set on the base station side and the frame timing detected on the wireless terminal side Is very small and negligible for the intermittent reception control of the present invention.

The frame timing interval Tflt is the time interval of the detected frame timing flt. For example, the counter that counts the standby clock fl at the first frame timing flt is started, and the counter is stopped at the second frame timing flt. If the number of clocks measured with the standby clock fl (cycle 1 / fl) is n, Tflt = (1 / fl) * n
As measured. In addition, when receiving each frame and detecting the frame timing flt, the frame interval Tf 'is equal to the frame timing interval Tflt, but the frame timing interval Tflt when receiving the frame intermittently is longer than the frame interval Tf'. . The standby clock fl is a low-speed clock having a frequency lower than that of the high-speed clock used for frame timing detection and consumes less power.

  Hereinafter, intermittent reception control in the frame timing interval measurement circuit 20 and the intermittent reception control circuit 21 will be described with reference to FIGS. FIG. 3 shows a case where the intermittent reception interval is estimated from the measurement of the frame timing interval Tflt of one frame.

The intermittent reception interval is generally set to an integer p times the frame interval Tf ′. Since the frame interval Tf ′ is measured as a frame timing interval Tflt (= (1 / fl) * n) of one frame as shown in FIGS. 2 and 3,
Intermittent reception interval = Tflt * p
= (1 / fl) * n * p
It can be expressed as. That is, the intermittent reception interval is p times the clock number n of the standby clock fl corresponding to the frame timing interval Tflt of one frame.

  For example, when the standby clock fl = 10 kHz and the frame interval Tf ′ = 1 second, the frame timing interval Tflt of one frame is detected as the number of clocks n = 10000. Here, if the intermittent reception interval is 10 seconds (10 times the frame interval (p = 10)), the intermittent reception control circuit 21 estimates that the number of standby clocks fl is n = 100000. When the standby clock fl = 5.123 kHz and the frame interval Tf ′ = 1 second, the frame timing interval Tflt of one frame is detected as the number of clocks n = 5123. Here, if the intermittent reception interval is 10 seconds, the intermittent reception control circuit 21 estimates that the number of clocks of the standby clock fl is n = 51230.

The intermittent reception control circuit 21 turns off the power of the reception circuit 12 when the intermittent reception operation is started after receiving the transmission signal from the base station, and the time until the next activation (reception standby time) is determined by the standby clock fl. Count. The actual reception standby time is set shorter than the estimated intermittent reception interval (100000 or 51230 as the clock number n of the standby clock fl in the above example) in consideration of the rise time of the circuit and the like. For example,
Reception standby period = intermittent reception interval−circuit rise time a−already received time b Here, “already received time b” is based on the frame timing flt detected at the beginning of the transmission signal from the base station as the frame timing interval Tflt, and the reception standby period is based on the frame timing interval Tflt. On the other hand, since the intermittent reception interval is based on the end of reception of the transmission signal from the base station, it corresponds to the signal reception time.

  In the example shown in FIG. 3, (1) the frame timing flt is detected and the frame timing interval Tflt (= (1 / fl) * n) of one frame is measured, and (2) the frame timing interval Tflt of one frame is intermittent. Estimate the reception interval Tflt * p (= (1 / fl) * n * p), and (3) count the reception standby period (intermittent reception interval -ab) corresponding to the intermittent reception interval with the standby clock fl (4) At the reception start timing after the reception standby period has elapsed, the power supply of the reception circuit 12 is turned on to enter the reception operation, and the next frame timing flt is detected.

  Here, while the reception standby period is counted by the standby clock fl, (5) the actual intermittent reception interval, that is, the frame timing interval Tflt in the case of intermittent reception is measured using the standby clock fl. At this time, the number of clocks of the standby clock fl is s. (6) The next intermittent reception interval is not set after detecting the frame timing interval Tflt of one frame, but is set using the latest intermittent reception interval (number of clocks s) measured in (5). As a result, the measured value of the intermittent reception interval measured at the closest timing can be used as the next intermittent reception interval, and even if the frequency of the standby clock fl changes due to the temperature, the timing error due to it is reduced. be able to. Note that an error between the intermittent reception interval estimated in (2) and the intermittent reception interval actually measured in (5) may be obtained to correct the intermittent reception interval at the next timing.

  By the way, when one cycle (1 / fl) of the standby clock fl is not an integral fraction of the frame interval Tf ′, an error is added to the intermittent reception interval defined as an integer p times the frame interval Tf ′. For example, when the standby clock fl = 10.0007 kHz and the frame interval Tf ′ = 1 second, the frame timing interval Tflt of one frame is detected as the number of clocks n = 10000. Here, if the intermittent reception interval is 10 seconds (10 times the frame interval (p = 10)), the intermittent reception control circuit 21 estimates that the number of standby clocks fl is n = 100000. However, to be exact, the number of clocks n should be estimated as 100007.

  To solve this error problem, it is effective to estimate the intermittent reception interval by measuring the frame timing interval k * Tflt of a plurality of k frames, instead of estimating the intermittent reception interval from the frame timing interval Tflt of one frame. It is. FIG. 4 shows a case where k = 2. That is, an example is shown in which the intermittent reception interval is estimated from the measurement of the frame timing interval 2Tflt of two frames.

  In FIG. 4, (1) the frame timing flt is detected and the frame timing interval 2Tflt of two frames is measured. If the number of clocks at this time is n ′, the average number of clocks in one frame is n ′ / 2. (2) Estimate intermittent reception interval Tflt * p (= (1 / fl) * (n '/ 2) * p) from frame timing interval 2Tflt of 2 frames, and (3) Corresponding reception standby period (intermittent reception) The interval -ab) is counted by the standby clock fl, and (4) the reception circuit 12 is turned on at the reception start timing after the reception standby period elapses to enter the reception operation, and the next frame timing flt is detected. To do. The process of using the measured value of the intermittent reception interval as the next intermittent reception interval is the same as in the example of FIG.

  For example, when the standby clock fl = 10.0007 kHz and the frame interval Tf ′ = 1 second, the frame timing interval 2Tflt of 2 frames is detected as the number of clocks n ′ = 20001 clocks. Here, if the intermittent reception interval is 10 seconds (10 times the frame interval (p = 10)), the intermittent reception control circuit 21 estimates that the number of clocks n of the standby clock fl is 100005. To be precise, the number of clocks n = 100007, but the accuracy can be improved as compared with the case of being based on the frame timing interval of one frame. In general, before entering an intermittent operation, a wireless terminal receives a plurality of frames by communication control such as authentication with a base station and a connection sequence. Therefore, by measuring the frame timing interval over the plurality of frames, it is possible to improve the estimation accuracy of the intermittent reception interval.

(Second Embodiment)
FIG. 5 shows a second embodiment of the intermittent receiving apparatus of the present invention.
In this embodiment, the wireless terminal 11 including the high-speed clock (fg) 15 is used instead of the wireless terminal 10 of the first embodiment shown in FIG. 1, and the accuracy of the frame timing interval Tflt measured by the frame timing interval measuring circuit 22 is used. And the accuracy of the intermittent reception interval estimated by the intermittent reception control circuit 23 is improved.

  6A shows an operation example of the base station 40, FIG. 6B shows an operation example of the frame timing interval measurement circuit 22 of the wireless terminal 11, and shows a process of measuring the frame timing interval Tflt of one frame.

  FIG. 7 shows a case where the intermittent reception interval is estimated from the measurement of the frame timing interval Tflt of one frame. FIG. 8 shows a case where the intermittent reception interval is estimated from the measurement of the frame timing interval Tflt of two frames.

The frame timing interval measurement circuit 22 counts the frame timing interval Tflt with the standby clock fl, and measures the clock number n. Further, the phase error between the frame timing flt and the standby clock fl is measured using the high-speed clock fg having a frequency higher than that of the standby clock fl. Here, the number of clocks obtained by counting the phase difference between the frame timing flt and the next standby clock fl with the high-speed clock fg is m1, and the phase difference between the next frame timing flt and the next standby clock fl is the high-speed clock fg. When the number of clocks counted is m2, the frame timing interval Tflt is
Tflt = (1 / fl) * n + (1 / fg) * (m1-m2) (1)
It becomes.

Next, assuming that the intermittent reception interval is an integer p times the frame timing interval Tflt, the intermittent reception interval is
Intermittent reception interval = Tflt * p
= (1 / fl) * n * p + (1 / fg) * (m1−m2) * p (2)
It becomes. About the second term of this equation (2)
(1 / fg) * (m1-m2) * p / (1 / fl) = q (3)
If we define an integer q (an integer by rounding down or rounding),
Intermittent reception interval = (1 / fl) * (n * p + q) (4)
It becomes. The intermittent reception interval represented by this equation is obtained by correcting the phase error between the frame timing flt and the standby clock fl accumulated by multiplying the frame timing interval Tflt by an integer p by the number of clocks q of the standby clock fl. means. When the high-speed clock fg is not used, as shown in the first embodiment,
Intermittent reception interval = (1 / fl) * n * p
And is obtained by removing q in equation (4).

For example, when the standby clock fl = 10.0007 kHz and the frame interval Tf ′ = 1 second, the frame timing interval Tflt of one frame is detected as the number of clocks n = 10000. Further, when fg≈100 kHz, m1 = 8 and m2 = 1 are detected. As a result, if the intermittent reception interval is 10 seconds (10 times the frame interval (p = 10)), the number of clocks of the standby clock fl is
(1 / fl) * (n * p + q) = (1 / 10kHz) * (10000 * 10 + [(1 / 100kHz) * (8-1) * 10 / (1 / 10kHz)]
= (1 / 10kHz) * 100007
Thus, the error is corrected.

  The high-speed clock fg can be shared with a clock for processing the reception circuit 12 of the wireless terminal 11, and the operation period can be the same as the reception period as shown in FIGS. That is, the high-speed clock fg is used by the frame timing interval measurement circuit 22 only when the reception circuit 12 is activated and the frame timing is detected at the time of reception, and the power supply is not turned off during the reception standby period. Therefore, measurement of the frame timing interval and estimation of the intermittent reception interval can be performed with high accuracy without increasing the power consumption.

  The high-speed clock fg is preferably synchronized with the low-speed clock fl, but is not necessarily synchronized.

The frame timing interval Tflt is measured not only by measuring the frame timing interval of one frame as shown in FIG. 7, but also by measuring the frame timing intervals of a plurality of k frames as shown in FIG. The estimation accuracy of the reception interval can be increased. FIG. 8 shows the case of k = 2, but the frame timing interval 2Tflt of two frames is n ′ as the number of clocks counted with the standby clock fl, and the phase error between the frame timing flt counted with the high-speed clock fg and the standby clock fl. If the number of clocks is (m1'-m2 ')
Intermittent reception interval = Tflt * p
= (1 / fl) * n '/ 2 * p + (1 / fg) * (m1'-m2') / 2 * p (2 ')
It becomes. About the second term of this equation (2 ')
(1 / fg) * (m1′−m2 ′) / 2 * p / (1 / fl) = q ′ (3 ′)
If we define an integer q '(where q' is a rounded or rounded integer)
Intermittent reception interval = (1 / fl) * (n ′ / 2 * p + q ′) (4 ′)
It becomes. The intermittent reception interval represented by this equation is obtained by multiplying the frame timing flt accumulated by multiplying the average frame timing interval Tflt of one frame by an integer p and the phase error between the standby clock fl and the number of clocks q of the standby clock fl. 'Means to correct.

  The processes (1) to (6) in FIGS. 7 and 8 correspond to the processes (1) to (6) in FIGS. 3 and 4 of the first embodiment. In particular, the frequency of the standby clock fl generally varies with temperature. In order to cope with temperature fluctuations during intermittent reception, it is effective to use an actual measurement value of the immediately preceding frame timing interval when estimating the intermittent reception interval. For that purpose, it is important to always measure the frame timing interval and update the estimated value of the intermittent reception interval even during intermittent reception.

(Third embodiment)
The standby clock fl and high-speed clock fg used in intermittent reception control cover the surroundings with a material with low thermal conductivity (heat is not easily transmitted), so that the temperature change of the oscillator or oscillator can be controlled against the ambient temperature change. It can be relaxed. As a method for this, there is a method of making a material covering the crystal oscillator a material having low thermal conductivity, a method of enclosing the crystal oscillator or the crystal oscillator with a material having low thermal conductivity, and a board or module on which the clock is mounted has a thermal conductivity characteristic. There is a method of surrounding with a low material. An example of a material having low thermal conductivity is foamed polystyrene.

The figure which shows the 1st Embodiment of this invention. The figure which shows the measurement procedure of frame timing space | interval Tflt of 1st Embodiment. The figure which shows the estimation procedure (1 frame measurement) of the intermittent reception interval of 1st Embodiment. The figure which shows the estimation procedure (2 frame measurement) of the intermittent reception interval of 1st Embodiment. The figure which shows the 2nd Embodiment of this invention. The figure which shows the measurement procedure of frame timing space | interval Tflt of 2nd Embodiment. The figure which shows the estimation procedure (1 frame measurement) of the intermittent reception interval of 2nd Embodiment. The figure which shows the estimation procedure (2 frame measurement) of the intermittent reception interval of 2nd Embodiment. The figure which shows the structural example of the conventional intermittent receiver.

Explanation of symbols

10, 11 Wireless terminal 12 Reception circuit 13 Frame timing detection circuit 14 Standby clock (fl)
15 High-speed clock (fg)
20, 22 Frame timing interval measurement circuit 21, 23 Intermittent reception control circuit 40 Base station 41 Transmission circuit 42 Reference clock (fh ')

Claims (5)

One radio station generates a frame composed of a transmission frame and a reception frame synchronized with the reference clock, and is provided in the other radio station that receives a signal transmitted at the timing of the transmission frame. In the intermittent reception device that sets the intermittent reception interval of, and turns on and off the power of the reception circuit at a timing according to the intermittent reception interval,
A standby clock slower than the reference clock;
A frame timing detection circuit that receives a signal transmitted from the one radio station and detects a frame timing synchronized with the transmission frame;
a frame timing interval measuring circuit that counts the frame timing interval over k frames (k is an integer of 1 or more) with the standby clock and measures the frame timing interval of k frames represented by the clock number n;
An intermittent reception control circuit that inputs a frame timing interval of k frames represented by the clock number n and sets the clock number ((n / k) * p) of the standby clock as the intermittent reception interval. An intermittent receiver characterized by that. One radio station generates a frame composed of a transmission frame and a reception frame synchronized with the reference clock, and is provided in the other radio station that receives a signal transmitted at the timing of the transmission frame. In the intermittent reception device that sets the intermittent reception interval of, and turns on and off the power of the reception circuit at a timing according to the intermittent reception interval,
A standby clock slower than the reference clock;
A high-speed clock faster than the standby clock;
A frame timing detection circuit that receives a signal transmitted from the one radio station and detects a frame timing synchronized with the transmission frame;
The frame timing interval over k frames (k is an integer equal to or greater than 1) is counted by the standby clock, and the frame timing and standby clock phase error are counted by the high-speed clock, and expressed as the sum of the respective clock numbers. A frame timing interval measuring circuit for measuring a frame timing interval of k frames to be performed;
The frame timing interval of k frames represented by the sum of the respective clock numbers is input, and the clock number obtained by accumulating the phase error represented by the number of clocks of the high-speed clock at the intermittent reception interval is the clock of the standby clock. An intermittent reception control circuit that calculates a clock number q converted to a number and sets the clock number ((n / k) * p + q) of the standby clock as the intermittent reception interval. apparatus. In the intermittent receiving device according to claim 1 or 2,
The intermittent reception control circuit is configured to measure a frame timing interval corresponding to the intermittent reception interval with the standby clock and set the frame timing interval as a next intermittent reception interval. . The intermittent receiving device according to claim 1,
An intermittent receiving apparatus characterized in that an oscillator or an oscillator constituting the standby clock is surrounded by a material having low heat conduction characteristics. The intermittent receiving device according to claim 2,
An intermittent receiving device characterized in that the standby clock and the oscillator or oscillator constituting the high-speed clock are surrounded by a material having low thermal conductivity.

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