JP4558234B2 - プログラマブルロジックデバイス - Google Patents
プログラマブルロジックデバイス Download PDFInfo
- Publication number
- JP4558234B2 JP4558234B2 JP2001129184A JP2001129184A JP4558234B2 JP 4558234 B2 JP4558234 B2 JP 4558234B2 JP 2001129184 A JP2001129184 A JP 2001129184A JP 2001129184 A JP2001129184 A JP 2001129184A JP 4558234 B2 JP4558234 B2 JP 4558234B2
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- row
- array blocks
- segmentation
- stitch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17764—Structural details of configuration resources for reliability
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US19975100P | 2000-04-26 | 2000-04-26 | |
| US60/199751 | 2000-04-26 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002033654A JP2002033654A (ja) | 2002-01-31 |
| JP2002033654A5 JP2002033654A5 (enExample) | 2007-09-06 |
| JP4558234B2 true JP4558234B2 (ja) | 2010-10-06 |
Family
ID=22738867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001129184A Expired - Fee Related JP4558234B2 (ja) | 2000-04-26 | 2001-04-26 | プログラマブルロジックデバイス |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US6600337B2 (enExample) |
| EP (1) | EP1162747B1 (enExample) |
| JP (1) | JP4558234B2 (enExample) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6850957B2 (en) * | 2002-03-12 | 2005-02-01 | Hitachi, Ltd. | Information system and data access method |
| US7111213B1 (en) | 2002-12-10 | 2006-09-19 | Altera Corporation | Failure isolation and repair techniques for integrated circuits |
| US7062685B1 (en) | 2002-12-11 | 2006-06-13 | Altera Corporation | Techniques for providing early failure warning of a programmable circuit |
| US7024327B1 (en) | 2002-12-18 | 2006-04-04 | Altera Corporation | Techniques for automatically generating tests for programmable circuits |
| US7058534B1 (en) | 2003-03-19 | 2006-06-06 | Altera Corporation | Method and apparatus for application specific test of PLDs |
| US7215140B1 (en) | 2003-05-30 | 2007-05-08 | Altera Corporation | Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method |
| US7180324B2 (en) * | 2004-05-28 | 2007-02-20 | Altera Corporation | Redundancy structures and methods in a programmable logic device |
| US7277346B1 (en) | 2004-12-14 | 2007-10-02 | Altera Corporation | Method and system for hard failure repairs in the field |
| US7265573B1 (en) | 2004-12-18 | 2007-09-04 | Altera Corporation | Methods and structures for protecting programming data for a programmable logic device |
| JP4797801B2 (ja) * | 2005-06-30 | 2011-10-19 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
| US7793251B2 (en) * | 2006-01-12 | 2010-09-07 | International Business Machines Corporation | Method for increasing the manufacturing yield of programmable logic devices |
| US8532850B2 (en) | 2009-03-17 | 2013-09-10 | General Electric Company | System and method for communicating data in locomotive consist or other vehicle consist |
| US8935022B2 (en) | 2009-03-17 | 2015-01-13 | General Electric Company | Data communication system and method |
| US8798821B2 (en) | 2009-03-17 | 2014-08-05 | General Electric Company | System and method for communicating data in a locomotive consist or other vehicle consist |
| US9637147B2 (en) | 2009-03-17 | 2017-05-02 | General Electronic Company | Data communication system and method |
| US9379775B2 (en) | 2009-03-17 | 2016-06-28 | General Electric Company | Data communication system and method |
| US7456653B2 (en) * | 2007-03-09 | 2008-11-25 | Altera Corporation | Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks |
| US7508231B2 (en) * | 2007-03-09 | 2009-03-24 | Altera Corporation | Programmable logic device having redundancy with logic element granularity |
| EP1995663A1 (en) * | 2007-05-22 | 2008-11-26 | Panasonic Corporation | System and method for local generation of programming data in a programable device |
| US8583299B2 (en) | 2009-03-17 | 2013-11-12 | General Electric Company | System and method for communicating data in a train having one or more locomotive consists |
| US7902855B1 (en) | 2010-03-03 | 2011-03-08 | Altera Corporation | Repairable IO in an integrated circuit |
| KR101638976B1 (ko) * | 2010-08-25 | 2016-07-13 | 삼성전자주식회사 | 재구성 가능한 논리 장치 |
| US9513630B2 (en) | 2010-11-17 | 2016-12-06 | General Electric Company | Methods and systems for data communications |
| US10144440B2 (en) | 2010-11-17 | 2018-12-04 | General Electric Company | Methods and systems for data communications |
| WO2013010162A2 (en) | 2011-07-14 | 2013-01-17 | General Electric Company | Method and system for rail vehicle control |
| US9236864B1 (en) | 2012-01-17 | 2016-01-12 | Altera Corporation | Stacked integrated circuit with redundancy in die-to-die interconnects |
| RU2503993C1 (ru) * | 2012-04-26 | 2014-01-10 | федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Пермский национальный исследовательский политехнический университет" | Программируемое логическое устройство |
| US9893732B1 (en) * | 2016-12-22 | 2018-02-13 | Intel Corporation | Techniques for bypassing defects in rows of circuits |
| US10658067B2 (en) | 2018-05-14 | 2020-05-19 | Micron Technology, Inc. | Managing data disturbance in a memory with asymmetric disturbance effects |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4899067A (en) | 1988-07-22 | 1990-02-06 | Altera Corporation | Programmable logic devices with spare circuits for use in replacing defective circuits |
| US5377124A (en) * | 1989-09-20 | 1994-12-27 | Aptix Corporation | Field programmable printed circuit board |
| US5498975A (en) | 1992-11-19 | 1996-03-12 | Altera Corporation | Implementation of redundancy on a programmable logic device |
| US5434514A (en) * | 1992-11-19 | 1995-07-18 | Altera Corporation | Programmable logic devices with spare circuits for replacement of defects |
| US5504440A (en) * | 1994-01-27 | 1996-04-02 | Dyna Logic Corporation | High speed programmable logic architecture |
| US5369314A (en) | 1994-02-22 | 1994-11-29 | Altera Corporation | Programmable logic device with redundant circuitry |
| US5592102A (en) | 1995-10-19 | 1997-01-07 | Altera Corporation | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices |
| US5721498A (en) * | 1995-12-11 | 1998-02-24 | Hewlett Packard Company | Block segmentation of configuration lines for fault tolerant programmable logic device |
| US5627480A (en) * | 1996-02-08 | 1997-05-06 | Xilinx, Inc. | Tristatable bidirectional buffer for tristate bus lines |
| GB2318663B (en) * | 1996-10-25 | 2000-06-28 | Altera Corp | Hierarchical interconnect for programmable logic devices |
| US6034536A (en) | 1997-02-05 | 2000-03-07 | Altera Corporation | Redundancy circuitry for logic circuits |
| GB2321989B (en) | 1997-02-05 | 2000-10-18 | Altera Corp | Redundancy circuitry for logic circuits |
| US5942913A (en) * | 1997-03-20 | 1999-08-24 | Xilinx, Inc. | FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines |
| JPH10313061A (ja) * | 1997-05-14 | 1998-11-24 | Hitachi Ltd | 半導体集積回路 |
| WO1998053401A1 (en) | 1997-05-23 | 1998-11-26 | Altera Corporation | Redundancy circuitry for programmable logic devices with interleaved input circuits |
-
2001
- 2001-04-26 EP EP01303797A patent/EP1162747B1/en not_active Expired - Lifetime
- 2001-04-26 US US09/844,077 patent/US6600337B2/en not_active Expired - Lifetime
- 2001-04-26 JP JP2001129184A patent/JP4558234B2/ja not_active Expired - Fee Related
-
2003
- 2003-04-22 US US10/422,007 patent/US6759871B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1162747B1 (en) | 2012-02-29 |
| US20030201793A1 (en) | 2003-10-30 |
| US20020003742A1 (en) | 2002-01-10 |
| EP1162747A2 (en) | 2001-12-12 |
| US6759871B2 (en) | 2004-07-06 |
| JP2002033654A (ja) | 2002-01-31 |
| US6600337B2 (en) | 2003-07-29 |
| EP1162747A3 (en) | 2003-03-26 |
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