JP4558220B2 - Digital broadcast receiving apparatus and frame synchronization detection method - Google Patents

Description

上記差動符号化前の２つのフレーム間のＸＯＲ演算を行った結果を、差動符号化後の信号パターンとする。
【００４２】
図４は差動符号化前の２フレーム分のＴＭＣＣキャリアのＸＯＲ演算を示す説明図である。図に示すように、ＸＯＲ演算器４が、１フレーム蓄積器２内のＴＭＣＣキャリアの信号パターンと、１フレーム遅延素子３から出力される１フレーム分遅延されたＴＭＣＣキャリアの信号パターンとの間でＸＯＲ演算を行う（ステップＳＴ４、ＸＯＲ演算ステップ）。このように、ＸＯＲ演算結果はＴＭＣＣキャリアの信号内の同期信号部分に固定パターン“１１１１１１１１１１１１１１１１”が出現する。そして、同期信号以外の部分、例えば、差動基準ビット、形式識別符号、ＴＭＣＣ情報、パリティビットは全て値０となる。
【００４３】
そして、ＸＯＲ演算結果の固定パターン“１１１１１１１１１１１１１１１１”の位置が、ＴＭＣＣキャリア内のどこにあるかをパターン検出器５が検出し、検出結果をフレーム誤差変換器６へ出力する（ステップＳＴ５、パターン検出ステップ）。
【００４４】
パターン検出器５から出力された検出結果、即ち、固定パターン“１１１１１１１１１１１１１１１１”の検出位置情報を基に、ディジタル放送受信装置においてフレームの先頭と考えられている位置から、真のフレーム先頭位置が何シンボル分ずれているかをフレーム誤差として、フレーム誤差変換器６が計算し、同期処理部（図示せず）へフィードバックする（ステップＳＴ６、フレーム誤差変換ステップ）。従って、ＸＯＲ演算で得られた結果の中で、上記の固定パターン“１１１１１１１１１１１１１１１１”の位置をサーチすることで、フレームの同期誤差の大きさを得ることができる。つまり、検出した固定パターン“１１１１１１１１１１１１１１１１”の先頭がフレームの２シンボル目（差動基準ビットの次のビット位置）に相当する。
【００４５】
以上のように、この実施の形態１によれば、差動復調器１がＴＭＣＣキャリアの差動基準ビットの値を問わずＴＭＣＣキャリア内における各ビットの値をそれぞれの直前のビットの値と比較して変化しない場合は０、変化する場合は１として差動復調し、ＸＯＲ演算器４が、１フレーム蓄積器２及び１フレーム遅延素子３から得られる２フレームのＴＭＣＣキャリアの間のＸＯＲ演算を実行し、パターン検出器５が、ＸＯＲ演算結果をサーチして、固定パターン“１１１１１１１１１１１１１１１１”の有無を検出して、ＴＭＣＣキャリア内の同期情報である同期信号の位置を知り、フレーム同期処理を行うように構成したので、差動復調処理において差動基準ビットの算出動作が省略され、且つ、差動復調した後、同期信号のビットパターンに一致するか否かの比較処理を、連続する２つのＴＭＣＣキャリアのそれぞれに対して行わなくても良いことから、フレーム同期処理に要する時間を短縮することができ、ディジタル放送受信装置を迅速に立ち上げることができる。
【００４６】
実施の形態２．
図５はこの発明の実施の形態２によるディジタル放送受信装置の構成を示すブロック図である。図において、１３は多数決判定器（多数決判定手段）で、差動復調器１から得られたＴＭＣＣキャリアのうち、同一データ内容が格納されるべき複数のＴＭＣＣキャリアが存在するとき、これら複数のＴＭＣＣキャリアのそれぞれに対応するビットにおいて出現頻度が最も高い値を判定して多数決判定したＴＭＣＣキャリアを生成する。なお、図１と同一構成要素には同一符号を付して重複する説明を省略する。
【００４７】
次に動作について説明する。
図６は図５のディジタル放送受信装置によるフレーム同期処理を示すフロー図であり、このフローに沿って動作の説明を行う。
先ず、高速フーリエ変換処理されたＩＳＤＢ信号のディジタルデータを、キャリア分割器によって、主信号キャリア、パイロットキャリア、付加情報キャリア、制御信号キャリアであるＴＭＣＣキャリアなどに分割し抽出するまでの動作は、上記実施の形態１と同様であるので重複する説明を省略する。
【００４８】
キャリア分割器により分割され抽出されたＴＭＣＣキャリアは、差動復調器１により差動復調される（ステップＳＴ１ａ、差動復調ステップ）。この差動復調処理も上記実施の形態１で示した、差動基準ビットの値を問わず（即ち、差動基準ビットを検出することなく）、ＴＭＣＣキャリアの最初の１ビット目の値を基準に直前のビットに対して変化しない場合は０、変化する場合は１として差動復調する方法を適用することで、差動復調処理に係る時間を短縮化することができる。
【００４９】
また、ＩＳＤＢ信号のＤＢＰＳＫ変調において、そのモード数によって複数のＴＭＣＣキャリアに同一内容のデータが格納されて搬送される場合がある。このように、複数のＴＭＣＣキャリアに同一内容のデータを格納することで、受信状態の悪い搬送波の周波数に対応するＴＭＣＣキャリアに格納されていたデータ内容を、他の周波数に対応するＴＭＣＣキャリアから受信することができるようにしている。
【００５０】
図７はＩＳＤＢ信号のキャリアの中に同一内容のデータを格納するＴＭＣＣキャリアが複数本存在する例を示す図である。図に示す例は、モード１の場合で同一内容のデータを格納するＴＭＣＣキャリアが５本（ＴＭＣＣ１〜ＴＭＣＣ５）存在する。これらＴＭＣＣキャリアは、理想的には全てが同一のデータ内容を有するはずである。しかしながら、受信装置が設置される箇所の通信環境によって、ある周波数の搬送波の受信に障害が生じた場合に上記ＴＭＣＣキャリア（ＴＭＣＣ１〜ＴＭＣＣ５）のうちのいずれかが格納するデータ内容の一部が変化する可能性がある。ＴＭＣＣキャリアに格納されるデータが、受信障害などによって完全に誤りのあるものと判定することができれば、他の周波数に対応するＴＭＣＣキャリアから同一のデータを受信する処理に移行することができるが、図示の例のように、データ中の一部が変化すると、真のデータ内容を有するＴＭＣＣキャリアがどれであるのかを判定できない場合がある。
【００５１】
そこで、この実施の形態２では、多数決判定器１３が上記ＴＭＣＣキャリア（ＴＭＣＣ１〜ＴＭＣＣ５）のそれぞれに対応するビットが有する値の出現頻度を判定して、出現頻度が最も高い値を格納するＴＭＣＣキャリアを生成する（ステップＳＴ２ａ、多数決判定ステップ）。
図８は実施の形態２による多数決判定器の多数決判定処理を説明する説明図である。図示の例では、同一内容のデータを格納すべきＴＭＣＣキャリア（ＴＭＣＣ１〜ＴＭＣＣ５）が、上述した受信側の通信状態によって、差動基準ビットや同期信号の最初のシンボル番号におけるビットの値が、ＴＭＣＣキャリアによって（搬送波の周波数の違いによって）異なる値となって受信されている。
これに対して、多数決判定器１３は、キャリア番号（搬送波の周波数方向）に沿ってそれぞれのＴＭＣＣキャリア（ＴＭＣＣ１〜ＴＭＣＣ５）の同一シンボル番号を有する各ビットの値の出現頻度を計数する。この計数結果として得られた出現頻度が最も高い値を、多数決判定器１３が上記ビットに対する最も確からしい値として判定し、この値を格納するＴＭＣＣキャリアを生成する。
【００５２】
上述のようにして、多数決判定器１３によって多数決判定されたＴＭＣＣキャリアは１フレーム蓄積器２内に格納される。この１フレーム蓄積器２内に格納された１フレーム分のＴＭＣＣキャリアは、１フレーム遅延素子３内で１フレーム分だけ遅延される。これにより、１フレーム遅延素子３から出力されるＴＭＣＣキャリアと、１フレーム蓄積器２内のＴＭＣＣキャリアとで、連続した２フレーム分のＴＭＣＣキャリアが得られる（ステップＳＴ３ａ、ステップＳＴ４ａ）。
【００５３】
このあと、ＸＯＲ演算器４による差動復調処理後における２フレーム分のＴＭＣＣキャリアのビットパターンに対するＸＯＲ演算処理（ステップＳＴ５ａ、ＸＯＲ演算ステップ）、ＸＯＲ演算結果の固定パターン“１１１１１１１１１１１１１１１１”の位置がＴＭＣＣキャリア内のどこにあるかをパターン検出器５が検出する（ステップＳＴ６ａ、パターン検出ステップ）、パターン検出器５から出力された検出結果を基にしてフレーム誤差変換器６がフレーム誤差を計算し、同期処理部（図示せず）へフィードバックする（ステップＳＴ６、フレーム誤差変換ステップ）については、上記実施の形態１で示したものと同様である。
【００５４】
以上のように、この実施の形態２によれば、差動復調されたＴＭＣＣキャリアのうち、同一データ内容が格納されるべき複数のＴＭＣＣキャリアが存在するとき、これら複数のＴＭＣＣキャリアのそれぞれに対応するビットが有する値の出現頻度を判定して、真のＴＭＣＣキャリアとして出現頻度が最も高い値を格納するＴＭＣＣキャリアを生成するので、ノイズの多い劣悪な受信環境においても、ＴＭＣＣキャリアに格納されたデータを精度良く受信することができる。これにより、同期信号のビットパターンを検出する処理を正確に行うことができ、フレーム誤差を精度良く検出することができる。
【００５５】
実施の形態３．
図９はこの発明の実施の形態３によるディジタル放送受信装置の構成を示すブロック図である。図において、１５はパワー変換器（パワー変換手段）で、ＸＯＲ演算器４にて得られた演算結果のビットパターンに対して、同期情報を構成するビット数分の加算を１ビットごとずらしながら行い、この加算結果をピーク検出器１６に逐次出力する。１６はピーク検出器（パターン検出手段）であって、パワー変換器１５からの加算結果のうち、最大加算値に対応するＴＭＣＣキャリア内の位置を検出し、フレーム誤差変換器６に出力する。なお、図１と同一構成要素には同一符号を付して重複する説明を省略する。
【００５６】
次に動作について説明する。
図１０は図９のディジタル放送受信装置によるフレーム同期処理を示すフロー図であり、このフローに沿って動作の説明を行う。
先ず、高速フーリエ変換処理されたＩＳＤＢ信号のディジタルデータを、キャリア分割器によって、主信号キャリア、パイロットキャリア、付加情報キャリア、制御信号キャリアであるＴＭＣＣキャリアなどに分割する。これによって抽出したＴＭＣＣキャリアを、差動復調器１により差動復調する（ステップＳＴ１ｂ、差動復調ステップ）。この差動復調処理も上記実施の形態１で示した、差動基準ビットの値を問わず（即ち、差動基準ビットを検出することなく）、ＴＭＣＣキャリアの最初の１ビット目の値を基準に直前のビットに対して変化しない場合は０、変化する場合は１として差動復調する方法を適用することで、差動復調処理に係る時間を短縮化することができる。
【００５７】
差動復調されたＴＭＣＣキャリアは１フレーム蓄積器２内に格納される。この１フレーム蓄積器２内に格納された１フレーム分のＴＭＣＣキャリアは、１フレーム遅延素子３内で１フレーム分だけ遅延される。これにより、１フレーム遅延素子３から出力されるＴＭＣＣキャリアと、１フレーム蓄積器２内のＴＭＣＣキャリアとで、連続した２フレーム分のＴＭＣＣキャリアが得られる（ステップＳＴ２ｂ、ステップＳＴ３ｂ）。
【００５８】
このあと、ＸＯＲ演算器４による差動復調処理後における２フレーム分のＴＭＣＣキャリアのビットパターンに対するＸＯＲ演算処理が行われる（ステップＳＴ４ｂ、ＸＯＲ演算ステップ）。これによって得られたＸＯＲ演算結果の固定パターン“１１１１１１１１１１１１１１１１”を有するＴＭＣＣキャリアは、パワー変換器１５に出力される。
【００５９】
パワー変換器１５では、ＸＯＲ演算器４によって得られた演算結果のビットパターンに対して、同期信号を構成するビット数分の加算を１ビットごとずらしながら行う（ステップＳＴ５ｂ、パワー変換ステップ）。
図１１は実施の形態３によるパワー変換器及びピーク検出器の同期信号パターンの検出処理を説明する説明図である。図１１の上段に示したように、パワー変換器１５は、ＸＯＲ演算器４からＴＭＣＣキャリアを入力すると、ＴＭＣＣキャリアの時間方向に並ぶビット列に対して、１６ビット加算（同期信号を構成するビット数分の加算）を１ビットごとずらしながら行う。ＸＯＲ演算器４において、同期信号に対応する固定パターンとして１６ビットの“１１１１１１１１１１１１１１１１”が得られることから、上述したパワー変換器１５による１６ビット加算が上記固定パターンに含まれる論理値１を全て加算できる位置では、加算値が十進数で１６となり、この位置がＴＭＣＣキャリアにおける同期信号の固定パターンの位置に相当する。
【００６０】
図１１の上段では、パワー変換器１５による１６ビット加算のビット列中における始点がずれていると、加算値が「１５」，「１４」，「１３」，「１２」，「１１」などとなって最大値が得られない。これらパワー変換器１５による加算値は、ピーク検出器１６に逐次出力される。
【００６１】
ピーク検出器１６は、パワー変換器１５からの加算値から、図１１の下段に示すような各ビットが送られる時間と加算結果との関係を求め、最大加算値が算出されたビットパターンの位置を同期信号の固定パターンの位置として検出する（ステップＳＴ６ｂ、パターン検出ステップ）。図１１の下段のグラフ図からわかるように、ＴＭＣＣキャリアの時間方向に並ぶビット列に対して１６ビット加算を行った結果は、同期信号の最初のビットを含めた最も高い加算値１６となってピークを示し、他のビット位置を加算の始点とする１６ビット加算では１６未満の加算結果をとる。ピーク検出器１６では、上記ピークとなる１６ビット加算のビット列中における始点に対応する時間を算出し、フレーム誤差変換器６へ出力する。
【００６２】
フレーム誤差変換器６では、ピーク検出器１６からの出力結果、即ち、固定パターン“１１１１１１１１１１１１１１１１”の最初のビットに対応する時間を基に、ディジタル放送受信装置においてフレームの先頭と考えられている位置から、真のフレーム先頭位置が何シンボル分ずれているかをフレーム誤差として計算し、同期処理部（図示せず）へフィードバックする（ステップＳＴ７ｂ、フレーム誤差変換ステップ）。従って、ＸＯＲ演算で得られた結果の中で、上記の固定パターン“１１１１１１１１１１１１１１１１”の位置をサーチすることで、フレームの同期誤差の大きさを得ることができる。つまり、検出した固定パターン“１１１１１１１１１１１１１１１１”の先頭がフレームの２シンボル目（差動基準ビットの次のビット位置）に相当する。
【００６３】
以上のように、この実施の形態３によれば、ＸＯＲ演算して得られたＴＭＣＣキャリアのビットパターンに対して、同期情報を構成するビット数分の加算を１ビットごとずらしながら行い、最大加算値が算出されたビットパターンの位置を、ＴＭＣＣキャリアに含まれる同期情報の所定ビットパターンの位置として検出するので、同期信号のビットパターンを検出する処理を正確に行うことができ、フレーム誤差を精度良く検出することができる。
【００６４】
なお、上記実施の形態３の構成を上記実施の形態２に適用してもよく、これにより、両実施の形態の効果をともに得ることができる。
【００６５】
【発明の効果】
以上のように、この発明によれば、受信したＩＳＤＢ信号からのＤＢＰＳＫ変調されたＴＭＣＣキャリアに対して、その差動基準ビットの値を問わずＴＭＣＣキャリア内における各ビットの値をそれぞれの直前のビットの値と比較して変化しない場合は０、変化する場合は１として差動復調し、差動復調した２フレームのＴＭＣＣキャリア間の排他的論理和演算を実行し、この演算結果をサーチして、ＴＭＣＣキャリアに含まれる同期情報の所定ビットパターンの位置を検出し、この検出結果に基づいて、ＩＳＤＢ信号のフレームの先頭位置までのずれをフレーム誤差として出力するので、差動復調処理において差動基準ビットの算出動作が省略され、且つ、差動復調した後、同期信号のビットパターンに一致するか否かの比較処理を、連続する２つのＴＭＣＣキャリアのそれぞれに対して行わなくても良いことから、フレーム同期処理に要する時間を短縮することができ、ディジタル放送受信装置を迅速に立ち上げることができるという効果がある。
【００６６】
この発明によれば、ＴＭＣＣキャリア内の同期情報が１６ビットの場合、同期情報に対応するパターンが“１１１１１１１１１１１１１１１１”となり、同期情報以外のビットが全て０となる所定ビットパターンを検出するので、差動復調した後、同期信号のビットパターンに一致するか否かの比較処理を、連続する２つのＴＭＣＣキャリアのそれぞれに対して行わなくても良いことから、フレーム同期処理に要する時間を短縮することができ、ディジタル放送受信装置を迅速に立ち上げることができるという効果がある。
【００６７】
この発明によれば、差動復調されたＴＭＣＣキャリアのうち、同一データ内容が格納されるべき複数のＴＭＣＣキャリアが存在するとき、これら複数のＴＭＣＣキャリアのそれぞれに対応するビットが有する値の出現頻度を判定して、出現頻度が最も高い値を格納するＴＭＣＣキャリアを生成し、これを２フレーム分蓄積して、これらＴＭＣＣキャリア間の排他的論理和演算を実行するので、ノイズの多い劣悪な受信環境においても、ＴＭＣＣキャリアに格納されたデータを精度良く受信することができるという効果がある。これにより、同期信号のビットパターンを検出する処理を正確に行うことができ、フレーム誤差を精度良く検出することができるという効果がある。
【００６８】
この発明によれば、ＸＯＲ演算結果のビットパターンに対して、同期情報を構成するビット数分の加算を１ビットごとずらしながら行い、最大加算値が算出されたビットパターンの位置を、ＴＭＣＣキャリアに含まれる同期情報の所定ビットパターンの位置として検出するので、同期信号のビットパターンを検出する処理を正確に行うことができ、フレーム誤差を精度良く検出することができるという効果がある。
【図面の簡単な説明】
【図１】 この発明の実施の形態１によるディジタル放送受信装置の構成を示すブロック図である。
【図２】 図１のディジタル放送受信装置によるフレーム同期処理を示すフロー図である。
【図３】 実施の形態１によるディジタル放送受信装置によるＴＭＣＣキャリア内の同期信号の差動復調方法を説明する説明図である。
【図４】 差動符号化前の２フレーム分のＴＭＣＣキャリアのＸＯＲ演算を示す説明図である。
【図５】 この発明の実施の形態２によるディジタル放送受信装置の構成を示すブロック図である。
【図６】 図５のディジタル放送受信装置によるフレーム同期処理を示すフロー図である。
【図７】 ＩＳＤＢ信号のキャリアの中に同一内容のデータを格納するＴＭＣＣキャリアが複数本存在する例を示す図である。
【図８】 実施の形態２による多数決判定器の多数決判定処理を説明する説明図である。
【図９】 この発明の実施の形態３によるディジタル放送受信装置の構成を示すブロック図である。
【図１０】 図９のディジタル放送受信装置によるフレーム同期処理を示すフロー図である。
【図１１】 実施の形態３によるパワー変換器及びピーク検出器の同期信号パターンの検出処理を説明する説明図である。
【図１２】 ＤＡＢで使用されているフレームの構成を示す図である。
【図１３】 ＩＳＤＢ信号のキャリアの構成を示す図である。
【図１４】 ＴＭＣＣキャリアの時間方向の構成を示す図である。
【図１５】 フレーム毎にビット反転された同期信号が挿入されている例を説明する説明図である。
【図１６】 ＴＭＣＣキャリア内の同期信号のＤＢＰＳＫ変調方法を説明する説明図である。
【図１７】 ＴＭＣＣキャリア内の同期信号のＤＢＰＳＫ復調方法を説明する説明図である。
【図１８】 ＩＳＤＢのディジタル放送受信装置によるフレーム同期処理動作を示すフロー図である。
【図１９】 ＤＡＢ受信装置がＮＵＬＬシンボルを検出してＮＵＬＬ信号を生成する動作を説明する説明図である。
【図２０】 ＤＡＢ受信装置によるフレーム同期処理動作を示すフロー図である。
【符号の説明】
１ 差動復調器（差動復調手段）、２ １フレーム蓄積器（１フレーム蓄積手段）、３ １フレーム遅延素子（１フレーム遅延手段）、４ ＸＯＲ演算器（ＸＯＲ演算手段）、５ パターン検出器（パターン検出手段）、６ フレーム誤差変換器（フレーム誤差変換手段）、１３ 多数決判定器（多数決判定手段）、１５パワー変換器（パワー変換手段）、１６ ピーク検出器（パターン検出手段）。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital broadcast receiving apparatus and a frame synchronization detection method in ISDB (Integrated Service Digital Broadcasting) which is a domestic digital broadcast.
[0002]
[Prior art]
A signal transmitted by digital broadcasting is generally incorporated and transmitted in a frame that is a group of temporal digital signals. A frame is composed of a set of a plurality of symbols as modulation units. Since these frames and symbols become a processing unit in digital signal processing, detection of frame delimiters and symbol delimiters on the digital broadcast receiving apparatus side is one of important controls along with frequency tuning.
[0003]
Frame delimitation differs depending on the broadcasting system. For example, as a typical example, in a digital audio broadcasting (DAB) which is a European digital audio broadcast, a NULL symbol having no carrier wave is inserted at the beginning of a frame.
[0004]
FIG. 12 is a diagram showing the structure of a frame used in DAB which is European digital audio broadcasting. As described above, in DAB which is European digital audio broadcasting, the NULL symbol is detected by the hardware on the receiving device side to confirm the frame delimiter.
[0005]
On the other hand, in ISDB, which is a domestic digital broadcast in Japan, there is a TMCC carrier (Transmission and Multiplexing Configuration Control Carrier) as one of ISDB signal carriers. This TMCC carrier is a carrier for transmitting frame synchronization information and the like.
[0006]
FIG. 13 is a diagram showing the configuration of the above-described ISDB signal carrier. In the figure, the horizontal axis indicates a carrier number (frequency direction), the vertical axis indicates a symbol number (time direction), CP (Continuous Pilot) indicates a pilot signal, and AC (Auxiliary Channel) indicates additional information. In FIG. 13, TMCC indicates a TMCC carrier. Further, the TMCC carrier shown in FIG. 13 can transmit information of 1 bit per carrier and 1 symbol.
[0007]
FIG. 14 is a diagram showing the configuration of the TMCC carrier in the time direction. As shown in the following, two types of signals that are bit-inverted, that is, synchronization signal 1 and synchronization signal 2, are used as synchronization signals that are synchronization information for frame synchronization set in the TMCC carrier.
Synchronization signal 1: 00110101111101110
Synchronous signal 2: 1100101000010001
Since there is a possibility that a signal having the same bit pattern as that of the above-mentioned sync signal exists in a field other than the sync signal in the TMCC carrier, the sync signals 1 and 2 that are bit-inverted alternately for each frame. It is decided to use.
[0008]
FIG. 15 is an explanatory diagram for explaining an example in which a synchronization signal that is bit-inverted for each frame is inserted. In the figure, the synchronization signals (16-bit configuration) of frame 1, frame 2, and frame 3 are as follows.
Frame 1 synchronization signal: 00110101111110
Synchronization signal of frame 2: 1100101000010001
Synchronization signal of frame 3: 00110101111110
As described above, the synchronization signal set in the TMCC carrier is alternately used after bit inversion for each frame.
[0009]
The TMCC carrier shown in FIG. 14 used in ISDB, which is a domestic digital broadcast, is modulated and transmitted based on a differential two-phase phase modulation method (DBPSK: Differential Binary Phase Shift Keying). In this TMCC carrier, there is a 1-bit differential reference bit immediately before the 16-bit synchronization signal shown in FIG. 14, and 0 or 1 is set therein. The initial value of the differential code can be obtained from the value of the differential reference bit.
[0010]
FIG. 16 is an explanatory diagram for explaining a DBPSK modulation method for a synchronization signal in a TMCC carrier. When the value set in the differential reference bit is 0, a 16-bit synchronization signal can be modulated by the method shown in FIG. That is, if the initial value 0 obtained from the differential reference bit is the same value as the first bit value of the synchronization signal, that is, if the value does not change, the modulation result is 0, and the next bit value If the values are different, that is, if the value changes, the modulation result becomes 1.
[0011]
When the DBPSK modulation is performed on the synchronization signal, the following modulated signal can be obtained. In the following, the first 1 bit is a differential reference bit, and the second and subsequent 16 bits are a synchronization signal.
When the differential reference bit value is 0:
Sync signal
Synchronization signal before modulation: 0 0011010111101110
Synchronized signal after modulation: 0 0010011010110100
Further, when the differential reference bit value is 0, the result of modulating a synchronization signal different from the above example is as follows.
Sync signal
Synchronization signal before modulation: 0 1100101000010001
Synchronization signal after modulation: 0 10000110000011110
[0012]
When the differential reference bit value is 1, the modulation result of the synchronization signal is as follows.
When the differential reference bit value is 1:
Sync signal
Synchronization signal before modulation: 10010011011101110
Synchronization signal after modulation: 1 1101100101001011
When the differential reference bit value is 1, the result of modulating a synchronization signal different from the above example is as follows.
Sync signal
Synchronization signal before modulation: 1 1100100001000001
Synchronized signal after modulation: 1 01111001111100001
[0013]
FIG. 17 is an explanatory diagram for explaining a DBPSK demodulation method for a synchronization signal in a TMCC carrier. When the synchronization signal obtained by the DBPSK modulation shown in FIG. 16 is DBPSK demodulated, the differential reference bit of the differential demodulation is changed for each carrier. That is, one or a plurality of TMCC carriers exist in one OFDM carrier configuration, and the value of the differential reference bit changes according to the carrier number of the carrier, so if the differential reference bit value is 0, If 1, the data before DBPSK demodulation is all inverted, and then the demodulation start bit (that is, the differential reference bit, if inverted, the inverted differential reference bit) is used as a reference, Differential demodulation is performed on subsequent bit strings. In this differential demodulation, similarly to the above-described differential modulation method, 0 is set when the value of the current bit does not change compared to the value of the immediately preceding bit, and 1 is set when it changes.
[0014]
Thus, in the ISDB digital broadcast receiving apparatus, first, in the frame synchronization process, the same bit pattern as the synchronization signal is detected, and the synchronization signal is confirmed for each frame. In this case, after the differential reference bits are calculated, differential demodulation is performed on the subsequent bits, and frame synchronization is established when the differential demodulation results in matching the bit pattern of the synchronization signal. .
[0015]
In the following, the frame synchronization processing in the ISDB digital broadcast receiver will be described in more detail.
FIG. 18 is a flowchart showing a frame synchronization processing operation by the ISDB digital broadcast receiving apparatus. First, a TMCC carrier for one frame is acquired (step ST111). Next, a differential reference bit is calculated in the TMCC carrier (step ST112), and differential two-phase phase demodulation (DBPSK demodulation) is performed on the subsequent bit string in the TMCC carrier based on the value of the differential reference bit. It performs (step ST113).
[0016]
Next, the bit pattern (16-bit bit pattern starting with 0011... Or 1100...) Of the two types of synchronization signals described above is checked (step ST114). If they match, the process flow proceeds to step ST115, and if they do not match, the process flow returns to step ST111.
[0017]
In step ST115, a TMCC carrier for the next one frame is acquired.
Then, a differential reference bit value is calculated from the acquired TMCC carrier for one frame (step ST116), and then DBPSK demodulation of the TMCC carrier is performed (step ST117). Then, the bit pattern of the synchronization signal in the DBPSK demodulation result is inverted, and it is checked whether the bit pattern of the synchronization signal detected in step ST114 matches the inverted pattern (step ST118). That is, since the synchronization signal in the TMCC carrier should be transmitted as a bit pattern that is bit-inverted for each frame, the bit pattern obtained by bit-inversion of the bit pattern of the synchronization signal after DBPSK demodulation detected in step ST114 is step ST117. It should be the bit pattern of the sync signal after DBPSK demodulation obtained in (1). As a result of the check, if it is determined that they match, the process flow proceeds to step ST119, and if they do not match, the process flow returns to step ST111.
[0018]
In step ST119, a frame error is detected from the position of the synchronization signal, the frame error is corrected for the acquired TMCC carrier for one frame, and the frame synchronization processing is thereby completed (step ST120).
[0019]
By the way, in DAB which is European digital audio broadcasting, as shown in FIG. 12, a NULL symbol having no carrier wave is inserted at the head of the frame, so that this NULL symbol can be easily obtained by using hardware on the receiving apparatus side. Can be detected.
[0020]
FIG. 19 is an explanatory diagram for explaining an operation in which a DAB receiving apparatus detects a NULL symbol and generates a NULL signal, and FIG. 20 is a flowchart showing a frame synchronization processing operation by the DAB receiving apparatus. In the frame synchronization processing by the DAB receiving apparatus, first, the DAB receiving apparatus detects the fall of the NULL signal corresponding to the NULL symbol (step ST130). Then, an error detection / correction operation of the digital signal received from the detected falling position is performed (step ST131).
[0021]
Thereby, the frame synchronization on the DAB receiving apparatus side is completed (step ST132). As described above, since no carrier wave is present in the head symbol of a DAB frame, a NULL symbol can be easily detected by hardware in the DAB receiver, and the time required for frame synchronization on the DAB receiver side. Hardly takes.
[0022]
On the other hand, in the digital broadcast receiving apparatus used for ISDB which is a domestic digital broadcast, as shown in the flowchart of FIG. 18, the ISDB signal received via an antenna or the like is DBPSK demodulated and DBPSK demodulated for each frame. A process for comparing the result and the bit pattern of the synchronization signal to detect the synchronization signal is required.
[0023]
[Problems to be solved by the invention]
Since the conventional digital broadcast receiving apparatus and the frame synchronization detection method are configured as described above, when performing frame synchronization of the received ISDB signal, each differential reference bit of two consecutive frames of the TMCC carrier is calculated, After performing DBPSK demodulation on the bit string indicating the synchronization information following the differential reference bit, it is necessary to detect the presence or absence of the same bit pattern as the synchronization signal for each TMCC carrier. There was a problem that it took.
[0024]
In order to shorten the start-up time, a method of detecting the presence or absence of the same bit pattern as the synchronization signal for each TMCC carrier before performing differential demodulation (DBPSK demodulation) is conceivable.
However, by performing differential demodulation, the frequency shift in the frequency direction is corrected for each symbol.
Therefore, if the presence of the same bit pattern as the synchronization signal is determined before differential demodulation, errors due to detuning accumulate as the carrier frequency of the TMCC carrier is slightly detuned as one frame is conveyed. The possibility that an error will occur in the data in the latter half of the frame becomes very high, and there is a problem that it is impossible to accurately determine whether the same bit pattern as that of the synchronization signal is coincident.
[0025]
The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a digital broadcast receiving apparatus that can easily establish frame synchronization of a received ISDB signal and can be quickly activated.
[0026]
[Means for Solving the Problems]
The digital broadcast receiving apparatus according to the present invention sets the value of each bit in the TMCC carrier to the bit immediately before the TMCC carrier subjected to DBPSK modulation from the received ISDB signal regardless of the value of the differential reference bit. A differential demodulating means for differentially demodulating as 0 if not changing and 1 if changing, 1 frame accumulating means for storing one frame of TMCC carrier obtained from the differential demodulating means, Performs an exclusive OR operation between one frame delay means for delaying the TMCC carrier in one frame storage means by one frame and two frames of the TMCC carrier obtained from the one frame storage means and the one frame delay means. XOR operation means and the operation result of the XOR operation means are searched for the synchronization information contained in the TMCC carrier. Pattern detection means for detecting the position of the constant bit pattern, and frame error conversion means for outputting a shift of the ISDB signal to the head position of the frame as a frame error based on the detection result output from the pattern detection means. Is.
[0027]
In the digital broadcast receiving apparatus according to the present invention, the predetermined bit pattern of the synchronization information included in the TMCC carrier detected by the pattern detection means is “1111111111111111” when the synchronization information in the TMCC carrier is 16 bits, All the bits other than the synchronization information are 0.
[0028]
The digital broadcast receiving apparatus according to the present invention corresponds to each of the plurality of TMCC carriers when there are a plurality of TMCC carriers in which the same data contents are to be stored among the TMCC carriers obtained from the differential demodulation means. A majority decision judging means for judging the appearance frequency of the value of the bit and generating a TMCC carrier storing the value having the highest appearance frequency, and one frame accumulating means for obtaining one frame of the TMCC carrier obtained from the majority decision judging means; To store.
[0029]
The digital broadcast receiving apparatus according to the present invention comprises power conversion means for performing addition for the number of bits constituting the synchronization information for each bit pattern with respect to the bit pattern of the operation result obtained from the XOR operation means, The pattern detection means detects the position of the bit pattern for which the conversion means has calculated the maximum addition value as the position of the predetermined bit pattern of the synchronization information included in the TMCC carrier.
[0030]
In the frame synchronization detection method according to the present invention, the value of each bit in the TMCC carrier is changed to the immediately preceding bit regardless of the value of the differential reference bit for the DBPSK modulated TMCC carrier from the received ISDB signal. A differential demodulation step that differentially demodulates as 0 when there is no change compared to the value of, and an exclusive OR operation between the two frames of the TMCC carrier obtained at the differential demodulation step. Based on the XOR calculation step to be executed, the calculation result in this XOR calculation step, the pattern detection step for detecting the position of the predetermined bit pattern of the synchronization information included in the TMCC carrier, and the detection result in this pattern detection step, A frame that outputs the deviation of the ISDB signal to the beginning of the frame as a frame error Those comprising a chromatography beam error converting step.
[0031]
In the frame synchronization detection method according to the present invention, the predetermined bit pattern of the synchronization information included in the TMCC carrier detected in the pattern detection step is “1111111111111111” when the synchronization information in the TMCC carrier is 16 bits, The bits other than the synchronization information are all 0.
[0032]
The frame synchronization detection method according to the present invention corresponds to each of a plurality of TMCC carriers when there are a plurality of TMCC carriers in which the same data contents are to be stored among the TMCC carriers obtained in the differential demodulation step. 2 frames obtained in the differential demodulation step in the XOR operation step, comprising the majority decision step of determining the appearance frequency of the value of the bit to be generated and generating a TMCC carrier storing the value having the highest appearance frequency The exclusive OR operation between the TMCC carriers is executed.
[0033]
The frame synchronization detection method according to the present invention includes a power conversion step in which addition for the number of bits constituting the synchronization information is shifted for each bit with respect to the bit pattern of the operation result obtained in the XOR operation step, In the pattern detection step, the position of the bit pattern for which the maximum addition value has been calculated in the power conversion step is detected as the position of the predetermined bit pattern of the synchronization information included in the TMCC carrier.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below.
Embodiment 1 FIG.
1 is a block diagram showing a configuration of a digital broadcast receiving apparatus according to Embodiment 1 of the present invention. In the figure, 1 is a differential demodulator (differential demodulation means) for differentially demodulating a DBCCK modulated TMCC carrier, and the value of each bit in the TMCC carrier regardless of the value of the differential reference bit of the TMCC carrier. Differential demodulation is performed with 0 when there is no change compared to the value of the bit immediately before and 1 when there is a change. 2 is a 1 frame accumulator (1 frame accumulating means) for storing one frame of the TMCC carrier obtained from the differential demodulator 1. 3 is a 1 frame delay for delaying the TMCC carrier in the 1 frame accumulator 2 by one frame. Element (1 frame delay means), 4 is an XOR operator (XOR operation) that performs an XOR operation (exclusive OR) between 2 frames of TMCC carriers obtained from the 1 frame accumulator 2 and 1 frame delay element 3 Means) 5 is a pattern detector (pattern detection means) for searching the calculation result of the XOR operator 4 and detecting the position of a predetermined bit pattern of the synchronization information included in the TMCC carrier, and 6 is output from the pattern detector 5. Based on the detected result, a frame error converter (frame error converter) that outputs a deviation of the ISDB signal to the head position of the frame as a frame error. It is a non-error conversion means).
[0035]
Next, the operation will be described.
FIG. 2 is a flowchart showing frame synchronization processing by the digital broadcast receiving apparatus of FIG. 1, and the operation will be described along this flow.
First, an ISDB signal transmitted from a digital broadcast transmission apparatus is received via an antenna. Next, the ISDB signal is converted to an intermediate frequency by a tuner and then converted to digital data by an A / D converter. Further, it is separated into a real part (in-phase component: In phase) and an imaginary part (quadrature component: Quadrature phase) by an I / Q separator, and fast Fourier transform processing is performed by an FFT processor. The configuration up to this point is the same as that of the DAB receiver and a general digital broadcast receiver, and illustration and detailed description thereof are omitted.
[0036]
Next, the digital data subjected to the fast Fourier transform processing by the FFT processor is divided and extracted by a carrier divider into a main signal carrier, a pilot carrier, an additional information carrier, a TMCC carrier as a control signal carrier, and the like. The main signal carrier is output to the demodulating circuit at the subsequent stage, and since this is also the same as the processing of a general digital broadcast receiving apparatus, the illustration and detailed description are omitted here.
[0037]
The TMCC carrier divided and extracted by the carrier divider is differentially demodulated by the differential demodulator 1 (step ST1, differential demodulation step). Conventionally, when differentially demodulating a DBPSK-modulated synchronization signal as shown in FIG. 14, as described above, one or more TMCC carriers exist in one OFDM carrier configuration, and the carrier numbers possessed by them exist. Therefore, if the differential reference bit value is 0, the differential reference bit value is 1, if the differential reference bit value is 1, the data before DBPSK demodulation is inverted. Differential demodulation is performed on the subsequent bit string based on the value of the bit at which demodulation is started.
On the other hand, in the digital broadcast receiver according to the first embodiment, the time required for differential demodulation is shortened by differential demodulation regardless of the value of the differential reference bit (that is, without detecting the differential reference bit). is doing.
[0038]
FIG. 3 is an explanatory diagram for explaining a method for differentially demodulating a synchronization signal in a TMCC carrier by the digital broadcast receiving apparatus according to the first embodiment. As shown in the figure, regardless of the value of the differential reference bit, the differential demodulator 1 changes to 0 if it does not change with respect to the immediately preceding bit with respect to the value of the first bit of the TMCC carrier. In this case, differential demodulation is performed as 1. This may cause an error in the value of the differential reference bit as described below, but the operation of detecting the differential reference bit can be omitted.
[0039]
In the differential demodulation process described above, the differential demodulator 1 outputs the value as it is without detecting the differential reference bit. At this time, this corresponds to a state where differential demodulation is not performed on the first bit of demodulation. Therefore, in the example described in the upper part of FIG. 3, the value of the first bit of demodulation matches the differential reference bit, and the bit string obtained by the differential demodulation is correctly demodulated as the value 0 of the differential reference bit. In the example shown in the lower part of FIG. 3, since the first bit of demodulation does not match the differential reference bit, and the value before and after demodulation is different, only the value of the first bit of demodulation is incorrect. As described above, in the differential demodulation according to the first embodiment, there is a possibility that an error is included in the value of the differential reference bit, but since it is only 1 bit, it has a great influence on the frame synchronization of the TMCC carrier. Never give.
[0040]
As described above, the TMCC carrier differentially demodulated by the differential demodulator 1 is stored in the one frame accumulator 2. One frame of the TMCC carrier stored in the one-frame storage 2 is delayed by one frame in the one-frame delay element 3. As a result, TMCC carriers for two consecutive frames are obtained from the TMCC carrier output from the one-frame delay element 3 and the TMCC carrier in the one-frame accumulator 2 (step ST2, step ST3).
[0041]
The TMCC carrier pattern for two frames after differential demodulation processing is shown below. However, a differential “111” is added as a format identification code after a 16-bit synchronization signal used for frame synchronization.
Before differential encoding

The result of performing the XOR operation between the two frames before differential encoding is defined as a signal pattern after differential encoding.
[0042]
FIG. 4 is an explanatory diagram showing the XOR operation of TMCC carriers for two frames before differential encoding. As shown in the figure, the XOR operator 4 is between the signal pattern of the TMCC carrier in the one-frame accumulator 2 and the signal pattern of the TMCC carrier delayed from the one-frame delay element 3 by one frame. XOR operation is performed (step ST4, XOR operation step). As described above, in the XOR operation result, the fixed pattern “1111111111111111” appears in the synchronization signal portion in the signal of the TMCC carrier. The parts other than the synchronization signal, for example, the differential reference bit, the format identification code, the TMCC information, and the parity bit all have the value 0.
[0043]
Then, the pattern detector 5 detects where the position of the fixed pattern “1111111111111111” of the XOR operation result is in the TMCC carrier, and outputs the detection result to the frame error converter 6 (step ST5, pattern detection step). .
[0044]
Based on the detection result output from the pattern detector 5, that is, the detected position information of the fixed pattern “1111111111111111”, the number of symbols from the position considered to be the head of the frame in the digital broadcast receiving apparatus to the true frame head position The frame error converter 6 calculates whether the difference is a frame error and feeds it back to a synchronization processing unit (not shown) (step ST6, frame error conversion step). Therefore, by searching the position of the fixed pattern “1111111111111111” in the result obtained by the XOR operation, the magnitude of the frame synchronization error can be obtained. That is, the head of the detected fixed pattern “1111111111111111” corresponds to the second symbol of the frame (the bit position next to the differential reference bit).
[0045]
As described above, according to the first embodiment, the differential demodulator 1 compares the value of each bit in the TMCC carrier with the value of the immediately preceding bit regardless of the value of the differential reference bit of the TMCC carrier. If the change does not change, it is differentially demodulated as 0, and when it changes, the XOR operator 4 performs an XOR operation between the two frames of the TMCC carrier obtained from the one frame accumulator 2 and the one frame delay element 3. The pattern detector 5 searches the XOR calculation result, detects the presence or absence of the fixed pattern “1111111111111111”, knows the position of the synchronization signal that is the synchronization information in the TMCC carrier, and performs the frame synchronization processing. Thus, the differential reference bit calculation operation is omitted in the differential demodulation process, and after differential demodulation, the bit pattern of the synchronization signal Therefore, the time required for frame synchronization processing can be shortened, and the digital broadcast receiving apparatus can be quickly operated. Can be launched.
[0046]
Embodiment 2. FIG.
FIG. 5 is a block diagram showing the configuration of a digital broadcast receiving apparatus according to Embodiment 2 of the present invention. In the figure, reference numeral 13 denotes a majority decision unit (majority decision unit). Among the TMCC carriers obtained from the differential demodulator 1, when there are a plurality of TMCC carriers in which the same data contents are to be stored, these plurality of TMCC carriers are present. A value having the highest appearance frequency in the bits corresponding to each of the carriers is determined to generate a TMCC carrier subjected to majority determination. In addition, the same code | symbol is attached | subjected to the same component as FIG. 1, and the overlapping description is abbreviate | omitted.
[0047]
Next, the operation will be described.
FIG. 6 is a flowchart showing frame synchronization processing by the digital broadcast receiving apparatus of FIG. 5, and the operation will be described along this flow.
First, the operation until the digital data of the ISDB signal subjected to the fast Fourier transform processing is divided into a main signal carrier, a pilot carrier, an additional information carrier, a TMCC carrier which is a control signal carrier, and the like is extracted by the carrier divider. Since it is the same as that of Embodiment 1, the overlapping description is omitted.
[0048]
The TMCC carrier divided and extracted by the carrier divider is differentially demodulated by the differential demodulator 1 (step ST1a, differential demodulation step). This differential demodulation processing also uses the value of the first bit of the TMCC carrier as a reference regardless of the value of the differential reference bit (that is, without detecting the differential reference bit) shown in the first embodiment. If the method of differential demodulation is applied as 0 when there is no change with respect to the immediately preceding bit and 1 when it is changed, the time required for differential demodulation processing can be shortened.
[0049]
Further, in DBPSK modulation of an ISDB signal, data having the same content may be stored and transported in a plurality of TMCC carriers depending on the number of modes. As described above, by storing data of the same content in a plurality of TMCC carriers, the data content stored in the TMCC carrier corresponding to the frequency of the carrier having a bad reception state is received from the TMCC carriers corresponding to other frequencies. To be able to.
[0050]
FIG. 7 is a diagram showing an example in which there are a plurality of TMCC carriers that store data of the same content in the carrier of the ISDB signal. In the example shown in the figure, in the case of mode 1, there are five TMCC carriers (TMCC1 to TMCC5) that store data of the same content. All of these TMCC carriers should ideally have the same data content. However, depending on the communication environment where the receiving device is installed, when a failure occurs in receiving a carrier wave of a certain frequency, part of the data content stored in any of the TMCC carriers (TMCC1 to TMCC5) changes. there's a possibility that. If the data stored in the TMCC carrier can be determined to be completely in error due to reception failure or the like, the process can be shifted to the process of receiving the same data from the TMCC carrier corresponding to another frequency. As in the illustrated example, if a part of data changes, it may not be possible to determine which TMCC carrier has the true data content.
[0051]
Therefore, in the second embodiment, the majority decision determiner 13 determines the appearance frequency of the values of the bits corresponding to each of the TMCC carriers (TMCC1 to TMCC5), and stores the value having the highest appearance frequency. (Step ST2a, majority decision step).
FIG. 8 is an explanatory diagram for explaining the majority decision process of the majority decision unit according to the second embodiment. In the example shown in the figure, TMCC carriers (TMCC1 to TMCC5) that store data of the same content have different values of the differential reference bit and the first symbol number of the synchronization signal depending on the communication state on the receiving side described above. Different values are received depending on the carrier (depending on the carrier frequency).
On the other hand, the majority decision determiner 13 counts the appearance frequency of the value of each bit having the same symbol number of each TMCC carrier (TMCC1 to TMCC5) along the carrier number (frequency direction of the carrier wave). The majority decision unit 13 determines the most likely value obtained as a result of the counting as the most probable value for the bit, and generates a TMCC carrier for storing this value.
[0052]
As described above, the TMCC carrier subjected to the majority decision by the majority decision determiner 13 is stored in the one frame accumulator 2. One frame of the TMCC carrier stored in the one-frame storage 2 is delayed by one frame in the one-frame delay element 3. As a result, TMCC carriers for two consecutive frames are obtained from the TMCC carrier output from the one-frame delay element 3 and the TMCC carrier in the one-frame accumulator 2 (step ST3a, step ST4a).
[0053]
Thereafter, the XOR operation processing (step ST5a, XOR operation step) for the bit pattern of the TMCC carrier for two frames after the differential demodulation processing by the XOR operator 4, the position of the fixed pattern “1111111111111111” of the XOR operation result is the TMCC carrier. The pattern detector 5 detects where in the frame (step ST6a, pattern detection step). The frame error converter 6 calculates the frame error based on the detection result output from the pattern detector 5, and performs synchronization processing. The feedback to the unit (not shown) (step ST6, frame error conversion step) is the same as that described in the first embodiment.
[0054]
As described above, according to the second embodiment, when there are a plurality of TMCC carriers in which the same data contents are stored among the differentially demodulated TMCC carriers, each of the plurality of TMCC carriers is supported. Since the TMCC carrier storing the value having the highest appearance frequency as a true TMCC carrier is generated by determining the appearance frequency of the value of the bit to be stored, it is stored in the TMCC carrier even in a noisy reception environment with a lot of noise. Data can be received with high accuracy. Thereby, the process of detecting the bit pattern of the synchronization signal can be performed accurately, and the frame error can be detected with high accuracy.
[0055]
Embodiment 3 FIG.
FIG. 9 is a block diagram showing a configuration of a digital broadcast receiving apparatus according to Embodiment 3 of the present invention. In the figure, reference numeral 15 denotes a power converter (power conversion means), which adds the number of bits constituting the synchronization information to the bit pattern of the operation result obtained by the XOR operator 4 while shifting by one bit. The addition result is sequentially output to the peak detector 16. Reference numeral 16 denotes a peak detector (pattern detection means) that detects the position in the TMCC carrier corresponding to the maximum addition value from the addition results from the power converter 15 and outputs the detected position to the frame error converter 6. In addition, the same code | symbol is attached | subjected to the same component as FIG. 1, and the overlapping description is abbreviate | omitted.
[0056]
Next, the operation will be described.
FIG. 10 is a flowchart showing frame synchronization processing by the digital broadcast receiving apparatus of FIG. 9, and the operation will be described along this flow.
First, the digital data of the ISDB signal subjected to the fast Fourier transform processing is divided into a main signal carrier, a pilot carrier, an additional information carrier, a TMCC carrier as a control signal carrier, and the like by a carrier divider. The TMCC carrier thus extracted is differentially demodulated by the differential demodulator 1 (step ST1b, differential demodulation step). This differential demodulation processing also uses the value of the first bit of the TMCC carrier as a reference regardless of the value of the differential reference bit (that is, without detecting the differential reference bit) shown in the first embodiment. If the method of differential demodulation is applied as 0 when there is no change with respect to the immediately preceding bit and 1 when it is changed, the time required for differential demodulation processing can be shortened.
[0057]
The differentially demodulated TMCC carrier is stored in one frame accumulator 2. One frame of the TMCC carrier stored in the one-frame storage 2 is delayed by one frame in the one-frame delay element 3. As a result, TMCC carriers for two consecutive frames are obtained from the TMCC carrier output from the one-frame delay element 3 and the TMCC carrier in the one-frame accumulator 2 (step ST2b, step ST3b).
[0058]
Thereafter, an XOR operation process is performed on the bit pattern of the TMCC carrier for two frames after the differential demodulation process by the XOR operator 4 (step ST4b, XOR operation step). The TMCC carrier having the XOR operation result fixed pattern “1111111111111111” obtained as a result is output to the power converter 15.
[0059]
In the power converter 15, the bit pattern of the calculation result obtained by the XOR calculator 4 is added by shifting the number of bits constituting the synchronization signal by one bit (step ST5b, power conversion step).
FIG. 11 is an explanatory diagram for explaining the detection process of the synchronization signal pattern of the power converter and the peak detector according to the third embodiment. As shown in the upper part of FIG. 11, when the power converter 15 receives the TMCC carrier from the XOR operator 4, the power converter 15 adds 16 bits to the bit string arranged in the time direction of the TMCC carrier (the number of bits constituting the synchronization signal). (Addition of minutes) is performed while shifting by 1 bit. Since the XOR operator 4 obtains 16-bit “1111111111111111” as a fixed pattern corresponding to the synchronization signal, the 16-bit addition by the power converter 15 described above can add all the logical values 1 included in the fixed pattern. At the position, the added value is 16 in decimal, and this position corresponds to the position of the fixed pattern of the synchronization signal in the TMCC carrier.
[0060]
In the upper part of FIG. 11, when the start point in the bit string of 16-bit addition by the power converter 15 is shifted, the addition value becomes “15”, “14”, “13”, “12”, “11”, and the like. The maximum value cannot be obtained. The added value by the power converter 15 is sequentially output to the peak detector 16.
[0061]
The peak detector 16 obtains the relationship between the time when each bit is sent as shown in the lower part of FIG. 11 and the addition result from the addition value from the power converter 15, and the position of the bit pattern where the maximum addition value is calculated. Is detected as the position of the fixed pattern of the synchronization signal (step ST6b, pattern detection step). As can be seen from the lower graph of FIG. 11, the result of 16-bit addition performed on the bit string arranged in the time direction of the TMCC carrier is the highest addition value 16 including the first bit of the synchronization signal, which is the peak. In the case of 16-bit addition using another bit position as the starting point of addition, an addition result of less than 16 is obtained. The peak detector 16 calculates a time corresponding to the start point in the 16-bit addition bit string that is the peak, and outputs the time to the frame error converter 6.
[0062]
In the frame error converter 6, based on the output result from the peak detector 16, that is, the time corresponding to the first bit of the fixed pattern “1111111111111111”, from the position considered as the head of the frame in the digital broadcast receiving apparatus. Then, how many symbols the true frame head position is shifted is calculated as a frame error and fed back to a synchronization processing unit (not shown) (step ST7b, frame error conversion step). Therefore, by searching the position of the fixed pattern “1111111111111111” in the result obtained by the XOR operation, the magnitude of the frame synchronization error can be obtained. That is, the head of the detected fixed pattern “1111111111111111” corresponds to the second symbol of the frame (the bit position next to the differential reference bit).
[0063]
As described above, according to the third embodiment, the TMCC carrier bit pattern obtained by the XOR operation is added by shifting the number of bits constituting the synchronization information for each bit, and the maximum addition is performed. Since the position of the bit pattern for which the value is calculated is detected as the position of the predetermined bit pattern of the synchronization information included in the TMCC carrier, the processing for detecting the bit pattern of the synchronization signal can be performed accurately, and the frame error is accurately detected. It can be detected well.
[0064]
Note that the configuration of the third embodiment may be applied to the second embodiment, whereby the effects of both embodiments can be obtained together.
[0065]
【The invention's effect】
As described above, according to the present invention, for the DBCCK modulated TMCC carrier from the received ISDB signal, the value of each bit in the TMCC carrier is set to the immediately preceding value regardless of the value of the differential reference bit. If it does not change compared to the bit value, it is differentially demodulated as 0, and if it is varied, differential demodulation is performed, an exclusive OR operation between the TMCC carriers of the differentially demodulated 2 frames is executed, and the operation result is searched. Thus, the position of the predetermined bit pattern of the synchronization information included in the TMCC carrier is detected, and based on this detection result, the deviation of the ISDB signal up to the head position of the frame is output as a frame error. The operation of calculating the dynamic reference bit is omitted, and after differential demodulation, the comparison process of whether or not it matches the bit pattern of the synchronization signal is continuously performed. That since the two need not be performed for each of the TMCC carrier, it is possible to shorten the time required for frame synchronization processing, there is an effect that the digital broadcast receiving apparatus can be started up quickly.
[0066]
According to this invention, when the synchronization information in the TMCC carrier is 16 bits, a pattern corresponding to the synchronization information is “1111111111111111,” and a predetermined bit pattern in which all bits other than the synchronization information are all 0 is detected. After the demodulation, it is not necessary to perform the comparison process whether or not it matches the bit pattern of the synchronization signal for each of the two consecutive TMCC carriers, so that the time required for the frame synchronization process can be shortened. Thus, there is an effect that the digital broadcast receiving apparatus can be started up quickly.
[0067]
According to the present invention, when there are a plurality of TMCC carriers in which the same data contents are to be stored among the differentially demodulated TMCC carriers, the appearance frequency of the values of the bits corresponding to each of the plurality of TMCC carriers The TMCC carrier storing the value having the highest appearance frequency is generated, this is accumulated for two frames, and the exclusive OR operation between these TMCC carriers is executed. Even in the environment, there is an effect that the data stored in the TMCC carrier can be received with high accuracy. Thereby, it is possible to accurately perform the process of detecting the bit pattern of the synchronization signal, and to detect the frame error with high accuracy.
[0068]
According to the present invention, the addition of the number of bits constituting the synchronization information is shifted for each bit with respect to the bit pattern of the XOR operation result, and the position of the bit pattern for which the maximum addition value is calculated is set in the TMCC carrier. Since it is detected as the position of the predetermined bit pattern of the included synchronization information, the process of detecting the bit pattern of the synchronization signal can be performed accurately, and the frame error can be detected with high accuracy.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a digital broadcast receiving apparatus according to Embodiment 1 of the present invention.
FIG. 2 is a flowchart showing frame synchronization processing by the digital broadcast receiving apparatus of FIG. 1;
FIG. 3 is an explanatory diagram for explaining a differential demodulation method for a synchronization signal in a TMCC carrier by the digital broadcast receiving apparatus according to the first embodiment;
FIG. 4 is an explanatory diagram illustrating an XOR operation of TMCC carriers for two frames before differential encoding.
FIG. 5 is a block diagram showing a configuration of a digital broadcast receiving apparatus according to Embodiment 2 of the present invention.
6 is a flowchart showing frame synchronization processing by the digital broadcast receiving apparatus of FIG. 5. FIG.
FIG. 7 is a diagram illustrating an example in which there are a plurality of TMCC carriers storing data of the same content among carriers of an ISDB signal.
FIG. 8 is an explanatory diagram for explaining majority decision processing of a majority decision determiner according to a second embodiment.
FIG. 9 is a block diagram showing a configuration of a digital broadcast receiving apparatus according to Embodiment 3 of the present invention.
10 is a flowchart showing frame synchronization processing by the digital broadcast receiving apparatus of FIG. 9. FIG.
FIG. 11 is an explanatory diagram for explaining a detection process of a synchronization signal pattern of a power converter and a peak detector according to a third embodiment.
FIG. 12 is a diagram showing the structure of a frame used in DAB.
FIG. 13 is a diagram illustrating a carrier configuration of an ISDB signal.
FIG. 14 is a diagram illustrating a configuration in a time direction of a TMCC carrier.
FIG. 15 is an explanatory diagram illustrating an example in which a synchronization signal that is bit-inverted for each frame is inserted.
FIG. 16 is an explanatory diagram for explaining a DBPSK modulation method of a synchronization signal in a TMCC carrier.
FIG. 17 is an explanatory diagram illustrating a DBPSK demodulation method for a synchronization signal in a TMCC carrier.
FIG. 18 is a flowchart showing a frame synchronization processing operation by the ISDB digital broadcast receiver.
FIG. 19 is an explanatory diagram illustrating an operation in which a DAB receiving apparatus detects a NULL symbol and generates a NULL signal.
FIG. 20 is a flowchart showing a frame synchronization processing operation by the DAB receiver.
[Explanation of symbols]
1 differential demodulator (differential demodulating means), 2 1 frame accumulator (1 frame accumulating means), 3 1 frame delay element (1 frame delay means), 4 XOR computing unit (XOR computing means), 5 pattern detector (Pattern detection means), 6 frame error converter (frame error conversion means), 13 majority decision determiner (majority decision decision means), 15 power converter (power conversion means), 16 peak detector (pattern detection means).

Claims (8)

When the DBCCK modulated TMCC carrier from the received ISDB signal is not changed by comparing the value of each bit in the TMCC carrier with the value of the immediately preceding bit regardless of the value of the differential reference bit Is a differential demodulating means for differentially demodulating as 0 and 1 when changing,
1-frame storage means for storing 1-frame TMCC carrier obtained from the differential demodulation means;
1-frame delay means for delaying the TMCC carrier in the 1-frame storage means by one frame;
XOR operation means for performing an exclusive OR operation between the 1-frame storage means and the 2-frame TMCC carrier obtained from the 1-frame delay means;
Pattern detection means for searching for a calculation result of the XOR operation means and detecting a position of a predetermined bit pattern of the synchronization information included in the TMCC carrier;
A digital broadcast receiving apparatus comprising: frame error conversion means for outputting a deviation of the ISDB signal to the head position of the frame as a frame error based on the detection result output from the pattern detection means. The predetermined bit pattern of the synchronization information included in the TMCC carrier detected by the pattern detection means is “1111111111111111” when the synchronization information in the TMCC carrier is 16 bits, and the bits other than the synchronization information in the TMCC carrier are The digital broadcast receiver according to claim 1, wherein all are zero. Among the TMCC carriers obtained from the differential demodulation means, when there are a plurality of TMCC carriers in which the same data contents are to be stored, the frequency of occurrence of the value of the bit corresponding to each of the plurality of TMCC carriers is determined. A majority decision determining means for generating a TMCC carrier storing a value having the highest appearance frequency,
2. The digital broadcast receiving apparatus according to claim 1, wherein the one-frame storage means stores one frame of the TMCC carrier obtained from the majority decision judging means. Power conversion means for performing addition for the number of bits constituting the synchronization information for each bit pattern with respect to the bit pattern of the operation result obtained from the XOR operation means,
The pattern detection means detects the position of the bit pattern at which the power conversion means has calculated the maximum added value as the position of the predetermined bit pattern of the synchronization information included in the TMCC carrier. The digital broadcast receiver according to claim 1. When the DBCCK modulated TMCC carrier from the received ISDB signal is not changed by comparing the value of each bit in the TMCC carrier with the value of the immediately preceding bit regardless of the value of the differential reference bit Is a differential demodulation step that differentially demodulates as 0 and 1 when changing,
An XOR operation step for performing an exclusive OR operation between the two frames of the TMCC carrier obtained in the differential demodulation step;
A pattern detection step of searching for a calculation result in the XOR calculation step and detecting a position of a predetermined bit pattern of the synchronization information included in the TMCC carrier;
A frame synchronization detection method comprising: a frame error conversion step of outputting, as a frame error, a shift of the ISDB signal to the start position of the frame based on a detection result in the pattern detection step. The predetermined bit pattern of the synchronization information included in the TMCC carrier detected in the pattern detection step is “1111111111111111” when the synchronization information in the TMCC carrier is 16 bits, and the bits other than the synchronization information in the TMCC carrier. 6. The frame synchronization detection method according to claim 5, wherein all are zero. When there are a plurality of TMCC carriers in which the same data content should be stored among the TMCC carriers obtained in the differential demodulation step, the frequency of occurrence of the value of the bit corresponding to each of the plurality of TMCC carriers is determined. And a majority decision step for generating a TMCC carrier storing a value having the highest appearance frequency,
6. The frame synchronization detection method according to claim 5, wherein, in the XOR operation step, an exclusive OR operation between the two frames of the TMCC carrier obtained in the differential demodulation step is executed. A power conversion step in which addition of the number of bits constituting the synchronization information is shifted for each bit with respect to the bit pattern of the operation result obtained in the XOR operation step
6. The pattern detection step detects the position of the bit pattern for which the maximum addition value has been calculated in the power conversion step as the position of a predetermined bit pattern of synchronization information included in the TMCC carrier. The frame synchronization detection method according to claim 1.

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