JP2002217883A - Digital broadcasting receiver and method for detecting frame synchronization - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of the starting not being speedy, because it takes time to process the frame synchronization of a received ISDB signal. SOLUTION: Values of respective bits are compared with the values of bits respectively prior to them, irrespective of the difference reference bit of a TMCC carrier. Then, the TMCC carrier is subjected to differential modulation with 0, when the value is not changed and with 1, when the value is changed. Then, the position of a synchronization pattern, included in an XOR arithmetic, result between TMCC carriers given differential modulation is detected to output the leading position of the frame of an ISDB signal as a frame error, based on it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to ISDB (Integrated Service) for domestic digital broadcasting.
The present invention relates to a digital broadcast receiving apparatus and a frame synchronization detection method in ce Digital Broadcasting.

[0002]

2. Description of the Related Art Generally, a signal transmitted by digital broadcasting is transmitted by being incorporated in a frame, which is a set of digital signals in time. Further, the frame is constituted by a plurality of symbols which are units of modulation.
Since these frames and symbols are processing units in digital signal processing, the digital broadcast receiving device side
Detecting a frame break or a symbol break is one of the important controls together with frequency tuning.

[0003] The division of a frame differs depending on the broadcasting system. For example, a typical example is DAB (Digital Audio) which is a European digital audio broadcast.
In Broadcasting, a NULL symbol without any carrier is inserted at the beginning of the frame.

[0004] FIG. 12 shows a European digital audio broadcast, D.
FIG. 3 is a diagram illustrating a configuration of a frame used in AB.
As described above, in DAB which is European digital audio broadcasting, the NULL symbol is detected by the hardware on the receiving device side to confirm a frame break.

On the other hand, Japanese domestic digital broadcasting I
In SDB, one of the carriers of the ISDB signal is TM
CC carrier (Transmission and M
multiplexing Configuration
Control Carrier). This TM
The CC carrier is a carrier for transmitting frame synchronization information and the like.

FIG. 13 is a diagram showing a configuration of a carrier of the above-mentioned ISDB signal. In the figure, the horizontal axis is the carrier number (frequency direction), the vertical axis is the symbol number (time direction),
CP (Continuous Pilot) is a pilot signal, AC (Auxiliary Channel)
Indicates additional information. In FIG. 13, TM
CC indicates a TMCC carrier. Further, T shown in FIG.
The MCC carrier can transmit one bit of information per carrier and per symbol.

FIG. 14 is a diagram showing a configuration of a TMCC carrier in a time direction. The synchronization signal, which is synchronization information for frame synchronization set in the TMCC carrier, includes two types of signals that are bit-inverted from each other, as shown below.
That is, the synchronization signal 1 and the synchronization signal 2 are used. Synchronization signal 1: 00110110111101110 Synchronization signal 2: 1100101000010001 In a field other than the synchronization signal in the TMCC carrier, there is a possibility that a signal having the same bit pattern as that of the above-mentioned synchronization signal may be present. It is determined that the inverted synchronization signals 1 and 2 are used alternately.

FIG. 15 is an explanatory diagram for explaining an example in which a bit-inverted synchronization signal is inserted for each frame. In the figure, the respective synchronization signals (16-bit configuration) of frame 1, frame 2 and frame 3 are as follows. Synchronization signal of frame 1: 0011011111011
10 Synchronization signal of frame 2: 11001010000100
01 Synchronization signal of frame 3: 0011011111011
10 As described above, as the synchronization signal set in the TMCC carrier, a bit-inverted one for each frame is used alternately.

The TMCC carrier shown in FIG. 14 used in ISDB which is a domestic digital broadcast uses a differential two-phase modulation system (DBPSK: Differential).
Binary Phase Shift Keyin
g) and transmitted. In this TMCC carrier, there is one differential reference bit immediately before the 16-bit synchronization signal shown in FIG. 14, and 0 or 1 is set therein. Then, the initial value of the differential code can be obtained from the value of the differential reference bit.

FIG. 16 is an explanatory diagram for explaining a DBPSK modulation method of a synchronization signal in a TMCC carrier. When the value set in the differential reference bit is 0, a 16-bit synchronization signal can be modulated by the method shown in FIG.
That is, if the initial value 0 obtained from the differential reference bit is the same value as the first bit value of the synchronization signal, that is, if the value does not change, the modulation result becomes 0, and the next bit value If the value is different, that is, if the value changes, the modulation result is 1.

When the DBPSK modulation is performed on the synchronization signal, the following modulated synchronization signal can be obtained. In the following, the first one bit is a differential reference bit, and the second and subsequent 16 bits are a synchronization signal. When the differential reference bit value is 0: Synchronization signal Synchronization signal before modulation: 0 0011110111101110 Synchronization signal after modulation: 0 001011010110110100 When the differential reference bit value is 0, a synchronization signal different from the above example is modulated. The result is as follows. Synchronization signal Synchronization signal before modulation: 0 1100101000010001 Synchronization signal after modulation: 0 10000110000011110

When the differential reference bit value is 1,
The modulation result of the synchronization signal is as follows. When the differential reference bit value is 1: Synchronization signal Synchronization signal before modulation: 1100110111101110 Synchronization signal after modulation: 1 1101100101001011 When the differential reference bit value is 1, a synchronization signal different from the above example is modulated. The result is as follows. Synchronization signal Synchronization signal before modulation: 1 1100101000010001 Synchronization signal after modulation: 110111001111100001

FIG. 17 is an explanatory diagram for explaining a DBPSK demodulation method of a synchronization signal in a TMCC carrier. The synchronization signal obtained by the DBPSK modulation shown in FIG.
In the case of demodulation, the differential reference bit for differential demodulation has a specification that changes for each carrier. That is, one OFDM
One or a plurality of TMCC carriers are present in the carrier configuration, and the value of the differential reference bit changes according to the carrier number of these carriers. After inverting all the previous data, the demodulation start bit (ie, the differential reference bit, and if inverted, the inverted differential reference bit) is used as a reference to the subsequent bit sequence. To perform differential demodulation. In this differential demodulation, similarly to the above-described differential modulation method, when the value of the current bit does not change compared to the value of the immediately preceding bit, it is set to 0, and when it changes, it is set to 1.

As described above, in the ISDB digital broadcast receiving apparatus, first, in the frame synchronization processing, the same bit pattern as the synchronization signal is detected, and the synchronization signal is confirmed for each frame. In this case, after calculating the differential reference bits, differential demodulation is performed on the subsequent bits, and when the result of the differential demodulation matches the bit pattern of the synchronization signal, frame synchronization is established. .

The frame synchronization processing in the ISDB digital broadcast receiving apparatus will be described below in more detail. FIG. 18 is a flowchart showing a frame synchronization processing operation by the ISDB digital broadcast receiving apparatus. First, 1
Acquire TMCC carriers for frames (step S
T111). Next, a differential reference bit is calculated in the TMCC carrier (step ST112), and differential two-phase demodulation (DBPSK demodulation) is performed on a subsequent bit string in the TMCC carrier based on the value of the differential reference bit. Perform (Step ST113).

Next, of the two types of synchronization signals described above,
Which bit pattern (0011 ... or
16-bit pattern starting with 1100 ...)
Is checked (step ST114). If any of them is matched, the process flow proceeds to step ST115. If not, the process flow is changed to step ST111.
Return to

In step ST115, a TMCC carrier for the next one frame is obtained. And the acquired 1
The differential reference bit value is calculated from the TMCC carriers for the frame (step ST116), and then the DBPSK demodulation of the TMCC carrier is performed (step ST117).
Then, the bit pattern of the synchronization signal in the DBPSK demodulation result is bit-inverted, and it is checked whether the bit pattern of the synchronization signal in the DBPSK demodulation result detected in step ST114 matches the inverted pattern (step ST118). That is, since the synchronization signal in the TMCC carrier should be transmitted as a bit pattern in which the bit is inverted for each frame, the bit pattern obtained by inverting the bit pattern of the synchronization signal after the DBPSK demodulation detected in step ST114 is obtained in step S114.
It should be the bit pattern of the synchronization signal after DBPSK demodulation obtained in T117. As a result of the check, if it is determined that they match, the process flow proceeds to step ST119. If they do not match, the process flow proceeds to step ST11.
Return to 1.

In step ST119, a frame error is detected from the position of the synchronizing signal, and the obtained T for one frame is detected.
The frame error is corrected for the MCC carrier, and the frame synchronization process is completed (step ST120).

By the way, in the DAB which is a European digital audio broadcast, a NULL symbol having no carrier is inserted at the head of the frame as shown in FIG.
Symbols can be easily detected.

FIG. 19 is an explanatory diagram for explaining an operation in which the DAB receiver detects a NULL symbol and generates a NULL signal, and FIG. 20 is a flowchart showing a frame synchronization processing operation by the DAB receiver. In the frame synchronization processing by the DAB receiving apparatus, first, the DAB receiving apparatus
The falling of the NULL signal corresponding to the LL symbol is detected (step ST130). Then, an operation of detecting and correcting an error of the digital signal received from the detected falling position is performed (step ST131).

Thus, the frame synchronization on the DAB receiving device side is completed (step ST132). As described above, since no carrier exists in the first symbol of the frame in DAB, a NULL symbol can be easily detected by hardware in the DAB receiving apparatus, and
The time required for frame synchronization on the side of the AB receiver is almost nil.

On the other hand, in a digital broadcast receiving apparatus used for ISDB which is a domestic digital broadcast, FIG.
As shown in the flowchart, the ISDB signal received via an antenna or the like is DBPSK demodulated, and the DB
A process for comparing the result of the PSK demodulation with the bit pattern of the synchronization signal to detect the synchronization signal is required.

[0023]

Since the conventional digital broadcast receiving apparatus and frame synchronization detecting method are configured as described above, when performing frame synchronization of a received ISDB signal, two consecutive TMCC carriers of two frames are required. After calculating each differential reference bit and performing DBPSK demodulation on a bit string indicating synchronization information following the differential reference bit, it is necessary to detect the presence or absence of the same bit pattern as the synchronization signal for each TMCC carrier. There was a problem that it took time to start up.

In order to shorten the start-up time, a method is conceivable in which the presence or absence of the same bit pattern as the synchronization signal is detected for each TMCC carrier before performing the differential demodulation (DBPSK demodulation). However, by performing the differential demodulation, the frequency shift in the frequency direction is corrected for each symbol. For this reason, if it is determined that the same bit pattern as the synchronization signal exists before the differential demodulation, if the frequency of the carrier of the TMCC carrier is slightly detuned, errors due to detuning accumulate as one frame is carried. However, there is a problem that the possibility of occurrence of an error in the latter half of the frame becomes extremely high, and it is not possible to accurately determine the coincidence of the same bit pattern as that of the synchronization signal.

The present invention has been made to solve the above problems, and has as its object to provide a digital broadcast receiving apparatus which can easily establish frame synchronization of a received ISDB signal and can start up quickly. And

[0026]

According to the present invention, there is provided a digital broadcast receiving apparatus comprising:
Regarding the SK-modulated TMCC carrier, the value of each bit in the TMCC carrier is compared with the value of the immediately preceding bit regardless of the value of the differential reference bit. Differential demodulation means for performing differential demodulation as 1; 1-frame storage means for storing one frame of TMCC carrier obtained from the differential demodulation means;
An exclusive OR operation is performed between one frame delay means for delaying the TMCC carrier in one frame storage means by one frame and two TMCC carriers obtained from the one frame storage means and one frame delay means. XOR operation means, pattern detection means for searching the operation result of the XOR operation means, and detecting the position of a predetermined bit pattern of the synchronization information included in the TMCC carrier, based on the detection result outputted from the pattern detection means , A frame error converting means for outputting a shift of the ISDB signal to the head position of the frame as a frame error.

[0027] In the digital broadcast receiving apparatus according to the present invention, when the predetermined bit pattern of the synchronization information included in the TMCC carrier detected by the pattern detection means is 16 bits, the synchronization information in the TMCC carrier is "11111111".
111111111 ", and all bits other than the synchronization information in the TMCC carrier are 0.

In the digital broadcast receiving apparatus according to the present invention, when there are a plurality of TMCC carriers in which the same data content is to be stored among the TMCC carriers obtained from the differential demodulating means, each of the plurality of TMCC carriers is provided. , And a majority decision means for generating a TMCC carrier storing a value having the highest appearance frequency is provided, and the one-frame storage means is provided for the one frame obtained from the majority decision means. TMC
The C carrier is stored.

The digital broadcast receiving apparatus according to the present invention includes a power conversion means for adding the number of bits constituting the synchronization information to the bit pattern of the operation result obtained from the XOR operation means while shifting it by one bit. Prepared,
The pattern detecting means detects the position of the bit pattern for which the power conversion means has calculated the maximum addition value as the position of the predetermined bit pattern of the synchronization information included in the TMCC carrier.

The frame synchronization detecting method according to the present invention comprises:
DBPSK modulated TM from received ISDB signal
Regarding the CC carrier, irrespective of the value of the differential reference bit, the value of each bit in the TMCC carrier is compared with the value of the immediately preceding bit. Differential demodulation step for demodulation, and two-frame TMC obtained in the differential demodulation step
An XOR operation step of performing an exclusive OR operation between C carriers, a pattern detection step of searching for an operation result in the XOR operation step, and detecting a position of a predetermined bit pattern of synchronization information included in the TMCC carrier; A frame error conversion step of outputting a shift of the ISDB signal to the head position of the frame as a frame error based on the detection result in the pattern detection step.

The frame synchronization detecting method according to the present invention
When the predetermined bit pattern of the synchronization information included in the TMCC carrier detected in the pattern detection step is 16 bits, the synchronization information in the TMCC carrier is “111111”.
11111111111 ", and all bits other than the synchronization information in the TMCC carrier are 0.

The frame synchronization detecting method according to the present invention comprises:
When there are a plurality of TMCC carriers in which the same data content is to be stored among the TMCC carriers obtained in the differential demodulation step, an appearance frequency of a value of a bit corresponding to each of the plurality of TMCC carriers is determined. And a majority decision step for generating a TMCC carrier storing a value having the highest appearance frequency. In an XOR operation step, an exclusive OR operation between the TMCC carriers of the two frames obtained in the differential demodulation step is performed. Is to execute.

The frame synchronization detecting method according to the present invention comprises:
A power conversion step of adding the number of bits constituting the synchronization information to the bit pattern of the calculation result obtained in the XOR calculation step while shifting the bit pattern by one bit; The position of the bit pattern for which the maximum addition value has been calculated
This is detected as a position of a predetermined bit pattern of the synchronization information included in the MCC carrier.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of a digital broadcast receiving apparatus according to Embodiment 1 of the present invention.
In the figure, reference numeral 1 denotes a differential demodulator (differential demodulation means) for differentially demodulating a DBPSK-modulated TMCC carrier.
Regardless of the value of the differential reference bit of the CC carrier, the value of each bit in the TMCC carrier is compared with the value of the immediately preceding bit. 2 is a one-frame accumulator (one-frame accumulator) for storing one frame of TMCC carrier obtained from the differential demodulator 1, and 3 is a one-frame accumulator 2.
Is a one-frame delay element (one-frame delay means) for delaying one TMCC carrier by one frame, and 4 is an XOR operation between the two-frame TMCC carriers obtained from the one-frame accumulator 2 and the one-frame delay element 3 (exclusive operation). XOR operator (XOR operation means) for executing a logical OR operation, a pattern detector (pattern detector) (5) for searching the operation result of the XOR operator 4 and detecting the position of a predetermined bit pattern of the synchronization information included in the TMCC carrier. Detection means), 6 are ISD based on the detection result output from the pattern detector 5
A frame error converter (frame error conversion means) that outputs a shift of the B signal to the head position of the frame as a frame error.

Next, the operation will be described. FIG. 2 is a flowchart showing the frame synchronization processing by the digital broadcast receiving apparatus of FIG. 1, and the operation will be described along this flow. First, an ISDB signal transmitted from a digital broadcast transmitter is received via an antenna. Next, IS
After the DB signal is converted to the intermediate frequency by the tuner,
The data is converted into digital data by the A / D converter. Furthermore, a real part (in-phase component: I
n phase) and an imaginary part (quadrature component: Quadra)
(TFT), and is subjected to fast Fourier transform processing by an FFT processor. The configuration up to this point is DAB
This is the same as a receiving device or a general digital broadcast receiving device, and illustration and detailed description are omitted.

Next, the digital data subjected to the fast Fourier transform processing by the FFT processor is processed by the carrier divider.
It is divided and extracted into a main signal carrier, a pilot carrier, an additional information carrier, a TMCC carrier as a control signal carrier, and the like. The main signal carrier is output to a subsequent demodulation circuit, which is also the same as the processing of a general digital broadcast receiving apparatus, so that illustration and detailed description are omitted here.

The TMCC carrier divided and extracted by the carrier divider is differentially demodulated by the differential demodulator 1 (step ST1, differential demodulation step). Traditionally,
When differentially demodulating a DBPSK-modulated synchronization signal as shown in FIG. 14, one or a plurality of TMCC carriers exist in one OFDM carrier configuration as described above, and according to the carrier numbers of these carriers, Since the value of the differential reference bit changes, first, the differential reference bit is detected.
After inverting all the data before SK demodulation, differential demodulation is performed on the subsequent bit string based on the value of the bit for starting demodulation. On the other hand, the digital broadcast receiving apparatus according to the first embodiment reduces the time required for differential demodulation by performing differential demodulation regardless of the value of the differential reference bit (ie, without detecting the differential reference bit). are doing.

FIG. 3 is an explanatory diagram for explaining a method of differentially demodulating a synchronization signal in a TMCC carrier by the digital broadcast receiving apparatus according to the first embodiment. As shown in the figure, regardless of the value of the differential reference bit, the differential demodulator 1 changes to 0 when the value of the first bit of the TMCC carrier does not change with respect to the immediately preceding bit. In this case, the differential demodulation is performed by setting it to 1. This may cause an error in the value of the differential reference bit as described below, but the operation for detecting the differential reference bit can be omitted.

In the above-described differential demodulation processing, the differential demodulator 1 does not detect the differential reference bit and outputs the value as it is. At this time, this corresponds to a state where differential demodulation is not performed on the first bit of demodulation. For this reason, in the example described in the upper part of FIG. 3, the value of the first bit of demodulation matches the differential reference bit, and the bit string obtained by differential demodulation is correctly demodulated as the differential reference bit value 0. In the example shown in the lower part of FIG. 3, the first bit of demodulation does not match the differential reference bit, and the value before and after demodulation is different. As described above, in the differential demodulation according to the first embodiment, there is a possibility that an error is included in the value of the differential reference bit, but since it is only one bit, it has a great effect on frame synchronization of the TMCC carrier. I will not give.

As described above, the TMCC carrier differentially demodulated by the differential demodulator 1 is stored in the one-frame accumulator 2
Is stored within. The TMCC carrier for one frame stored in the one-frame accumulator 2 is delayed by one frame in the one-frame delay element 3. This allows
Two consecutive TMCC carriers are obtained from the TMCC carrier output from the one-frame delay element 3 and the TMCC carrier in the one-frame accumulator 2 (step ST2, step ST3).

The following shows the patterns of TMCC carriers for two frames after the differential demodulation processing. However, after the 16-bit synchronization signal used for frame synchronization,
The differential "111" is given as a type identification code. Synchronization signal before differential encoding Format identification code Previous frame: 0 0011010111101110 111. . . Current frame: 0 1100101000010001 111. . . The result of performing the XOR operation between the two frames before the differential encoding is defined as a signal pattern after the differential encoding.

FIG. 4 shows TM for two frames before differential encoding.
FIG. 4 is an explanatory diagram showing an XOR operation of a CC carrier. As shown in the figure, the XOR operation unit 4 determines between the signal pattern of the TMCC carrier in the one-frame accumulator 2 and the signal pattern of the TMCC carrier output from the one-frame delay element 3 and delayed by one frame. An XOR operation is performed (step ST4, XOR operation step). Thus, XO
The result of the R operation is a fixed pattern "11111111111111111" in the synchronization signal portion in the signal of the TMCC carrier.
Appears. Then, portions other than the synchronization signal, for example, the differential reference bits, the format identification code, the TMCC information, and the parity bits all have the value 0.

The position of the fixed pattern “1111111111111111” of the XOR operation result is TM
The pattern detector 5 detects the position in the CC carrier, and outputs the detection result to the frame error converter 6 (step ST5, pattern detection step).

The detection result output from the pattern detector 5, that is, the fixed pattern "11111111111111"
Based on the detected position information of 111 ″, from the position considered to be the head of the frame in the digital broadcast receiving apparatus,
The frame error converter 6 calculates how many symbols the true frame head position is shifted as a frame error, and feeds it back to a synchronization processing unit (not shown) (step ST6, frame error conversion step). Therefore, XOR
Among the results obtained by the calculation, the fixed pattern "11
By searching the position of “111111111111111”, the magnitude of the frame synchronization error can be obtained. That is, the detected fixed pattern “11111111” can be obtained.
The head of 11111111 "corresponds to the second symbol of the frame (the bit position next to the differential reference bit).

As described above, according to the first embodiment, differential demodulator 1 sets the value of each bit in the TMCC carrier to the value of the immediately preceding bit regardless of the value of the differential reference bit of the TMCC carrier. The value is differentially demodulated as 0 when the value does not change compared to the value, and as 1 when the value changes. X
The OR operation is performed, and the pattern detector 5 searches for the XOR operation result and obtains the fixed pattern “1111111111”.
Since it is configured to detect the presence / absence of 111111 ″ and to know the position of the synchronization signal that is the synchronization information in the TMCC carrier and perform the frame synchronization processing, the operation of calculating the differential reference bit in the differential demodulation processing is omitted. In addition, after the differential demodulation, the comparison process for checking whether the bit pattern of the synchronization signal matches the bit pattern does not need to be performed for each of two consecutive TMCC carriers. Can be shortened, and the digital broadcast receiving apparatus can be quickly started.

Embodiment 2 FIG. 5 is a block diagram showing a configuration of a digital broadcast receiving apparatus according to Embodiment 2 of the present invention. In the figure, reference numeral 13 denotes a majority decision unit (majority decision means) which is a plurality of TCCs in which the same data content is to be stored among the TMCC carriers obtained from the differential demodulator 1.
When an MCC carrier is present, these multiple
The value with the highest appearance frequency in the bit corresponding to each of the carriers is determined to generate a majority-determined TMCC carrier. The same components as those in FIG. 1 are denoted by the same reference numerals, and duplicate description will be omitted.

Next, the operation will be described. FIG. 6 is a flowchart showing the frame synchronization processing by the digital broadcast receiving apparatus of FIG. 5, and the operation will be described along this flow. First, the operation of dividing the digital data of the ISDB signal subjected to the fast Fourier transform processing into a main signal carrier, a pilot carrier, an additional information carrier, a TMCC carrier as a control signal carrier, and the like by a carrier divider is described above. Since it is the same as in the first embodiment, a duplicate description will be omitted.

The TMCC carrier divided and extracted by the carrier divider is differentially demodulated by the differential demodulator 1 (step ST1a, differential demodulation step). Also in this differential demodulation process, the value of the first bit of the TMCC carrier is referenced regardless of the value of the differential reference bit (that is, without detecting the differential reference bit) as described in the first embodiment. By applying a differential demodulation method to 0 when there is no change to the immediately preceding bit and 1 when there is a change, the time required for differential demodulation processing can be shortened.

In the DBPSK modulation of the ISDB signal, data of the same content may be stored and transported on a plurality of TMCC carriers depending on the number of modes.
As described above, by storing the same data in a plurality of TMCC carriers, the data contents stored in the TMCC carrier corresponding to the frequency of the carrier having a poor reception state can be received from the TMCC carriers corresponding to other frequencies. To be able to.

FIG. 7 is a diagram showing an example in which a plurality of TMCC carriers for storing data having the same contents exist in the carrier of the ISDB signal. In the example shown in the figure, in mode 1, there are five TMCC carriers (TMCC1 to TMCC5) that store data of the same content. These TMCC
The carriers should ideally all have the same data content. However, when a failure occurs in the reception of a carrier wave of a certain frequency due to the communication environment of the place where the receiving device is installed, the TMCC carriers (TMCC1 to TMCC1)
Some of the data contents stored in any of the TMCCs 5) may change. If the data stored in the TMCC carrier can be determined to be completely erroneous due to a reception failure or the like, the process can shift to a process of receiving the same data from the TMCC carrier corresponding to another frequency. When a part of the data changes as in the example shown, the TMCC having the true data content
It may not be possible to determine the carrier.

Therefore, in the second embodiment, the majority decision unit 13 uses the TMCC carriers (TMCC1 to TMC
C5) TMC that determines the appearance frequency of the value of the bit corresponding to each of the bits and stores the value with the highest appearance frequency
A C carrier is generated (step ST2a, majority decision step). FIG. 8 is an explanatory diagram illustrating majority decision processing of the majority decision unit according to the second embodiment. In the illustrated example, the TMCC carriers (TMCC1 to TMCC5) in which the same data should be stored have the differential reference bits and the bit value in the first symbol number of the synchronization signal set to TMCC depending on the communication state of the receiving side. Different values are received depending on the carrier (depending on the frequency of the carrier). On the other hand, the majority decision unit 13
Counts the appearance frequency of the value of each bit having the same symbol number of each TMCC carrier (TMCC1 to TMCC5) along the carrier number (frequency direction of the carrier wave). The majority decision unit 13 determines the value having the highest appearance frequency obtained as the counting result as the most probable value for the bit, and generates a TMCC carrier that stores this value.

As described above, the TMCC carrier for which the majority decision is made by the majority decision unit 13 is stored in the one-frame accumulator 2. The TMCC carrier for one frame stored in the one-frame accumulator 2 is delayed by one frame in the one-frame delay element 3. Thus, TMCC carriers for two consecutive frames are obtained from the TMCC carriers output from the one-frame delay element 3 and the TMCC carriers in the one-frame accumulator 2 (steps ST3a and ST4a).

Thereafter, the XOR operation processing is performed on the bit patterns of the TMCC carriers for two frames after the differential demodulation processing by the XOR operation unit 4 (step ST5).
a, XOR operation step), the position of the fixed pattern “1111111111111111” of the XOR operation result is T
The pattern detector 5 detects the position in the MCC carrier (step ST6a, pattern detection step), and based on the detection result output from the pattern detector 5, the frame error converter 6 calculates a frame error, The feedback to the synchronization processing unit (not shown) (step ST6, frame error conversion step) is the same as that described in the first embodiment.

As described above, according to the second embodiment, when there are a plurality of TMCC carriers to which the same data content is to be stored among the differentially demodulated TMCC carriers, the plurality of TMCC carriers are used. The appearance frequency of the value of each corresponding bit is determined, and the TMCC carrier that stores the value with the highest appearance frequency as a true TMCC carrier is generated. The stored data can be accurately received. This allows
The process of detecting the bit pattern of the synchronization signal can be accurately performed, and the frame error can be accurately detected.

Embodiment 3 FIG. 9 is a block diagram showing a configuration of a digital broadcast receiving apparatus according to Embodiment 3 of the present invention. In the figure, reference numeral 15 denotes a power converter (power conversion means), which performs addition of the number of bits constituting the synchronization information on the bit pattern of the operation result obtained by the XOR operation unit 4 while shifting it by one bit. , Are sequentially output to the peak detector 16. Reference numeral 16 denotes a peak detector (pattern detecting means), which is a power converter 15
Of the addition results from TMCC corresponding to the maximum addition value
The position in the carrier is detected and output to the frame error converter 6. The same components as those in FIG. 1 are denoted by the same reference numerals, and duplicate description will be omitted.

Next, the operation will be described. FIG. 10 shows FIG.
FIG. 4 is a flowchart showing a frame synchronization process by the digital broadcast receiving apparatus of FIG. First, the digital data of the ISDB signal subjected to the fast Fourier transform processing is divided by a carrier divider into a main signal carrier, a pilot carrier, an additional information carrier, a TMCC carrier as a control signal carrier, and the like. The TMCC carrier thus extracted is differentially demodulated by the differential demodulator 1 (step ST1b, differential demodulation step). Also in this differential demodulation process, the value of the first bit of the TMCC carrier is referenced regardless of the value of the differential reference bit (that is, without detecting the differential reference bit) as described in the first embodiment. By applying a differential demodulation method to 0 when there is no change to the immediately preceding bit and 1 when there is a change, the time required for differential demodulation processing can be shortened.

The differentially demodulated TMCC carrier is stored in the one-frame accumulator 2. This one-frame accumulator 2
The TMCC carrier for one frame stored in the
It is delayed by one frame in the frame delay element 3.
Thereby, TM output from one-frame delay element 3
Two consecutive frames of TMCC carriers are obtained from the CC carriers and the TMCC carriers in the one-frame storage 2 (step ST2b, step ST3b).

Thereafter, the XOR operation is performed on the bit patterns of the TMCC carriers for two frames after the differential demodulation processing by the XOR operation unit 4 (step ST4b, XOR operation step). The fixed pattern “11111111” of the XOR operation result obtained in this way
The TMCC carrier having 11111111 ″ is output to the power converter 15.

The power converter 15 adds the number of bits constituting the synchronization signal to the bit pattern of the operation result obtained by the XOR operation unit 4 while shifting it by one bit (step ST5b, power conversion step). ). FIG. 11 is an explanatory diagram illustrating the detection processing of the synchronization signal pattern of the power converter and the peak detector according to the third embodiment. As shown in the upper part of FIG. 11, when the power converter 15 receives the TMCC carrier from the XOR operator 4, the power converter 15 adds 16 bits to the bit sequence arranged in the time direction of the TMCC carrier (the number of bits constituting the synchronization signal). (Addition of minutes) is performed while shifting by one bit. In the XOR operator 4, 16-bit "11111111111111111" is used as a fixed pattern corresponding to the synchronization signal.
Is obtained, the 16-bit addition by the power converter 15 described above results in the logical value 1 included in the fixed pattern.
Are all 16 at decimal positions, and this position corresponds to the position of the fixed pattern of the synchronization signal on the TMCC carrier.

In the upper part of FIG. 11, if the starting point in the bit string of the 16-bit addition by the power converter 15 is shifted, the added value becomes “15”, “14”, “13”, “1”.
2 "," 11 ", etc., and the maximum value cannot be obtained. The added value of these power converters 15 is calculated by the peak detector 16
Are sequentially output to

The peak detector 16 obtains the relationship between the time at which each bit is sent and the addition result as shown in the lower part of FIG. 11 from the addition value from the power converter 15, and determines the bit for which the maximum addition value has been calculated. The position of the pattern is detected as the position of the fixed pattern of the synchronization signal (step ST6b, pattern detection step). As can be seen from the lower graph of FIG. 11, the result of performing the 16-bit addition on the bit sequence arranged in the time direction of the TMCC carrier is the highest added value 16 including the first bit of the synchronization signal, and the peak is obtained. , And the addition result of less than 16 is obtained in 16-bit addition using the other bit position as the start point of addition. The peak detector 16 calculates the time corresponding to the start point in the bit sequence of the 16-bit addition that becomes the peak, and outputs the calculated time to the frame error converter 6.

In the frame error converter 6, the output result from the peak detector 16, that is, the fixed pattern "11111"
Based on the time corresponding to the first bit of 111111111111 ″, how many symbols the true frame start position is shifted from the position considered to be the start of the frame in the digital broadcast receiving apparatus is calculated as a frame error. This is fed back to a processing unit (not shown) (step ST7b, frame error conversion step) .Therefore, by searching for the position of the fixed pattern “1111111111111111” in the result obtained by the XOR operation, The magnitude of the synchronization error can be obtained, that is, the detected fixed pattern “1111” can be obtained.
The head of “111111111111 ″ corresponds to the second symbol of the frame (the bit position next to the differential reference bit).

As described above, according to the third embodiment, the addition of the number of bits constituting the synchronization information to the bit pattern of the TMCC carrier obtained by the XOR operation is performed while shifting by one bit. Since the position of the bit pattern for which the maximum addition value is calculated is detected as the position of the predetermined bit pattern of the synchronization information included in the TMCC carrier, the process of detecting the bit pattern of the synchronization signal can be performed accurately, An error can be accurately detected.

Note that the configuration of the third embodiment may be applied to the second embodiment, whereby the effects of both embodiments can be obtained.

[0065]

As described above, according to the present invention, the DBCC-modulated TMCC from the received ISDB signal is used.
Regardless of the value of the differential reference bit for the carrier, T
When the value of each bit in the MCC carrier is not changed as compared with the value of the immediately preceding bit, the bit is differentially demodulated as 0, and when it is changed, the bit is differentially demodulated as 1. A logical sum operation is executed, the result of the operation is searched, the position of a predetermined bit pattern of the synchronization information included in the TMCC carrier is detected, and based on the detection result, the deviation of the ISDB signal to the head position of the frame is detected. Since this is output as a frame error, the operation of calculating the differential reference bit in the differential demodulation processing is omitted,
In addition, after the differential demodulation, the comparison process for determining whether or not the bit pattern of the synchronization signal matches the bit pattern does not need to be performed for each of two consecutive TMCC carriers.
The time required for frame synchronization processing can be reduced,
There is an effect that the digital broadcast receiving apparatus can be started up quickly.

According to the present invention, when the synchronization information in the TMCC carrier is 16 bits, the pattern corresponding to the synchronization information is “11111111111111111”,
Since a predetermined bit pattern in which all bits other than the synchronization information are 0 is detected, after differential demodulation, a comparison process of whether or not the bit pattern matches the bit pattern of the synchronization signal is performed for each of two consecutive TMCC carriers. Since it does not need to be performed, the time required for the frame synchronization processing can be reduced, and the digital broadcast receiving apparatus can be started up quickly.

According to the present invention, differentially demodulated TMC
When there are a plurality of TMCC carriers in which the same data content is to be stored among the C carriers, the plurality of TCC carriers
The appearance frequency of the value of the bit corresponding to each of the MCC carriers is determined, a TMCC carrier that stores the value with the highest appearance frequency is generated, and this is accumulated for two frames. Since the logical sum operation is performed, there is an effect that data stored in the TMCC carrier can be accurately received even in a poor reception environment with much noise. As a result, the process of detecting the bit pattern of the synchronization signal can be accurately performed, and the frame error can be accurately detected.

According to the present invention, the bit pattern of the result of the XOR operation is added by the number of bits constituting the synchronization information while shifting by one bit, and the position of the bit pattern for which the maximum added value is calculated is Since the position is detected as the position of the predetermined bit pattern of the synchronization information included in the TMCC carrier, the process of detecting the bit pattern of the synchronization signal can be performed accurately, and the frame error can be accurately detected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital broadcast receiving device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing frame synchronization processing by the digital broadcast receiving apparatus of FIG. 1;

FIG. 3 is an explanatory diagram illustrating a method for differentially demodulating a synchronization signal in a TMCC carrier by the digital broadcast receiving apparatus according to the first embodiment.

FIG. 4 is an explanatory diagram showing an XOR operation of TMCC carriers for two frames before differential encoding.

FIG. 5 is a block diagram showing a configuration of a digital broadcast receiving device according to a second embodiment of the present invention.

FIG. 6 is a flowchart showing a frame synchronization process by the digital broadcast receiving apparatus of FIG. 5;

FIG. 7 is a diagram illustrating an example in which a plurality of TMCC carriers for storing data having the same contents exist in a carrier of an ISDB signal.

FIG. 8 is an explanatory diagram illustrating a majority decision process of a majority decision unit according to the second embodiment.

FIG. 9 is a block diagram showing a configuration of a digital broadcast receiving device according to a third embodiment of the present invention.

FIG. 10 is a flowchart showing a frame synchronization process by the digital broadcast receiving apparatus of FIG. 9;

FIG. 11 is an explanatory diagram illustrating detection processing of a synchronization signal pattern of a power converter and a peak detector according to a third embodiment.

FIG. 12 is a diagram illustrating a configuration of a frame used in DAB.

FIG. 13 is a diagram illustrating a configuration of a carrier of an ISDB signal.

FIG. 14 is a diagram illustrating a configuration of a TMCC carrier in a time direction.

FIG. 15 is an explanatory diagram illustrating an example in which a bit-inverted synchronization signal is inserted for each frame.

FIG. 16 shows a DBPS of a synchronization signal in a TMCC carrier.
FIG. 4 is an explanatory diagram illustrating a K modulation method.

FIG. 17 shows a DBPS of a synchronization signal in a TMCC carrier.
FIG. 4 is an explanatory diagram illustrating a K demodulation method.

FIG. 18 is a flowchart showing a frame synchronization processing operation by the ISDB digital broadcast receiving apparatus.

FIG. 19 is an explanatory diagram illustrating an operation in which the DAB receiving device detects a NULL symbol and generates a NULL signal.

FIG. 20 is a flowchart showing a frame synchronization processing operation by the DAB receiving apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Differential demodulator (differential demodulation means), 2 1 frame accumulator (1 frame accumulation means), 3 1 frame delay element (1 frame delay means), 4 XOR operator (XOR operation means), 5 pattern detector (Pattern detection means),
6. Frame error converter (frame error conversion means), 1
3 Majority decision unit (majority decision unit), 15 power converter (power conversion unit), 16 peak detector (pattern detection unit).

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masakazu Morita 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation F-term (reference) 5K004 AA05 FA03 FC02 FG00 5K047 AA01 BB01 CC08 HH01 MM11 MM12

Claims (8)

[Claims] 1. DBPSK from a received ISDB signal
Regarding the modulated TMCC carrier, irrespective of the value of the differential reference bit, if the value of each bit in the TMCC carrier does not change as compared with the value of the immediately preceding bit, it is 0; Differential demodulating means for performing differential demodulation as 1, one frame accumulating means for storing one frame of TMCC carrier obtained from the differential demodulating means, and delaying the TMCC carrier in the one frame accumulating means by one frame One-frame delay means; XOR operation means for performing an exclusive OR operation between the one-frame storage means and the two-frame TMCC carrier obtained from the one-frame delay means; and an operation result of the XOR operation means Search for the above TMC
Pattern detection means for detecting the position of a predetermined bit pattern of the synchronization information included in the C carrier; and, based on the detection result output from the pattern detection means, outputting a deviation up to the head position of the frame of the ISDB signal as a frame error. A digital broadcast receiving apparatus comprising: 2. The predetermined bit pattern of the synchronization information included in the TMCC carrier detected by the pattern detection means is “1111111111111111” when the synchronization information in the TMCC carrier is 16 bits, and
2. The digital broadcast receiving apparatus according to claim 1, wherein all bits other than the synchronization information in the MCC carrier are 0. 3. A plurality of TCCs in which the same data content is to be stored among TMCC carriers obtained from the differential demodulation means.
When an MCC carrier is present, these multiple
TM that determines the appearance frequency of the value of the bit corresponding to each carrier and stores the value with the highest appearance frequency
2. The digital broadcast receiving apparatus according to claim 1, further comprising a majority decision means for generating a CC carrier, wherein the one frame storage means stores one frame of the TMCC carrier obtained from the majority decision means. 4. A power conversion means for adding the number of bits constituting the synchronization information to the bit pattern of the operation result obtained from the XOR operation means while shifting the bit pattern by one bit. 4. The power conversion unit according to claim 1, wherein a position of the bit pattern at which the maximum addition value is calculated is detected as a position of a predetermined bit pattern of synchronization information included in the TMCC carrier. The digital broadcast receiving device according to the item. 5. DBPSK from a received ISDB signal
Regarding the modulated TMCC carrier, irrespective of the value of the differential reference bit, if the value of each bit in the TMCC carrier does not change as compared with the value of the immediately preceding bit, it is 0; A differential demodulation step of performing differential demodulation as 1, and a two-frame TMC obtained in the differential demodulation step.
An XOR operation step of performing an exclusive OR operation between C carriers, and searching for an operation result in the XOR operation step,
A pattern detection step for detecting the position of a predetermined bit pattern of the synchronization information included in the TMCC carrier; and a frame for outputting a shift to the head position of the ISDB signal frame as a frame error based on the detection result in the pattern detection step. A frame synchronization detection method comprising: an error conversion step. 6. TM detected in a pattern detection step
The predetermined bit pattern of the synchronization information included in the CC carrier is “111111111111111” when the synchronization information in the TMCC carrier is 16 bits, and all bits other than the synchronization information in the TMCC carrier are 0. The frame synchronization detecting method according to claim 5, wherein: 7. The TMCC obtained in the differential demodulation step
When there are a plurality of TMCC carriers in which the same data content is to be stored, the plurality of TMCC carriers
A majority decision step of determining a frequency of appearance of a value of a bit corresponding to each of the CC carriers and generating a TMCC carrier storing a value of the highest frequency of occurrence; 6. The frame synchronization detecting method according to claim 5, wherein an exclusive OR operation between the TMCC carriers of the two frames obtained in the step (a) is performed. 8. A power conversion step of adding the number of bits constituting the synchronization information to the bit pattern of the operation result obtained in the XOR operation step while shifting the bit pattern by one bit. 8. The method according to claim 5, wherein a position of the bit pattern for which the maximum addition value is calculated in the power conversion step is detected as a position of a predetermined bit pattern of synchronization information included in the TMCC carrier. A frame synchronization detection method according to any one of the preceding claims.