JP4541798B2 - Charged particle beam lens array, and charged particle beam exposure apparatus using the charged particle beam lens array - Google Patents

Description

  The present invention belongs to the technical field of charged particle beam lenses used in exposure apparatuses using charged particle beams such as electron beams, and particularly relates to an electron lens array in which electron lenses are arrayed.

  In the production of semiconductor devices, electron beam exposure technology has been spotlighted as a promising candidate for lithography that enables exposure of fine patterns of 0.1 μm or less, and there are several methods.

  One of these methods is a multi-beam type exposure system that draws a pattern simultaneously with multiple electron beams without using a mask, eliminating the need for physical mask fabrication and replacement, and has many advantages for practical application. It is to be prepared. What is important in making an electron beam multi-purpose is the number of arrays of electron lenses used for this. The number of beams is determined by the number of electron lenses that can be arranged inside the multi-beam type exposure apparatus, which is a major factor in determining the throughput. For this reason, how to reduce the size while improving the performance of the electron lens is one of the keys to improving the performance of the multi-beam exposure apparatus.

  Japanese Patent Application Laid-Open No. 2004-55166 is a patent document showing an example of an electron lens array used in a multi-beam type exposure apparatus. FIG. 14 is a cross-sectional view of the electron lens array 300. Here, the electron lens array 300 is disclosed as an array of Einzel lenses by aligning three electrodes 301 using fibers 302 and grooves 304 formed on a Si substrate. A conductive shield electrode 303 is provided between the fiber 302 and the electron beam passage region to prevent the fiber 302 from being charged up. Fabrication is performed using micromechatronics technology. In addition, a multi-beam type exposure apparatus using the electron lens array 300 is disclosed.

Japanese Patent Laid-Open No. 2001-345259 is a patent document showing an example of another electron lens array. FIG. 15 is a cross-sectional view of the electron lens array 400, 401 is an electrode, and 403 is a shield electrode. Here, the electron lens array 400 discloses a structure in which a shield electrode 403 is provided between the electron lenses in a direction parallel to the optical axis to prevent crosstalk between the beams. Again, the fabrication is done using micromechatronics technology.
JP 2004-55166 A JP 2001-345259 A

  An object of the present invention is to provide an electronic lens array for a multi-beam type exposure apparatus, which is intended to be improved over the conventional one, and to provide an electronic lens array with a simpler configuration that can apply a high voltage with less crosstalk. It is what.

  In order to achieve the above object, the present invention provides a charged particle beam lens array in which an upper electrode, a middle electrode, and a lower electrode each having a plurality of openings are arranged in this order, between the upper electrode and the middle electrode, and It has the insulator arrange | positioned at least one between the middle electrode and the said lower electrode, The surface of the said insulator is uneven | corrugated shape or a wave shape, It is characterized by the above-mentioned.

  Further, the present invention may be characterized in that the middle electrode is electrically independent for each row of the openings, and the aspect ratio of the uneven shape or the wave shape is 2 or more. Alternatively, at least one of the upper electrode and the lower electrode may have a shield electrode for each row of the openings, and the shield electrode may have a cylindrical shape. The shield electrode may be electrically connected to at least one of the upper electrode and the lower electrode, and at least one of the upper electrode and the lower electrode is an SOI substrate. It may be characterized by comprising:

A charged particle beam exposure apparatus according to the present invention includes a charged particle source that emits a charged particle beam,
A correction electron optical system including the charged particle beam lens array according to any one of claims 1 to 7 and forming a plurality of intermediate images of the charged particle source, and projection electron optics for reducing and projecting the plurality of intermediate images onto an exposure target And a deflector for deflecting the plurality of intermediate images projected onto the exposure target so as to move on the exposure target.

  The present invention also relates to a method for producing a charged particle beam lens array in which an upper electrode, a middle electrode, and a lower electrode each having a plurality of openings are arranged in this order, and between the upper electrode and the middle electrode and the middle electrode. A step of forming the upper electrode, the middle electrode, and the lower electrode, respectively, wherein a surface of an insulator disposed on at least one of the lower electrodes has an uneven shape or a corrugated shape; and the upper electrode And the step of joining and integrating the middle electrode and the lower electrode.

Moreover, the device manufacturing method according to the present invention includes a step of exposing an exposure target using the exposure apparatus having any one of the above characteristics, and a step of developing the exposed exposure target. Features.

  According to the present invention, it is possible to provide an electron lens array with less crosstalk and capable of applying a high voltage with a simpler configuration.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.

<Electronic lens array>
An electronic lens array 500 according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1-1 is a conceptual diagram of an electron lens array 500, which shows a 3 × 3 array. The electron lens array 500 generally has a structure in which an upper electrode 521, a middle electrode 522, and a lower electrode 523, each having a plurality of openings, are sequentially stacked. Further, an upper shield electrode 524 integral with the upper electrode 521, and a lower shield electrode 525 integral with the lower electrode 523 are arranged so as to divide each opening into columns. Further, an insulator 526 having a concavo-convex shape or a corrugated shape is provided so as to electrically insulate the middle electrode 522 and the upper shield electrode 524 from each other. Similarly, the insulator 526 insulates the middle electrode 522 and the lower shield electrode 525 from each other. Details of the insulator 526 are shown in FIG. The insulator 526 has a plurality of grooves 527 parallel to the upper shield electrode 524 or the lower shield electrode 525, and the grooves 527 are concave. Further, the insulator 526 may be V-shaped as shown in FIG. 1-3. The upper electrode 521 has a thin film structure formed of a conductor, and a plurality of openings 528 are arranged in a lattice shape (centering on each intersection of vertical and horizontal virtual straight lines). The lower electrode 523 has the same configuration, and a plurality of openings 514 are formed at the same position as the opening 528 of the upper electrode 521. The middle electrode 522 is an electrically independent (insulated) electrode group for each column (y-axis direction). A plurality of openings 510 are formed at the same position as the openings 528 of the upper electrode 521. By matching the positions of the openings of the electrodes on a plane, the electron beam EB can be passed through the openings. Further, the upper shield electrode 524 and the upper electrode 521, the lower shield electrode 525 and the lower electrode 523 are integrated, and are configured to be electrically conductive and have the same potential. The upper electrode 521 and the lower electrode 523 are electrically grounded. Further, the middle electrode 522 has a voltage applying unit 515 independently for each of the A, B, and C columns.

  Next, the operation of the electron lens array 500 having the above configuration will be described. In the electron lens array 500, a potential of 0V is applied to the upper electrode 521 and the lower electrode 523, a potential of −1000V is applied to the A and B rows of the middle electrode 522, and −950V is applied to the C row of the middle electrode 522. Then, assuming that the adjacent potential difference between the B row and the C row is 50 V, the lens action on the electron beam is obtained independently for each row. At this time, the potentials of the upper shield electrode 524 and the upper electrode 521, and the lower shield electrode 525 and the lower electrode 523 are the same potential, which is 0V in the above case. In this case, since the insulator 526 has the groove 527 on the surface, the creepage distance d is increased without changing the outer dimension of the insulator 526, and the discharge between the upper shield electrode 524 and the middle electrode 522 is less likely to occur. ing. Therefore, the lens action can be increased by increasing the applied voltage. If the creepage distance d is increased by simply increasing the outer dimension of the insulator 526, there is a problem that the insulator 526 is easily visible from the electron beam EB due to the structure and charge-up is likely to occur. Therefore, if the size of the insulator 526 is minimized and the aspect ratio of the groove 527 provided in the insulator 526 is increased (for example, 2 or more), it becomes a structure in which both discharge and charge-up hardly occur, which is ideal. is there. Further, since the upper shield electrode 524 and the lower shield electrode 525 are provided so that the electric field is independent for each column, the electron lens array 500 with less crosstalk can be realized.

  In a charged particle beam lens array in which an upper electrode, a middle electrode, and a lower electrode each having a plurality of openings are sequentially stacked, insulation is performed between the upper electrode and the middle electrode and between the middle electrode and the lower electrode. By having a body and making the surface of the insulator uneven or corrugated, the creeping distance between the middle electrode and the upper electrode or the lower electrode can be increased. Therefore, creeping discharge is less likely to occur between the middle electrode and the upper electrode or the lower electrode, and as a result, a high voltage can be applied.

  In the charged particle beam lens array, since the middle electrode is electrically independent for each column of openings, the focal length for each particle beam can be controlled for each column.

  In the charged particle beam lens array, when the aspect ratio of the concavo-convex shape or the corrugated shape is 2 or more, the creepage distance between the middle electrode and the upper electrode or the lower electrode can be increased, and high voltage application can be achieved. It becomes possible.

  In the charged particle beam lens array, the upper electrode and the lower electrode each have a shield electrode that divides a space for each row of openings, so that crosstalk between the particle beams can be reduced.

  Next, the electron lens array 500 of the present invention will be described in detail according to the structure actually formed. 2-1 is a perspective view, FIG. 2-2 is a cross-sectional view taken along line AA ′ in FIG. 2-1, and FIG. 2-3 is a perspective view showing the lower electrode 523, the lower shield electrode 525, the middle electrode 522, and the insulator 526. It is. For simplicity, a 1 × 2 array is shown, but in practice several tens × several tens of arrays are formed. The upper electrode 521, the middle electrode 522, and the lower electrode 523 each having a plurality of openings are sequentially stacked. The upper electrode 521, the middle electrode 522, and the lower electrode 523 are manufactured from substrates made of different silicon or the like, and a conductor 504 whose surface is gold or the like is patterned. Further, the upper electrode 521, the middle electrode 522, and the lower electrode 523 are joined together through an insulator 526. Further, the upper shield electrode 524 and the upper electrode 521, and the lower shield electrode 525 and the lower electrode 523 are each made from the same substrate. The opening 528 has a diameter of 80 μm and a pitch of 200 μm. The configuration of each electrode and insulator is as described above. The electrodes are electrically insulated via an insulator 526 having a groove 527 having an aspect ratio of 2.5. The insulator 526 is made of a plate-like polyimide, silicon dioxide or the like having a substantially rectangular cross-section. Detailed dimensions are shown in Fig. 2-2. In this embodiment, the main dimensions are as follows: the width of the groove 527 is 2 μm, the depth of the groove 527 is 5 μm, the pitch of the grooves 527 is 4 μm, the width of the central insulator is 52 μm, and the adjacent opening 528 of the upper electrode 521. The inter-edge dimension is 120 μm, and the vertical dimension of the upper shield electrode 524 and the middle electrode 522 is 200 μm.

  In particular, since the electrode interval is directly related to the performance of the electron lens array 500, it is an important factor and is determined by a desired specification. In this embodiment, the electrode interval (separation dimension) is 210 μm.

  Next, another configuration of the electron lens array 500 according to the embodiment of the present invention will be described. 2-4 is a perspective view showing the lower electrode 523, the lower shield electrode 525, and the middle electrode 522 of the electron lens array 500 having another configuration. In the electron lens array 500 described above, each shield electrode is arranged so as to divide each opening into columns. Here, for example, as shown in FIG. 2-4, a cylindrical lower shield electrode 525 is provided. It is characterized by being formed independently for each opening. Further, the insulator 526 provided in the middle electrode 522 has a feature of having an independent circular groove 527 for each opening corresponding to the lower shield electrode 525. For this reason, the electric field tends to be symmetric with respect to the optical axis, and aberrations are easily reduced.

  That is, in the charged particle beam lens array, the upper electrode and the lower electrode have shield electrodes that divide the space for each opening, and the shield electrode is cylindrical, so that crosstalk between the particle beams can be reduced. . In addition, since the electric field in the aperture is symmetric with respect to the optical axis, it is advantageous for suppressing aberrations to a small value.

Next, a manufacturing method of the electron lens array 500 having the above structure will be described.
First, a method for manufacturing the middle electrode 522 will be described with reference to FIGS. 3-1 (a) to (f) and FIGS. 3-2 (g) to (k) which are cross-sectional views taken along line AA ′ in FIG. 2-1. . Again, for simplicity, a 1 × 2 array will be described. For example, it manufactures by performing the process shown to the following (1)-(11).

(1) A substrate 501 is prepared. The substrate 501 is made of single crystal silicon and has a thickness of, for example, 200 μm. The thickness is determined by the specifications of the electron lens. Next, silicon dioxide 507 having a film thickness of 1.5 μm is formed on the front and back surfaces of the substrate 501 by using a thermal oxidation method (FIG. 3A).

(2) The electrode layer 502 is formed on the surface by continuously depositing titanium / gold with a thickness of 5 nm / 100 nm, respectively. Moreover, the film thickness of titanium should just work of adhesion | attachment promotion, and is used in the range of several nm-several hundred nm. Further, gold used as the electrode layer 502 is used in the range of several tens of nm to several hundreds of nm. After that, photolithography is performed on the surface of the substrate 501 using a novolac resist to form an etching mask (not shown). Next, reactive ion etching (RIE) using Ar or Cl-based gas is performed to etch the electrode layer 502 made of gold. Thereafter, the resist is removed. This process is similarly performed on the back surface (FIG. 3B).

(3) A film or resin photosensitive polyimide is formed on the front and back surfaces of about 10 μm and patterned to form an insulator 526. (Fig. 3-1 (c)).

(4) Titanium / gold is continuously deposited on the front and back surfaces at a thickness of 5 nm / 100 nm, respectively, and patterned to form a bonding layer 529 (FIG. 3-1 (d)).

(5) A novolak resist is applied to a thickness of about 8 μm, and photolithography is performed to form a dry etching mask (not shown). Thereafter, reactive ion etching (RIE) using an O ₂ -based gas is performed, the insulator 526 made of polyimide is etched, and a groove 527 is formed. In order to process the groove 527 into a high aspect ratio structure, it is desirable that the RIE apparatus uses inductively coupled plasma having high perpendicularity. Thereafter, the resist is removed (FIG. 3-1 (e)).

(6) A novolak resist is applied to a thickness of about 10 μm, and photolithography is performed to form a dry etching mask. Thereafter, reactive ion etching (RIE) using a gas such as CF ₄ or CHF ₃ is performed, the silicon dioxide 507 is etched, and the substrate 501 made of Si is exposed. Subsequently, RIE using an inductively coupled plasma and a BOSCH process is performed on the substrate 501 which is silicon from the front surface to expose the silicon dioxide 507 on the back surface which is an etching stopper. Further, the silicon dioxide 507 on the back surface is removed by dry etching, and a through hole 531 is formed. Thereafter, the resist is removed (FIG. 3-1 (f)). Here, the BOSCH process is a method in which silicon is selectively etched with good anisotropy by alternately supplying an etching gas and a sidewall protection gas and switching between etching and sidewall protection. By using this type of RIE, an opening 531 having a high aspect ratio can be formed. Specifically, SF ₆ (sulfur hexafluoride) is used as an etching gas, C ₄ F ₈ (tetrafluorocarbon ₈ ) is used as a side wall protecting gas, RF power: 1800 W, bias power: 30 W, gas Flow rate: SF ₆ = 300 sccm (Standard Cubic Centimeter), C ₄ F ₈ = 150 sccm, SF ₆ / C ₄ F ₈ gas switching time: 7 seconds / 2 seconds, substrate temperature: 10 ° C., etching time: 40 minutes Etching is good.

(7) A film resist 508 having a thickness of about 20 μm is patterned, and parts other than the through-hole 531 are masked. Thereafter, silicon dioxide 509 is formed by sputtering to insulate the side wall of the through-hole 531 (FIG. 3-2 (g)).

(8) By removing the film resist 508, unnecessary portions of the silicon dioxide 509 are removed by lift-off to expose the insulator 526 (FIG. 3-2 (h)).

(9) The film resist 510 is newly patterned to expose the electrode layer 502 by about 10 μm. Next, a titanium / gold film is formed on the surface by sputtering at a thickness of 5 nm / 100 nm, respectively, to form an electrode layer 503 (FIG. 3-2 (i)). Here, the electrode layer 502 and the electrode layer 503 are electrically connected to each other on the surface of the substrate 501.

(10) By removing the film resist 510, unnecessary portions of the electrode layer 503 are removed by lift-off (FIG. 3-2 (j)).

(11) The steps (9) to (10) are similarly performed on the back surface (FIG. 3-2 (k)).

  Next, a method for manufacturing the upper electrode 521 and the lower electrode 523 will be described with reference to FIGS. 4A to 4F which are A-A ′ cross-sectional views in FIG. Again, for simplicity, a 1 × 2 array will be described. For example, it manufactures by performing the process shown to the following (1)-(6).

(1) A substrate 601 is prepared. The substrate 601 is an SOI substrate made of single crystal silicon, and the device layer 604, the BOX layer 606, and the support layer 605 have a thickness of 25 μm, 1 μm, and 200 μm, respectively, and have a thickness of 226 μm as a whole. The thickness is determined by the specifications of the electron lens. Next, about 1 μm of silicon dioxide 607 is formed on the back surface by sputtering (FIG. 4A).

(2) A novolak resist is applied to a thickness of about 10 μm, and photolithography is performed to form a dry etching mask (not shown). Subsequently, RIE using an inductively coupled plasma and a BOSCH process is performed on the substrate 601 that is silicon from the surface, and the BOX layer 606 made of silicon dioxide is exposed by an etching stopper. Thereafter, the resist is removed (FIG. 4B).

(3) A seed layer 602 is formed on the back surface by continuously depositing titanium / gold with a thickness of 5 nm / 100 nm, respectively. Gold used as the conductive layer is used in the range of several tens nm to several hundreds nm. A novolak resist 608 is applied to a thickness of about 15 μm, and photolithography is performed to form an electroplating mask. Thereafter, gold electroplating is performed using a cyan gold plating solution until the thickness reaches about 10 μm, thereby forming bonding bumps 628 (FIG. 4C).

(4) Next, after removing the resist 608, reactive ion etching using a gas such as argon is performed, and titanium / gold is etched to remove unnecessary portions of the seed layer 602 (FIG. 4D). .

(5) A novolac resist is applied on the back surface to a thickness of about 10 μm, and photolithography is performed to form a dry etching mask (not shown). Thereafter, reactive ion etching (RIE) using a gas such as CF ₄ or CHF ₃ is performed to etch the silicon dioxide 607 to expose the substrate 601 made of Si. Subsequently, RIE using an inductively coupled plasma and a BOSCH process is performed on the substrate 601 that is silicon from the surface to expose the BOX layer 608 that is an etching stopper. Further, the BOX layer 608 is removed by dry etching, and a through hole 631 is formed. Thereafter, the resist is removed (FIG. 4E).

(6) Titanium / gold is formed on the front and back surfaces by sputtering at a thickness of 5 nm / 100 nm, respectively, to form an electrode layer 603 (FIG. 4F).

  As described above, in the charged particle beam lens array, by manufacturing the upper electrode or the lower electrode from the SOI substrate, the BOX layer can be used as an etching stop layer, and the upper electrode or the lower electrode with high accuracy can be manufactured.

  Next, a method of integrating the upper electrode 521, the middle electrode 522, and the lower electrode 523 described above with reference to FIGS. 5A and 5B which are AA ′ sectional views in FIG. I will explain. For example, it manufactures by performing the process shown to the following (1)-(2).

(1) The upper electrode 521, the middle electrode 522, and the lower electrode 523 described above are prepared.

(2) The surface of the bonding layer 529 and the bonding bump 628 is cleaned by ion bombardment by exposing the back surface of the upper electrode 521 which is the bonding surface and the surface of the middle electrode 522 to plasma with argon gas. Thereafter, the upper electrode 521 and the middle electrode 522 are aligned, and a load is applied and bonded so that the stress applied to the bonding bump 628 is about 500 Mpa. When the bonding layer 529 and the bonding bump 628 are made of gold, the Au—Au room temperature bonding described above can be performed. When bonding is performed at room temperature, there is little need to consider the difference in coefficient of thermal expansion depending on the material, which is advantageous for substrate warpage and misalignment.

  An upper electrode, a middle electrode, and a lower electrode each having a plurality of openings are sequentially laminated, and an insulator is provided between the upper electrode and the middle electrode and between the middle electrode and the lower electrode. And forming the upper electrode, the middle electrode, and the lower electrode in a method for manufacturing a charged particle beam lens array, wherein the surface of the insulator has an uneven shape or a corrugated shape; By having the process of joining and integrating the electrode, the middle electrode and the lower electrode, a charged particle beam lens array with high fabrication accuracy can be produced by a micro-mechatronics technology based on a semiconductor process. realizable.

<Description of components of electron beam exposure apparatus>
An electron beam exposure apparatus to which the electron lens array according to the first embodiment can be applied will be described as a second embodiment of the present invention.

  FIG. 6 is a schematic diagram of a main part of the electron beam exposure apparatus according to the present embodiment. In FIG. 6, reference numeral 1 denotes an electron gun including a cathode 1a, a grid 1b, and an anode 1c. In the electron gun 1, electrons emitted from the cathode 1a form a crossover image between the grid 1b and the anode 1c (hereinafter, this crossover image is referred to as an electron source ES).

  The electrons emitted from the electron gun 1 become a substantially parallel electron beam EB by the condenser lens 2 whose front focal position is at the position of the electron source ES. The condenser lens 2 of the present embodiment has two sets (21, 22) of unipotential lenses composed of three aperture electrodes. The substantially parallel electron beam obtained by the condenser lens 2 enters the correction electron optical system 3. The correction electron optical system 3 includes an aperture array, a blanker array, a multi-charged beam lens, an element electron optical system array unit using the electron lens array described above, and a stopper array. Details of the correction electron optical system 3 will be described later.

  The correction electron optical system 3 forms a plurality of intermediate images of the light source, and each intermediate image is reduced and projected by a reduction electron optical system 4 described later to form a light source image on the wafer 5. At this time, the correction electron optical system 3 forms a plurality of intermediate images so that the interval between the light source images on the wafer 5 is an integral multiple of the size of the light source image. Further, the correction electron optical system 3 varies the position of each intermediate image in the optical axis direction according to the field curvature of the reduction electron optical system 4, and each intermediate image is reduced and projected onto the wafer 5 by the reduction electron optical system 4. Aberrations that occur during the correction are corrected in advance.

  The reduction electron optical system 4 includes two sets of symmetric magnetic tablets, and each symmetric magnetic tablet includes a first projection lens 41 (43) and a second projection lens 42 (44). When the focal length of the first projection lens 41 (43) is f1, and the focal length of the second projection lens 42 (44) is f2, the distance between the two lenses is f1 + f2. The object point on the optical axis AX is at the focal position of the first projection lens 41 (43), and the image point is connected to the focal point of the second projection lens 42 (44). This image is reduced to -f2 / f1. In addition, since the two lens magnetic fields are determined so as to act in opposite directions, theoretically, the five aberrations of spherical aberration, isotropic astigmatism, isotropic coma aberration, field curvature aberration, and axial chromatic aberration are determined. Except for aberrations, other Seidel aberrations and chromatic aberrations related to rotation and magnification are canceled out.

  A deflector 6 deflects a plurality of electron beams from the correction electron optical system 3 to displace a plurality of light source images on the wafer 5 by substantially the same amount of displacement in the X and Y directions. Although not shown, the deflector 6 includes a main deflector used when the deflection width is wide and a sub-deflector used when the deflection width is narrow. The main deflector is an electromagnetic deflector, and the sub deflector is an electrostatic deflector.

  Reference numeral 7 denotes a dynamic focus coil, which corrects the focus position shift of the light source image due to deflection aberration generated when the deflector 6 is operated. Reference numeral 8 denotes a dynamic stig coil which, like the dynamic focus coil 7, corrects astigmatism of deflection aberration caused by deflection.

  Reference numeral 9 denotes a θ-Z stage on which a wafer is placed and can move in the optical axis AX (Z-axis) direction and the rotation direction around the Z-axis. A stage reference plate 10 and a Faraday cup 13 are fixed to the θ-Z stage 9. The Faraday cup 13 detects the charge amount of the light source image formed by the electron beam from the correction electron optical system 3. Reference numeral 11 denotes an XY stage, which is a stage on which the θ-Z stage 9 is mounted and is movable in the XY direction orthogonal to the optical axis AX (Z axis). A reflected electron detector 12 detects reflected electrons generated when the mark on the stage reference plate 10 is irradiated with an electron beam.

  Next, the correction electron optical system 3 will be described with reference to FIG. 7A is a view of the correction electron optical system 3 as viewed from the electron gun 1 side, and FIG. 7B is a cross-sectional view taken along the line AA ′ of FIG.

  As described above, the correction electron optical system 3 includes the aperture array AA, blanker array BA, multi-charged beam lens ML, element electron optical system array unit LAU (ordered from the electron gun 1 side along the optical axis AX). LA1 to LA4) and a stopper array SA.

  The aperture array AA has a plurality of openings formed in a substrate, and divides a substantially parallel electron beam from the condenser lens 2 into a plurality of electron beams. The blanker array BA is formed by forming a plurality of deflecting means for individually deflecting a plurality of electron beams divided by the aperture array AA on a single substrate. The details of one of the deflecting means are shown in FIG. The substrate 31 has an opening AP. A blanking electrode 32 is composed of a pair of electrodes sandwiching the opening AP and has a deflection function. Further, wiring (W) for individually turning on / off the blanking electrode 32 is formed on the substrate 31.

  Returning to FIG. 7, the multi-charged beam lens ML is used in the correction electron optical system 3 to increase the charged beam convergence effect.

  The element electron optical system array unit LAU is a first electron optical system array which is the electron lens array according to the first embodiment of the present invention described above, which is formed by two-dimensionally arranging a plurality of electron lenses in the same plane. It is composed of LA1, a second electron optical system array LA2, a third electron optical system array LA3, and a fourth electron optical system array LA4.

  FIG. 9 is a diagram for explaining the first electron optical system array LA1. The first electron optical system array LA1 is a multi-electrostatic lens composed of three pieces of an upper electrode UE, an intermediate electrode CE, and a lower electrode LE in which a plurality of openings are arranged, and upper, middle, and lower electrodes arranged in the direction of the optical axis AX. This constitutes one electron lens EL1, a so-called unipotential lens. All the upper and lower electrodes of each electron optical system are connected at the same potential and set to the same potential (in this embodiment, the acceleration potential of the electron beam is set). The intermediate electrodes of the electron lenses arranged in the y direction are independently connected for each column by wiring (W). As a result, the potentials of the intermediate electrodes of the electron lenses arranged in the y direction can be individually set by the LAU control circuit 112 described later, whereby the optical characteristics of the electron lenses arranged in the y direction are set to be substantially the same. , Optical characteristics (focal lengths) for the respective electron lens groups arranged in the y direction are individually set. In other words, the electronic lenses arranged in the y direction and set to the same optical characteristic (focal length) are grouped together, and the optical characteristics (focal length) of the group arranged in the x direction orthogonal to the y direction are individually set. ing.

  FIG. 10 is a diagram for explaining the second electron optical system array LA2. The second electron optical system array LA2 is different from the first electron optical system array LA1 in that the intermediate electrodes of the electron lenses arranged in the x direction are independently connected to each other by wiring (W). As a result, the potential of each intermediate electrode of the electron lenses arranged in the x direction can be individually set by the LAU control circuit 112 described later, and the optical characteristics of the electron lenses arranged in the x direction are set to be substantially the same. The optical characteristics (focal length) for each group of electron lenses arranged in the direction are individually set. In other words, the electronic lenses arranged in the x direction and set to the same optical characteristic (focal length) are set as one group, and the optical characteristics (focal length) of the group arranged in the y direction are individually set.

  Since the third electron optical system array LA3 is the same as the first electron optical system array LA1, and the fourth electron optical system array LA4 is the same as the second electron optical system array LA2, their description is omitted. To do.

  Next, the action that the electron beam receives by the correction electron optical system 3 described above will be described with reference to FIG.

  The electron beams EB1 and EB2 divided by the aperture array AA are incident on the element electron optical system array unit LAU via different blanking electrodes. The electron beam EB1 passes through the electron lens EL11 of the first electron lens array LA1, the electron lens EL21 of the second electron lens array LA2, the electron lens EL31 of the third electron lens array LA3, and the electron lens EL41 of the fourth electron lens array LA4. Thus, an intermediate image img1 of the electron source is formed. On the other hand, the electron beam EB2 is an electron lens EL12 of the first electron lens array LA1, an electron lens EL22 of the second electron lens array LA2, an electron lens EL32 of the third electron lens array LA3, and an electron lens of the fourth electron lens array LA4. An intermediate image img2 of the electron source is formed via EL42.

  At this time, as described above, the electron lenses arranged in the x direction of the first and third electron lens arrays LA1 and LA3 are set to have different focal lengths, and the second and fourth electron lens arrays LA2, LA4 are set. The electron lenses arranged in the x direction are set to have the same focal length. Furthermore, the combined focal length of the electron lens EL11, electron lens EL21, electron lens EL31, and electron lens EL41 through which the electron beam EB1 passes, and the electron lens EL12, electron lens EL22, electron lens EL32, and electron through which the electron beam EB2 passes. The focal length of each electron lens is set so that the combined focal length of the lens EL42 is substantially equal. Thereby, the intermediate images img1 and img2 of the electron source are formed at substantially the same magnification. Further, in order to correct the field curvature that occurs when each intermediate image is reduced and projected onto the wafer 5 via the reduction electron optical system 4, the intermediate images img1 and img2 of the electron source according to the field curvature. Are formed in different positions in the optical axis AX direction.

  Further, when an electric field is applied to the passing blanking electrode, the electron beams EB1 and EB2 change their trajectories as shown by broken lines in the figure, and cannot pass through the openings corresponding to the respective electron beams of the stopper array SA. The beams EB1 and EB2 are blocked.

  Next, a system configuration diagram of this embodiment is shown in FIG. The BA control circuit 111 is a control circuit that individually controls on / off of the blanking electrodes of the blanker array BA, and the LAU control circuit 112 is a control circuit that controls the electro-optical characteristics (focal length) of the lens array unit LAU. It is.

  The D_STIG control circuit 113 is a control circuit that controls the astigmatism of the reduction electron optical system 4 by controlling the dynamic stig coil 8. The D_FOCUS control circuit 114 is a control circuit that controls the focus of the reduction electron optical system 4 by controlling the dynamic focus coil 7. The deflection control circuit 115 is a control circuit that controls the deflector 6. The optical characteristic control circuit 116 is a control circuit that adjusts optical characteristics (magnification, distortion, rotational aberration, optical axis, etc.) of the reduction electron optical system 4.

  The stage drive control circuit 118 is a control circuit that drives and controls the XY stage 11 in cooperation with the laser interferometer LIM that drives and controls the θ-Z stage 9 and detects the position of the XY stage 11.

  The control system 120 controls each control circuit described above based on data from the memory 121 in which the drawing pattern is stored. The control system 120 is controlled by a CPU 123 that controls the entire electron beam exposure apparatus via an interface 122.

<Explanation of exposure operation>
Next, with reference to FIG. 13, the exposure operation of the electron beam exposure apparatus according to this embodiment will be described.

  The control system 120 commands the deflection control circuit 115 based on the exposure control data from the memory 121, deflects a plurality of electron beams by the deflector 6, and commands the BA control circuit 111 to pattern the wafer 5 to be exposed. In response to this, the blanking electrodes of the blanker array BA are individually turned on / off. At this time, the XY stage 11 continuously moves in the y direction, and the deflector 6 deflects the plurality of electron beams so that the plurality of electron beams follow the movement of the XY stage.

  Each electron beam scans and exposes a corresponding element exposure region (EF) on the wafer 5 as shown in FIG. Since the element exposure area (EF) of each electron beam is set so as to be adjacent in two dimensions, as a result, a subfield (SF) composed of a plurality of element exposure areas (EF) that are exposed simultaneously is formed. Exposed.

  After exposing the subfield (SF1), the control system 120 instructs the deflection control circuit 115 to expose the next subfield (SF2), and the deflector 6 causes the direction orthogonal to the stage scanning direction (y direction). A plurality of electron beams are deflected in the (x direction). At this time, the aberration when each electron beam is reduced and projected via the reduction electron optical system 4 also changes due to the change of the subfield due to the deflection. Therefore, the control system 120 instructs the LAU control circuit 112, the D_STIG control circuit 113, and the D_FOCUS control circuit 114 to set the lens array unit LAU, the dynamic stig coil 8, and the dynamic focus coil 7 so as to correct the changed aberration. adjust. Then, as described above, the subfield (SF2) is exposed by exposing the element exposure region (EF) to which each electron beam corresponds. Then, as shown in FIG. 14, the subfields (SF1 to SF6) are sequentially exposed to expose the pattern on the wafer 5. As a result, on the wafer 5, a main field (MF) composed of subfields (SF1 to SF6) arranged in a direction (x direction) perpendicular to the stage scanning direction (y direction) is exposed.

  Further, after exposing the main field 1 (MF1) shown in FIG. 13, the control system 122 instructs the deflection control circuit 115 to sequentially enter the main fields (MF2, MF3, MF4...) Aligned in the stage scanning direction (y direction). A plurality of electron beams are deflected and exposed. As a result, as shown in FIG. 17, a stripe (STRIPE1) composed of main fields (MF2, MF3, MF4...) Is exposed.

  Then, the XY stage 11 is stepped in the x direction to expose the next stripe (STRIPE2).

  In a charged particle beam exposure apparatus, a charged particle source that emits a charged particle beam, a correction electron optical system that includes a charged particle beam lens array that forms a plurality of intermediate images of the charged particle source, and a plurality of intermediate images reduced to an exposure target By having a projection electron optical system to project and a deflector that deflects the plurality of intermediate images projected onto the exposure target to move on the exposure target, each intermediate image is transferred to the wafer or the like via the reduction electron optical system. It is possible to increase the throughput of the charged particle beam exposure apparatus by correcting the curvature of field that occurs when the image is reduced and projected onto the exposure object, and as a result, the drawing area is enlarged.

  Next, a semiconductor device manufacturing process using the exposure apparatus according to the above embodiment will be described. FIG. 16 is a diagram showing a flow of an entire manufacturing process of a semiconductor device. In step 1 (circuit design), a semiconductor device circuit is designed. In step 2 (EB data conversion), exposure control data for the exposure apparatus is created based on the designed circuit pattern.

  On the other hand, in step 3 (wafer manufacture), a wafer is manufactured using a material such as silicon. Step 4 (wafer process) is called a pre-process, and an actual circuit is formed on the wafer using lithography using the exposure apparatus and wafer to which the exposure control data has been input. The next step 5 (assembly) is called a post-process, and is a process for forming a semiconductor chip using the wafer produced in step 4, and is an assembly process (dicing, bonding), packaging process (chip encapsulation), etc. Process. In step 6 (inspection), the semiconductor device manufactured in step 5 undergoes inspections such as an operation confirmation test and a durability test. A semiconductor device is completed through these processes, and is shipped in Step 7.

  The wafer process in step 4 includes the following steps. An oxidation step for oxidizing the surface of the wafer, a CVD step for forming an insulating film on the wafer surface, an electrode formation step for forming electrodes on the wafer by vapor deposition, an ion implantation step for implanting ions on the wafer, and applying a photosensitive agent to the wafer The resist processing step, the exposure step for printing and exposing the circuit pattern onto the wafer after the resist processing step by the above-described exposure apparatus, the development step for developing the wafer exposed in the exposure step, and the etching for removing portions other than the resist image developed in the development step Step, resist stripping step to remove resist that is no longer needed after etching. By repeating these steps, multiple circuit patterns are formed on the wafer.

It is a perspective view which shows the concept of the electron lens array which concerns on the Example of this invention. It is a perspective view which shows the detail of the insulator which concerns on the Example of this invention. It is a perspective view which shows the modification of the insulator which concerns on the Example of this invention. It is a figure for demonstrating the electronic lens array which concerns on the Example of this invention. This is A-A 'in FIG. It is a perspective view which shows the lower electrode, lower shield electrode, middle electrode, and insulator which concern on the Example of this invention. It is a perspective view which shows another example of the lower electrode which concerns on the Example of this invention, a lower shield electrode, a middle electrode, and an insulator. It is a figure for demonstrating the manufacturing method of the middle electrode of the electronic lens array which concerns on the Example of this invention. It is a figure for demonstrating the manufacturing method of the middle electrode of the electronic lens array which concerns on the Example of this invention. It is a figure for demonstrating the preparation methods of the upper electrode and lower electrode of an electronic lens array which concern on the Example of this invention. It is a figure for demonstrating the manufacturing method of the electron lens array which concerns on the Example of this invention. It is a figure for demonstrating the optical system of the electron beam exposure apparatus which concerns on the Example of this invention. It is a figure which shows the correction | amendment electron optical system of the electron beam exposure apparatus which concerns on the Example of this invention. It is a figure for demonstrating the blanker array of the electron beam exposure apparatus which concerns on the Example of this invention. It is a figure for demonstrating the electron optical system array of the electron beam exposure apparatus which concerns on the Example of this invention. It is a figure for demonstrating the electron optical system array of the electron beam exposure apparatus which concerns on the Example of this invention. It is a figure for demonstrating the effect | action received with the correction | amendment electron optical system of the electron beam exposure apparatus which concerns on the Example of this invention. It is a figure for demonstrating the system configuration | structure of the electron beam exposure apparatus which concerns on the Example of this invention. It is a figure for demonstrating the exposure operation | movement of the electron beam exposure apparatus which concerns on the Example of this invention. It is a figure for demonstrating background art. It is a figure for demonstrating background art. It is a figure which shows the flow of the whole manufacturing process of a semiconductor device.

Explanation of symbols

AA: Aperture array, BA: Blanker array, ML: Multi-charged beam lens, LAU: Element electron optical system array unit, LA (LA1 to LA4): Electro optical system array, SA: Stopper array, UE: Upper electrode, CE: Intermediate electrode, LE: lower electrode, EL: electron lens, EB: electron beam, LIM: laser interferometer, AP: aperture, W: wiring,
1: electron gun, 2: condenser lens, 3: correction electron optical system, 4: reduction electron optical system, 5: wafer, 6: deflector, 7: dynamic focus coil, 8: dynamic stig coil, 9: θ-Z Stage: 10: Stage reference plate, 11: XY stage, 12: Backscattered electron detector, 13: Faraday cup, 21, 22: Unipotential lens, 31: Substrate, 32: Blanking electrode, 41, 43: First projection Lens, 42, 44: second projection lens, 111: BA control circuit, 112: LAU control circuit, 113: D_STIG control circuit, 114: D_FOCUS control circuit, 115: deflection control circuit, 116: optical characteristic control circuit, 117: Stage drive control circuit, 120: control system, 121: memory, 122: interface, 123: CPU, 300: Electronic lens array, 301: electrode, 302: fiber, 303: shield electrode, 400: electron lens array, 401: electrode, 403: shield electrode, 500: electron lens array, 501: substrate, 502: electrode layer, 503: electrode Layer, 504: conductor, 507: silicon dioxide, 508: film resist, 509: silicon dioxide, 510: film resist, 514: opening, 515: voltage applying means, 521: upper electrode, 522: middle electrode, 523: lower Electrode, 524: upper shield electrode, 525: lower shield electrode, 526: insulator, 527: groove, 528: opening, 529: bonding layer, 531: opening, 601: substrate, 603: electrode layer, 604: device layer, 605: support layer, 606: BOX layer, 607: silicon dioxide, 608: resist, 628: bonding bump 631: through-hole.

Claims (10)

In a charged particle beam lens array in which an upper electrode, a middle electrode, and a lower electrode each having a plurality of openings are sequentially arranged,
An insulator disposed between at least one of the upper electrode and the middle electrode and between the middle electrode and the lower electrode;
The charged particle beam lens array, wherein the surface of the insulator has an uneven shape or a wave shape.   The charged particle beam lens array according to claim 1, wherein the middle electrode is electrically independent for each row of the openings.   The charged particle beam lens array according to claim 1, wherein an aspect ratio of the uneven shape or the corrugated shape is 2 or more. Charged particle beam lens array according to claim 1, characterized in that it comprises a at least one of the electrode shield electrode for each column of said opening of said upper electrode and said lower electrode.   The charged particle beam lens array according to claim 4, wherein the shield electrode has a cylindrical shape.   6. The charged particle beam lens array according to claim 4, wherein the shield electrode is electrically connected to at least one of the upper electrode and the lower electrode. At least one of the electrodes, the charged particle beam lens array according to any one of claims 1 to 6, characterized in that it consists of an SOI substrate of the upper electrode and the lower electrode. A charged particle source emitting a charged particle beam;
A correction electron optical system including the charged particle beam lens array according to any one of claims 1 to 7, wherein a plurality of intermediate images of the charged particle source are formed.
A projection electron optical system for reducing and projecting the plurality of intermediate images onto an exposure target;
A charged particle beam exposure apparatus comprising: a deflector configured to deflect the plurality of intermediate images projected onto the exposure target so as to move on the exposure target. In a method of creating a charged particle beam lens array in which an upper electrode, a middle electrode, and a lower electrode each having a plurality of openings are sequentially arranged,
The surface of the insulator disposed between at least one of the upper electrode and the middle electrode and between the middle electrode and the lower electrode has a concavo-convex shape or a corrugated shape,
Forming the upper electrode, the middle electrode, and the lower electrode, respectively;
A method of manufacturing a charged particle beam lens array, comprising the step of joining the upper electrode, the middle electrode, and the lower electrode together.   A device manufacturing method comprising: a step of exposing an exposure target using the exposure apparatus according to claim 8; and a step of developing the exposed exposure target.

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