JP4537891B2 - Circuit pattern inspection apparatus and inspection method - Google Patents

Description

  The present invention relates to a pattern inspection technique for a substrate having a fine circuit pattern such as a semiconductor device or a liquid crystal, and more particularly to a pattern inspection technique on a wafer in the course of manufacturing a semiconductor device.

  A semiconductor wafer inspection will be described as an example. A semiconductor device is manufactured by repeating a process of transferring a pattern formed on a photomask on a semiconductor wafer by lithography and etching. In the manufacturing process of a semiconductor device, the quality of lithography processing, etching processing, and other defects and foreign matter generation greatly affect the yield of the semiconductor device. Therefore, in order to detect abnormalities and defects early or in advance, the semiconductor in the manufacturing process A method for inspecting a pattern on a wafer has been conventionally performed.

  As a method for inspecting defects present in patterns on a semiconductor wafer, a defect inspection apparatus that irradiates a semiconductor wafer with white light and compares the same kind of circuit patterns of a plurality of LSIs using an optical image has been put into practical use. The outline of the inspection method is described in Non-Patent Document 1. Moreover, in the inspection method using an optical image, as described in Patent Document 1, an optically illuminated region on a substrate is imaged by a time delay integration sensor, and the image and pre-input design characteristics are formed. As described in Patent Document 2, a method for detecting defects by comparing images and monitoring image degradation at the time of image acquisition and correcting it at the time of image detection enables comparative inspection with a stable optical image. A method of performing is disclosed. When a semiconductor wafer in the manufacturing process is inspected by such an optical inspection method, residues and defects of a pattern having a silicon oxide film or a photosensitive photoresist material on the surface through which light is transmitted cannot be detected. Moreover, the etching residue which is below the resolution of the optical system and the non-opening defect of the minute conduction hole could not be detected. Furthermore, a defect generated at the bottom of the step of the wiring pattern could not be detected.

  As described above, defect detection by optical images has become difficult as circuit patterns become finer, circuit pattern shapes become more complex, and materials diversify. Therefore, electron beam images with higher resolution than optical images are used. A method for comparing and inspecting circuit patterns has been proposed. In order to obtain a practical inspection time when comparing and examining circuit patterns using electron beam images, images are acquired at a much higher speed than observation with a scanning electron microscope (hereinafter abbreviated as SEM). There is a need. And it is necessary to ensure the resolution of the image acquired at high speed and the SN ratio of the image.

  Non-Patent Document 2, Non-Patent Document 3, and Patent Document 3 and Patent Document 4 have electron beam currents of 100 times or more (10 nA or more) of ordinary SEM as a pattern inspection inspection apparatus using an electron beam. Electrons are irradiated onto a conductive substrate (X-ray mask, etc.), any secondary electrons, reflected electrons, or transmitted electrons generated are detected, and defects are automatically detected by comparing and inspecting the image formed from the signals. A method of detecting is disclosed.

  In addition, as a method for inspecting or observing a circuit board having an insulator with an electron beam, Patent Document 5 and Non-Patent Document 4 describe a stable method using low acceleration electron beam irradiation of 2 keV or less in order to reduce the influence of charging. A method for acquiring an image is disclosed. Further, Patent Document 6 discloses a method of irradiating ions from the back of a semiconductor substrate, and Patent Document 7 discloses a method of canceling the charge on the insulator by irradiating the surface of the semiconductor substrate with light.

  Moreover, it is difficult to obtain a high-resolution image due to the space charge effect with an electron beam with a large current and a low acceleration. As a method for solving this, Patent Document 3 discloses that a high-acceleration electron beam is used immediately before the sample. A method of slowing down and irradiating the sample as a substantially low acceleration electron beam is disclosed.

  As a method for acquiring an electron beam image at high speed, Patent Document 8 and Patent Document 3 disclose a method in which an electron beam is continuously irradiated and acquired on a semiconductor wafer on a sample table while the sample table is continuously moved. . In addition, as a secondary electron detection device that has been used in the conventional SEM, a configuration using a scintillator (aluminum-deposited phosphor), a light guide, and a photomultiplier tube is used. Since light emission by the phosphor is detected, the frequency response is poor and it is inappropriate for forming an electron beam image at high speed. In order to solve this problem, Patent Document 3 discloses a detection means using a semiconductor detector as a detection device for detecting a high-frequency secondary electron signal.

Japanese Unexamined Patent Publication No. 3-167456 Japanese Patent Publication No. 6-58220 JP-A-5-258703 U.S. Pat.No. 5,502,306 JP 59-155941 Japanese Patent Laid-Open No. 2-15546 JP-A-6-338280 JP 59-160948 Monthly Semiconductor World, August 1995, pages 96-99 J. Vac. Sci. Tech. B, Vol.9, No.6, pp.3005-3009 (1991) J. Vac. Sci. Tech. B, Vol.10, No.6, pp.2511-2515 (1992) "Electron and ion beam handbook" (Nikkan Kogyo Shimbun) 622-623

  There is a technique for stabilizing the charged state of a wafer by irradiating a charged particle beam before the wafer inspection. Due to the structure of the wafer, a wafer in which the charge is lost immediately after irradiation with the charged particle beam needs to be irradiated with the charged particle beam immediately before the inspection in order to improve the defect detection rate. In the conventional apparatus, the charged particle beam is irradiated before the wafer inspection, or the charged particle beam irradiation is executed for each inspection stripe, the charged state becomes unstable before the inspection, and the defect detection rate decreases. In addition, there is a problem that the total inspection time becomes long.

  The present invention has been made in view of the above points, and improved the charged particle irradiation means and the detection and imaging means of the wafer appearance inspection apparatus to form an effective charged state and improve the defect detection rate. It is an object of the present invention to provide a circuit pattern inspection apparatus and inspection method with reduced time.

Specifically, the present invention provides the following apparatuses and methods.
The present invention relates to an irradiation means for irradiating a charged particle beam focused on a substrate surface on which a circuit pattern of a wafer is formed, a detection means for detecting a signal generated from the substrate by the irradiation, and a detection means detected by the detection means. Storage means for imaging and storing a signal; comparison means for comparing the stored image with an image formed from another identical circuit pattern; and determination means for determining a defect on the circuit pattern from the comparison result in the inspection apparatus for circuit pattern and means for detecting and means for irradiating a plurality of times the same scanning line in the focused charged particle beam, a signal generated every irradiation of the plurality of times, the plurality of times without using the imaging part of the times of the signals of the signal generated for each irradiation, Oyo inspection apparatus for circuit pattern having a means for using a signal from the outside portion of times times the imaging ,
Irradiating the same scanning line with the focused charged particle beam a plurality of times, detecting a signal generated by the plurality of times of irradiation, and based on a signal of a part of the signals generated by the plurality of times of irradiation. A method for inspecting a circuit pattern to be imaged is provided.

The present invention relates to an irradiation means for irradiating a charged particle beam focused on a substrate surface on which a circuit pattern of a wafer is formed, a detection means for detecting a signal generated from the substrate by the irradiation, and a detection means detected by the detection means. Storage means for imaging and storing a signal; comparison means for comparing the stored image with an image formed from another same circuit pattern; and determination means for determining a defect on the circuit pattern from the comparison result; in the inspection apparatus for circuit pattern with a chromatic and means for irradiating a plurality of times the same scanning line in the focused charged particle beam, and means for imaging an image signal detected by the irradiation of the charged particle beam The charged state of the substrate is stabilized by scanning one of the charged particle beams irradiated a plurality of times, and the plurality of times of irradiation performed on the substrate with the charged state stabilized. The image signals detected by other scanning out to provide an inspection apparatus for circuit pattern having a means for imaging.

According to the present invention, a stable charged state is formed by having a function of irradiating the same scanning line with a charged particle beam a plurality of times immediately before signal detection and imaging a signal generated from the plurality of irradiations. Thus, a defect detection rate can be improved and a circuit pattern inspection method and apparatus with good throughput can be provided.

An embodiment of the present invention includes an irradiating unit that irradiates a charged particle beam focused on a substrate surface on which a circuit pattern of a wafer is formed, a detecting unit that detects a signal generated from the substrate by the irradiation, and the detecting unit. Storage means for imaging and storing the detected signal, comparison means for comparing the stored image with an image formed from another identical circuit pattern, and a defect on the circuit pattern is determined from the comparison result A circuit pattern inspection apparatus including a discriminating unit, which constitutes a circuit pattern inspection apparatus having a function of irradiating the same scanning line by a return operation of irradiating a charged particle beam.

  The present invention provides an irradiation means for irradiating a charged particle beam onto a substrate surface on which a circuit pattern of a wafer is formed, a detection means for detecting a signal generated from the substrate by the irradiation, and an image of a signal detected by the detection means. And storing means for storing and storing, comparing means for comparing the stored image with an image formed from another identical circuit pattern, and determining means for determining a defect on the circuit pattern from the comparison result A circuit pattern inspection apparatus, which is a circuit pattern inspection apparatus having a function of irradiating a next inspection position by a return operation of irradiating a charged particle beam.

  Hereinafter, an example of an inspection method and an apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a configuration example of a circuit pattern inspection apparatus 1 of the present invention using a charged particle beam. The circuit pattern inspection apparatus 1 includes an inspection chamber 2 in which the chamber is evacuated, and a spare chamber (not shown in the present embodiment) for transporting the substrate 9 to be inspected into the inspection chamber 2. The spare chamber is configured to be evacuated independently of the examination chamber 2. The circuit pattern inspection apparatus 1 includes a control unit 5 and an image processing unit 6 in addition to the inspection room 2 and the spare room. The inspection chamber 2 is roughly divided into an electron optical system 3, a secondary electron detection unit 7, a sample chamber 8, and an optical microscope unit 4. The electron optical system 3 includes an electron gun 10, an electron beam extraction electrode 11, a condenser lens 12, a blanking deflector 13, a scanning deflector 15, an aperture 14, an objective lens 16, a reflecting plate 17, and an ExB deflector 18. Yes. Of the secondary electron detector 7, the secondary electron detector 20 is disposed above the objective lens 16 in the examination room 2. The output signal of the secondary electron detector 20 is amplified by a preamplifier 21 installed outside the examination room 2 and converted into digital data by an AD converter 22.

The sample chamber 8 includes a sample stage 30, an X stage 31, a Y stage 32, a rotary stage 33, a position monitor length measuring device 34, and a substrate height measuring device 35 to be inspected. The optical microscope unit 4 is installed in the vicinity of the electron optical system 3 in the examination room 2 and at a position that does not affect each other, and the distance between the electron optical system 3 and the optical microscope unit 4 Is known. Then, the X stage 31 or the Y stage 32 reciprocates a known distance between the electron optical system 3 and the optical microscope unit 4. The optical microscope unit 4 includes a white light source 40, an optical lens 41, and a CCD camera 42. The image processing unit 6 includes a storage unit 45, an image processing circuit 46, a defect data buffer 47, and a calculation unit 48. The captured electron beam image or optical image is displayed on the monitor 50. Operation commands and operation conditions of each part of the apparatus are input from the control unit 5. In the control unit 5, conditions such as an acceleration voltage at the time of generating an electron beam, an electron beam deflection width, a deflection speed, a signal acquisition timing of a secondary electron detector, a sample stage moving speed, etc. are arbitrarily or arbitrarily selected according to the purpose. It is input so that it can be set. The control unit 5 uses the scanning signal generator 43 provided with the correction control circuit to monitor the position and height deviation from the signals of the position monitor length measuring device 34 and the inspected substrate height measuring device 35, and as a result. to generate more correction signal and sends a correction signal to the objective lens 1 6 and scanning deflector 15 so that the electron beam is irradiated is always the correct position.

In order to acquire an image of the substrate 9 to be inspected, the primary electron beam 19 that is narrowed down is irradiated onto the substrate 9 to be inspected to generate secondary electrons 51, which are the scanning and stage of the primary electron beam 19. By detecting in synchronization with the movement of the X31 and Y stage 32, an image of the surface of the inspected substrate 9 is obtained. An automatic inspection apparatus must have a high inspection speed. Therefore, unlike an ordinary SEM, an electron beam with an electron beam current of the pA order is scanned at a low speed, and multiple scans and superposition of each image are not performed. Further, in order to suppress charging of the insulating material, it is necessary to scan the electron beam once or several times at a high speed. In this embodiment, therefore, an image is formed by scanning a high-current electron beam of about 100 times or more, for example, 100 nA, for example, about once or several times compared with a normal SEM. The scanning width was 100 μm, one pixel was 0.1 μm ^□, and one scan was performed in 1 μs.

  The electron gun 10 uses a diffusion replenishment type thermal field emission electron source. By using this electron gun 10, it is possible to secure a stable electron beam current as compared with, for example, a conventional tungsten (W) filament electron source or a cold field emission electron source. An image is obtained. Further, since the electron beam current can be set large by the electron gun 10, high-speed inspection as described later can be realized. The primary electron beam 19 is extracted from the electron gun 10 by applying a voltage between the electron gun 10 and the electron beam extraction electrode 11. The primary electron beam 19 is accelerated by applying a high-voltage negative potential to the electron gun 10. As a result, the primary electron beam 19 travels in the direction of the sample stage 30 with energy corresponding to the potential, is converged by the condenser lens 12, and is further narrowed down by the objective lens 16 to be XY stage 31 on the sample stage 30. The substrate 9 to be inspected (a substrate having a fine circuit pattern such as a semiconductor wafer, a chip or a liquid crystal, a mask) mounted on the substrate 32 is irradiated. The blanking deflector 13 is connected to a scanning signal generator 43 that generates a scanning signal and a blanking signal, and the condenser lens 12 and the objective lens 16 are connected to a lens power source 44, respectively. A negative voltage can be applied to the substrate 9 to be inspected by a retarding power source 36. By adjusting the voltage of the retarding power source 36, the primary electron beam is decelerated, and the electron beam irradiation energy to the substrate 9 to be inspected can be adjusted to an optimum value without changing the potential of the electron gun 10.

  Secondary electrons 51 generated by irradiating the substrate 9 to be inspected with the primary electron beam 19 are accelerated by a negative voltage applied to the substrate 9 to be inspected. The ExB deflector 18 is disposed above the substrate 9 to be inspected, and the secondary electrons 51 accelerated thereby are deflected in a predetermined direction. The amount of deflection can be adjusted by the voltage applied to the ExB deflector 18 and the strength of the magnetic field. The electromagnetic field can be varied in conjunction with a negative voltage applied to the sample. The secondary electrons 51 deflected by the ExB deflector 18 collide with the reflection plate 17 under a predetermined condition. The reflection plate 17 has a conical shape integrally with a shield pipe of a deflector of an electron beam (hereinafter referred to as a primary electron beam) irradiated on a sample. When the accelerated secondary electrons 51 collide with the reflection plate 17, second secondary electrons 52 having energy of several V to 50 eV are generated from the reflection plate 17.

  The secondary electron detector 7 includes a secondary electron detector 20 in the evacuated examination chamber 2, and a preamplifier 21, an AD converter 22, a light conversion means 23, and a light transmission means 24 outside the examination room 2. , Electrical conversion means 25, high-voltage power supply 26, preamplifier drive power supply 27, AD converter drive power supply 28, and reverse bias power supply 29. As already described, in the secondary electron detector 7, the secondary electron detector 20 is disposed above the objective lens 16 in the examination room 2. The secondary electron detector 20, the preamplifier 21, the AD converter 22, the light conversion means 23, the preamplifier drive power supply 27, and the AD converter drive power supply 28 are floated to a positive potential by the high voltage power supply 26. The second secondary electrons 52 generated by colliding with the reflecting plate 17 are guided to the secondary electron detector 20 by this attractive electric field. The secondary electron detector 20 is a second secondary electron generated when the secondary electron 51 generated while the primary electron beam 19 is irradiated on the substrate 9 to be inspected is then accelerated and collides with the reflecting plate 17. 52 is detected in conjunction with the scanning timing of the primary electron beam 19. The output signal of the secondary electron detector 20 is amplified by a preamplifier 21 installed outside the examination room 2 and converted into digital data by an AD converter 22. The AD converter 22 is configured to immediately convert the analog signal detected by the secondary electron detector 20 into a digital signal after being amplified by the preamplifier 21 and transmit the digital signal to the image processing unit 6. Since the detected analog signal is digitized immediately after detection and then transmitted, a signal having a higher speed and a higher S / N ratio can be obtained.

  A substrate 9 to be inspected is mounted on the X stage 31 and the Y stage 32, and when the inspection is executed, the X stage 31 and the Y stage 32 are stationary and the primary electron beam 19 is scanned two-dimensionally. One of the methods of scanning the primary electron beam 19 in a straight line in the X direction by continuously moving the X stage 31 and the Y stage 32 in the Y direction at a constant speed can be selected. When inspecting a specific relatively small area, the former stage is inspected with the stationary stage, and when inspecting a relatively large area, the stage is continuously moved at a constant speed and inspected. It is. When the primary electron beam 19 needs to be blanked, the blanking deflector 13 deflects the primary electron beam 19 so that the electron beam does not pass through the diaphragm 14. As the position monitor length measuring device 34, a length measuring device based on laser interference is used in this embodiment. The positions of the X stage 31 and the Y stage 32 can be monitored in real time and transferred to the control unit 5. Similarly, data such as the rotational speeds of the motors of the X stage 31, the Y stage 32, and the rotary stage 33 is also transferred from each driver to the control unit 5, and the control unit 5 stores these data. The region and position where the primary electron beam 19 is irradiated can be accurately grasped based on the above, and the displacement of the irradiation position of the primary electron beam 19 is corrected in real time as necessary. Correction is performed by the signal generator 43. In addition, the region irradiated with the electron beam can be stored for each substrate to be inspected.

  As the inspected substrate height measuring device 35, an optical measuring device that is a measuring method other than an electron beam, for example, a laser interference measuring device or a reflected light measuring device that measures changes at the position of reflected light is used. The height of the substrate 9 to be inspected mounted on the Y stage 31 and 32 is measured in real time. In this embodiment, the inspected substrate 9 is irradiated with the elongated white light that has passed through the slit through the transparent window, the position of the reflected light is detected by the position detection monitor, and the amount of change in height is determined from the change in position. The calculation method was used. Based on the measurement data of the inspected substrate height measuring device 35, the focal length of the objective lens 16 for narrowing the primary electron beam 19 is dynamically corrected, and the primary electron beam 19 always focused on the non-inspection region. Can be irradiated. It is also possible to measure the warpage and height distortion of the inspected substrate 9 before electron beam irradiation, and to set correction conditions for each inspection region of the objective lens 16 based on the data. It is.

  The image processing unit 6 includes a storage unit 45, an image processing circuit 46, a defect data buffer 47, a calculation unit 48, and an overall control unit 49. The image signal of the inspected substrate 9 detected by the secondary electron detector 20 is amplified by the preamplifier 21, digitized by the AD converter 22, converted into an optical signal by the light conversion means 23, and light transmission means 24, is converted into an electric signal again by the electric conversion means 25, and then stored in the storage means 45. The image processing circuit 46 uses the stored image signal to perform alignment between the images that are apart from a specific position, normalize the signal level, and perform various image processing for removing the noise signal, and perform a comparison operation on the image signal. To do. The absolute value of the difference image signal that has been subjected to the comparison operation is compared with a predetermined threshold value. If the difference image signal level is greater than the predetermined threshold value, the pixel is determined as a defect candidate, and the position and Displays the number of defects.

The control unit 5, the X-Y stage 31 moves chip pitch, it is possible to obtain an image of the same point of comparison chip inspection chip of the substrate to be inspected 9. Control unit 5, based on the shading difference of the same point of comparison chip inspection chip, is greater than a predetermined threshold value, it is determined that there is a defect in the examined points of the inspection chip.

  FIG. 2 is a diagram illustrating a configuration example of the monitor unit. The monitor screen is roughly divided into five areas. The area (1) is arranged at the upper part of the screen, and the device name, device ID, recipe file name, process file name, etc. are displayed as the recipe name. In the area (2), guidance for explaining operations and states is displayed. The area (3) in the center of the screen includes a map display unit 55 and an image display unit 56, and the display contents change depending on the operation and progress state. In the area (4) on the right side of the screen, operation buttons that are commonly required for a plurality of screens are displayed, and there are “print”, “file save”, “start”, “end”, “image save”, and the like. For example, when “Save File” is pressed, a screen for designating the name of the product file and process file for saving the recipe currently being created is displayed. When “Save Image” is pressed, a screen for designating a name for saving the currently displayed image as an image file is displayed. The mode name is displayed in the operation area (5) at the bottom of the screen. For example, when “inspection” is pressed, the automatic inspection is executed, and when “recipe creation” is pressed, the above parameters are entered.

  Next, a recipe creation method will be described. FIG. 3 shows a processing flow of the recipe creation mode. When the “recipe creation” mode is selected on the initial screen of FIG. 2, the mode switching means 60 functions and switches to the recipe creation screen shown in FIG. Since the start button is pressed on this screen and the cassette shelf number is displayed, the shelf number is first designated (S1). Next, the recipe file is called, and the new or changed product condition, lot ID, and wafer ID are input (S2). This change is a change in recipe creation conditions, regardless of whether or not it is loaded, and is mainly a load change. In addition, since recipes of other devices to be described later cannot be directly input, an inspection result file (defect information file: the contents of this file is disclosed to the user) is input, converted, and a recipe for the own device And change in this step to make up for the missing data.

  Here, the wafer cassette is newly created, and then the wafer cassette is installed in the loader of the inspection apparatus (S3). As processing items, (1) OF or notch is detected, (2) is held in the sample holder (sample exchange chamber), and (3) the sample holder is transferred to the examination room stage. Next, the stage is moved to the stage reference mark, and absolute calibration of the beam is performed (S4). Here, calibration is performed based on default recipe file conditions, and (1) beam irradiation, (2) deflection correction, reference coordinate correction, and (3) focus parameter correction are performed. Next, the designated position on the sample is irradiated with an electron beam, and after confirming the image contrast on the sample, the focus and astigmatism are readjusted (S5). At this time, if sufficient contrast cannot be obtained, the electron beam irradiation conditions are changed. Here, the designated irradiation conditions, focal points, and astigmatic conditions are stored as recipe parameters in the process file.

  When the electron beam irradiation conditions are determined and the contrast is confirmed, the shot of the wafer and the size and arrangement of the die (chip) are input (S6). When the shot size and the shot matrix are input and the arrangement of the dies in the shot is input, the shot on the wafer peripheral portion or the presence / absence of the die is designated. The shot and die arrangement set here are stored as parameters in the recipe file.

  Next, alignment condition input and alignment are executed (S7). Specifically, (1) Specify alignment chip (multiple points), (2) Move to the origin of the first chip, (3) Switch the optical microscope monitor, (4) Manually move to the alignment mark position of the first chip To do. (5) An optical image is registered, (6) SEM image mode is switched, (7) Fine adjustment is manually performed to the alignment mark position, (8) SEM image registration, and (9) Alignment coordinate registration are performed. As items for alignment execution, (1) first point movement, (2) image input / search / matching, (3) second point movement, (4) image input / search / matching, (5) remaining point (6) Inclination / position / chip interval correction.

  Also, as offset setting of the chip origin, (1) move to the last point alignment mark, (2) specify the alignment mark position (SEM image mode), (3) move to the first chip origin, (4) specify the chip origin position (SEM image mode), (5) Chip origin-alignment mark offset calculation and registration. The offset of the chip origin is the distance between the alignment coordinates and the origin coordinates of the chip where the mark is located.

  In this way, the offset value between the designated alignment pattern coordinates and the chip origin is input and registered as an alignment parameter in the process file. In recipe creation, since there are many parameters for specifying coordinates for executing various processes on the wafer, alignment conditions are first determined and registered, and the process is executed up to alignment.

  Next, the memory cell area in the chip is set (S8). The items include (1) cell area input, (2) cell pitch input, and (3) (1), (2) registration. The cell area is input using an optical microscope image and an electron beam image. Next, die area setting is performed (S9). The items include (1) die area input, (2) die non-inspection area input, and (3) (1) and (2) registration. The die area is also input using an optical microscope image and an electron beam image.

  Next, an inspection area is designated (S10). In specifying the inspection area, two types of inspection area and inspection area in the die can be specified. When it is not necessary to inspect all the dies, or when it is desired to inspect only a specific area in the die, it can be arbitrarily designated as described later. Furthermore, the inspection sampling rate can be specified for the specified area. Also, the inspection direction can be specified. Die area and inspection area data are stored as parameters in the process file.

  When the specification of the inspection area is completed, the process proceeds to calibration setting for adjusting the brightness at the time of inspection (S11). In calibration, an image is acquired, and hardware gain adjustment and brightness correction are performed according to the signal amount from the brightness distribution. Actually, it is carried out by specifying a die to be calibrated and coordinates within the die. The coordinate value for performing calibration, the gain of brightness, and the offset value are stored as parameters in the process file.

  Next, an image is actually acquired under various conditions set so far, and image processing conditions for detecting defects are set (S12). First, when acquiring an image, the type of filter to be applied to the detection signal is selected. Then, an image of a small area in one chip is actually acquired under the same conditions as the inspection. Here, the small area refers to an area having a width of 100 μm, which is the scanning width of an electron beam, and a length corresponding to one chip. When the image is acquired, a threshold value for determining a defect is input, and an image of a portion determined to be a defect is displayed. By repeating this, the optimum inspection condition is determined. This series of operations is called “small area test inspection”. The parameters such as the threshold value and file set here are stored as parameters of the in-process file.

  Various parameters necessary for the inspection can be set by the above various inputs. However, in actual semiconductor wafers, there are process variations within the wafer surface and between production lots, so setting image processing conditions in the small area test inspection is not sufficient. It is necessary to determine a threshold value.

  Therefore, the final inspection is performed with the created recipe file (S13). That is, (1) stage constant continuous movement, position / height monitoring, (2) beam scanning, real time correction (stage / Z sensor tracking), (3) secondary electron detection, AD conversion, image memory (4) Image processing and comparison determination, (5) Beam correction for each N stripe, and (6) Display of defect number and defect position. Based on the monitor result, the defect detection level and the false detection level are confirmed (S14). If the conditions are finally appropriate, various parameters input so far are registered in the product file and the process file (S15). . Finally, the wafer is unloaded (S16).

  In the present invention, the step (S8) of setting the memory cell area in the recipe-created chip is improved to enable setting of cell areas having a plurality of different cell pitches and setting of the cell pitch.

  The charged particle beam irradiation means and signal detection will be described with reference to FIG. 4A is an overall schematic diagram of the wafer to be inspected, and FIG. 4B is an enlarged schematic diagram of the chip A. FIG.

An embodiment of the present invention will be described with reference to FIGS. FIG. 5 is an enlarged schematic view of the cell B in FIG. While moving the stage, a charged particle beam is irradiated by executing a beam scan in a direction orthogonal to the stage moving direction. In the conventional technology, as shown in FIG. 6A, one signal is detected by one irradiation, and the inspection is executed by imaging the signal. Alternatively, as shown in FIG. 6B, a plurality of signals are added in order to improve the S / N. To stabilize the charged state of the wafer not only S / N improving illumination of multiple charged particle beams in the present embodiment, as shown in FIG. 6 (c), 4 times to the image of one line When the charged particle beam is irradiated by executing the beam scan, the third beam scan is used to form a stable wafer charged state, and only the signal generated by the last charged particle beam irradiation is obtained. Detect and image. Also, as shown in FIG. 6D, the first and second beam scans are used to form a stable wafer charged state, and are signals generated by the third and fourth charged particle beam irradiations. Is added to improve the S / N and image.

That is, inspection apparatus for circuit patterns of this embodiment, a means for irradiating a plurality of charged particle beams focused by the same scan line times, means for detecting a signal that occurs each its multiple radiations, its without using the imaging part of the times of the signals of the signal generated for each of the plurality of times of irradiation, a means for using the times of the signal other than the part of every imaging, a.

Alternatively, the circuit pattern inspection apparatus of the present embodiment includes means for irradiating the same scanning line with a focused charged particle beam a plurality of times, and means for imaging an image signal detected by the irradiation of the charged particle beam. The charged state of the substrate is stabilized by scanning one of the charged particle beams irradiated a plurality of times, and the other of the plurality of times of irradiation performed on the substrate whose charged state is stabilized An image signal detected by scanning is imaged .

A process of imaging only a specific signal from a signal detected a plurality of times will be described with reference to FIG.

First, image processing for realizing the present invention will be described. The calculation unit 48 converts the recipe information set from the overall control unit 49 into inspection information for the image processing circuit, and sets it in the image processing circuit 46 (position shift detection unit, defect determination unit, and defect analysis unit). 1-dimensional image data that are sequentially acquired while moving the stage is transferred to the images processing circuit 46 via the storage unit 45. The image processing circuit 46 performs cell comparison processing while acquiring image data from the storage unit 45 according to the inspection information, and determines defect coordinates and defect data. The determined defect data is stored in the defect data buffer.

A detection mode indicating a condition to be detected as recipe information is sent from the overall control unit 49 to the calculation unit 48. Detection mode, as shown below, by irradiating once charged particle beam, the mode for detecting and imaging the one signal as 1, imaging 1 and second signals by irradiating twice The mode to perform is defined as 2.

Detection mode 1 (Once irradiation, the first detection signal is imaged)
Detection mode 2 (Two irradiations are used to image the first and second detection signals)
Detection mode 3 (2nd detection signal is imaged by 2 exposures)
:
For example, when imaging only the second detection signal after irradiation twice, the recipe information of the detection mode 3 is sent from the overall control unit 49 to the calculation unit 48.

Under this condition, the same scanning line is irradiated with the charged particle beam twice, and a signal for two times is detected as a signal. Only the second data of the signal data for two times is imaged and sent to the image processing circuit 46 for processing.

For example, when the same scanning line is irradiated with the charged particle beam four times and only the third and fourth signals are imaged, the signal data for two times is added by the calculation unit 48.

A function of irradiating the same scanning line in the return operation (charging stabilization operation) irradiated with the charged particle beam will be described with reference to FIG. First executes the return at the second charged particle beam irradiation of the charged particle beam irradiation as shown in FIG.

With reference to FIG. 8B, a function of irradiating the next scanning line in the return operation (charging stabilization operation) irradiated with the charged particle beam will be described. Executing a charged particle beam irradiation of the second line is the next scan line when the return of the first line of the charged particle beam irradiation as shown in FIG.

  By using the return operation of the two charged particle beam irradiations, the charged particle beam irradiation time can be shortened, and the inspection time can be shortened as a whole.

As described above, according to the present embodiment, a stable function is achieved by irradiating the same scanning line with a charged particle beam a plurality of times immediately before signal detection and imaging a signal generated at each of the plurality of irradiations. It is possible to provide a circuit pattern inspection method and apparatus with improved throughput by forming a charged state and improving the throughput.

The block diagram of the circuit pattern inspection apparatus using the charged particle which concerns on this invention. The block diagram of the monitor part of the circuit pattern inspection apparatus which concerns on this invention. The flowchart which shows the recipe creation process of the circuit pattern inspection apparatus which concerns on this invention. Explanatory drawing of the test | inspection operation | movement which concerns on this invention. The figure which shows the irradiation means of the charged particle beam which concerns on this invention. An explanatory view of signal detection. Explanatory drawing of the signal detection by the image processing which concerns on this invention, and an imaging process. Explanatory drawing of the irradiation means of the charged particle beam which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Circuit pattern inspection apparatus, 2 ... Examination room, 3 ... Electron optical system, 4 ... Optical microscope part, 5 ... Control part, 6 ... Image processing part, 7 ... Secondary electron detection part, 8 ... Sample room, 9 ... substrate to be inspected, 10 ... electron gun, 11 ... electron extraction electrode, 12 ... condenser lens, 13 ... blanking deflector, 14 ... diaphragm, 15 ... scanning deflector, 16 ... objective lens, 17 ... reflector, 18 DESCRIPTION OF SYMBOLS ... ExB deflector, 19 ... Primary electron beam, 20 ... Secondary electron detector, 21 ... Preamplifier, 22 ... AD converter, 23 ... Optical conversion means, 24 ... Optical transmission means, 25 ... Electrical conversion means, 26 ... High pressure Power source, 27 ... Preamplifier drive power supply, 28 ... AD converter drive power supply, 29 ... Reverse bias power supply, 30 ... Sample stage, 31 ... X stage, 32 ... Y stage, 33 ... Rotation stage, 34 ... Position monitor length measuring device, 35 ... Inspection board height measuring instrument, 3 DESCRIPTION OF SYMBOLS 6 ... Retarding power supply, 40 ... White light source, 41 ... Optical lens, 42 ... CCD camera, 43 ... Scanning signal generator, 44 ... Lens power supply, 45 ... Memory | storage means part, 46 ... Image processing circuit, 47 ... Defect data buffer 49... Overall control unit 55. Map 56. Image display unit 60. Mode switching means 61.

Claims (8)

An irradiation means for irradiating a charged particle beam focused on a substrate surface on which a circuit pattern of the wafer is formed;
Detecting means for detecting a signal generated from the substrate by the irradiation;
Storage means for imaging and storing the signal detected by the detection means;
Comparing means for comparing the stored image with an image formed from another identical circuit pattern;
In a circuit pattern inspection apparatus provided with a discriminating means for discriminating defects on a circuit pattern from a comparison result,
Means for irradiating the same scanning line multiple times with the focused charged particle beam ;
It means for detecting a signal that occurs every irradiation of the plurality of times,
It characterized that you and means used for imaging Some times the signal without the imaging of the signal from the round than the part of the times of the signal generated every irradiation of the plurality of times Circuit pattern inspection device. The circuit pattern inspection apparatus according to claim 1,
An apparatus for inspecting a circuit pattern, comprising means for irradiating the same scanning line with a return operation in which a charged particle beam is irradiated. The circuit pattern inspection apparatus according to claim 1,
A circuit pattern inspection apparatus comprising means for irradiating a next scanning line by a return operation of irradiating a charged particle beam. Irradiating means for irradiating a charged particle beam having a circuit pattern is focused to a formed substrate surface of the wafer,
Detecting means for detecting a signal generated from the substrate by the irradiation;
Storage means for imaging and storing the signal detected by the detection means;
Comparing means for comparing the stored image with an image formed from another identical circuit pattern;
In a circuit pattern inspection apparatus provided with a discriminating means for discriminating defects on a circuit pattern from a comparison result,
Means for irradiating the same scanning line multiple times with the focused charged particle beam ;
Means for imaging an image signal detected by irradiation with the charged particle beam,
The charged state of the substrate is stabilized by scanning one of the charged particle beams irradiated a plurality of times, and the other scanning of the plurality of times of irradiation performed on the substrate having the charged state stabilized. A circuit pattern inspection apparatus comprising means for imaging a detected image signal . The circuit pattern inspection apparatus according to claim 4,
An apparatus for inspecting a circuit pattern, comprising means for stabilizing the charged state of a substrate by irradiating the same scanning line with a return operation in which a charged particle beam is irradiated. The circuit pattern inspection apparatus according to claim 4,
A circuit pattern inspection apparatus comprising means for irradiating a next scanning line by a return operation of irradiating a charged particle beam. An irradiation means for irradiating a charged particle beam focused on a substrate surface on which a circuit pattern of the wafer is formed;
Detecting means for detecting a signal generated from the substrate by the irradiation;
Storage means for imaging and storing the signal detected by the detection means;
Comparing means for comparing the stored image with an image formed from another identical circuit pattern;
In the inspection method by the circuit pattern inspection apparatus, comprising a determination means for determining a defect on the circuit pattern from the comparison result,
Irradiating the same scanning line with the focused charged particle beam multiple times,
Detecting a signal that occur by irradiation of the plurality of times,
The circuit pattern inspection method, wherein imaging is performed based on a signal of a part of the signals generated by the plurality of irradiations . An irradiation means for irradiating a charged particle beam focused on a substrate surface on which a circuit pattern of the wafer is formed;
Detecting means for detecting a signal generated from the substrate by the irradiation;
Storage means for imaging and storing the signal detected by the detection means;
Comparing means for comparing the stored image with an image formed from another identical circuit pattern;
In the inspection method by the circuit pattern inspection apparatus, comprising a determination means for determining a defect on the circuit pattern from the comparison result,
Hitting the irradiated multiple times the same scanning line in the focused charged particle beam, a part of said multiple radiation used to stabilize the charged state of the substrate, the other of the multiple radiations Part is used to detect the image signal after the stabilization of charging,
A circuit pattern inspection method comprising imaging from the detected image signal.

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