JP4530247B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a wafer lot start method in a semiconductor device manufacturing process.
[0002]
[Prior art]
For example, when a reticle (photomask) is changed as a change in processing conditions in a stepper, a reticle newly set prior to the change of the reticle is notified to the supply control apparatus as a reserved reticle, and the reserved reticle is notified. The supply control device instructs the stocker to supply a wafer lot that matches the reticle, so that even if the processing conditions are changed, all the wafer lots that have delivered the stocker are processed by that stepper without reducing the stepper's operating rate. There is a technique for making it possible (see, for example, Patent Document 1).
[0003]
Further, for example, by a host computer that manages the entire production line of a factory, an input / output terminal connected to the host computer via a communication line, and a reticle storage shelf connected to the input / output terminal via a communication line At the start of work and at the completion of work in each work process of the production lot, the input / output terminal reports to the host computer and compares the expected arrival time of the wafer lot to the exposure device and the expected arrival time of the reticle to the exposure device at that timing. To determine whether or not to release the reticle from the reticle storage shelf, and to issue the reticle, transmit the reticle delivery instruction to the reticle storage shelf, and deliver the reticle from the reticle storage shelf to the exposure apparatus. Thus, there is a technique for improving the operating rate of the exposure apparatus (see, for example, Patent Document 2).
[0004]
Further, for example, it is searched whether there is a wafer lot whose progress is delayed among the wafer lots in progress in the exposure process, and if there is no wafer lot whose progress is delayed, the reticle set in the exposure apparatus is selected. Use this to search for a processable wafer lot, transport the wafer lot to the exposure system, and if there is no processable wafer lot, calculate the number of in-process wafer lots for each reticle used in the exposure process. By transporting the reticle with the largest number of in-process reticles to the corresponding exposure system and transporting the wafer lot using the reticle to the exposure system, the wafer lot and reticle are efficiently transported to the exposure system, improving the operating rate of the exposure system. There is a technique (see, for example, Patent Document 3).
[0005]
[Patent Document 1]
JP-A-11-330200
[0006]
[Patent Document 2]
JP-A-6-268043
[0007]
[Patent Document 3]
JP 2000-182939 A
[0008]
[Problems to be solved by the invention]
In recent years, in the manufacture of semiconductor devices, it has been required to supply products quickly according to customer requirements. In order to respond to this requirement, the need to manufacture products with a short TAT (Turn Around Time) has increased. Yes. Also, since product cycles have become shorter, there is a strong demand for shortening the semiconductor device development TAT. In particular, in the development stage of a new product, it is necessary to repeatedly adjust the manufacturing process and correct the mask pattern. Therefore, it is important to shorten the product development period by shortening the TAT for manufacturing the prototype.
[0009]
By the way, the present inventors are examining the technique which automates conveyance of a photomask in a semiconductor manufacturing line. Among them, the present inventors have found the following problems from the viewpoint of manufacturing a semiconductor device with a short TAT.
[0010]
That is, in the exposure process in the manufacture of a semiconductor device, a photomask is required when a wafer lot is started. In a high-mix low-volume production line with a high photomask replacement frequency, it is impossible to start lots until the photomask is transferred to the exposure equipment, so the TAT for semiconductor device manufacturing becomes longer and the exposure equipment is used effectively. There will be less time available. As a result, the throughput of manufacturing the semiconductor device is reduced. In order to avoid such a state, for example, a means can be considered that supports a photomask necessary for a wafer lot to be processed at a high speed. However, the photomask transport system investigated by the present inventors is performed by OHS (Over Head Shuttle) that transports the photomask via a track installed on the ceiling of the clean room, and the photomask is transferred to the exposure apparatus. At a high position. When the present inventors examined, since it was difficult to carry the photomask by OHS at high speed, it turned out that it was difficult to introduce the system which automatically conveys the photomask by OHS at high speed. . For this reason, there is a problem that when the transport of the photomask is automated, the operating rate of the exposure apparatus decreases and the TAT for manufacturing the semiconductor device increases.
[0011]
An object of the present invention is to provide a technique capable of manufacturing a semiconductor device with a short TAT in a semiconductor manufacturing line in which conveyance of a photomask is automated.
[0012]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0013]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0014]
That is, according to the first aspect of the present invention, a wafer lot is transferred to a first manufacturing apparatus included in a first apparatus group according to a first construction plan, and exposure processing is performed on the wafer lot by the first manufacturing apparatus. The first construction plan includes the following steps:
(A) A first wafer lot having a priority level equal to or higher than a first priority level is extracted from the wafer lots set in the semiconductor manufacturing line, and the first wafer lot is used as a start set for the first device group. A step of adding the first wafer lot to an in-process wafer lot group after giving a scheduled time,
(B) A process of creating an in-process list in which in-process ranks are assigned to all the first wafer lots included in the in-process wafer lot group, and the first wafer lots are arranged in the in-process rank order;
(C) A process of creating a manufacturing apparatus list in which start orders are assigned to all the first manufacturing apparatuses included in the first apparatus group, and the first manufacturing apparatuses are arranged in the order of the start orders;
(D) Select the first manufacturing apparatus in order from the top of the manufacturing apparatus list, and search for the first wafer lot that can be started by the selected first manufacturing apparatus in order from the top of the in-process list; A plan for starting the matching first wafer lot with the selected first manufacturing apparatus is incorporated into the first construction plan, and the first wafer lot incorporated in the first construction plan is used as the work in progress. Process to remove from the list,
(E) performing the step (d) for all the first manufacturing apparatuses included in the manufacturing apparatus list;
The first photomask corresponding to the first wafer lot is produced prior to transferring the first wafer lot to the corresponding first manufacturing apparatus in accordance with the first construction plan. Transport to the corresponding first manufacturing apparatus.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
[0016]
FIG. 1 is an explanatory diagram showing an outline of a system configuration of a production line for semiconductor devices according to the present embodiment. As shown in FIG. 1, the production line of the semiconductor device of this embodiment includes a production management system PMS, a manufacturing information registration mechanism PIE, a system evaluation mechanism (system evaluation means) SES, a manufacturing information recording mechanism PIR, and a schedule interruption mechanism SIS. , A manufacturing apparatus PE, an inspection apparatus IE, a transport system CS, and the like. The production management system PMS includes a progress management mechanism AMS, a scheduling mechanism SJS, a transport system control mechanism CCS, an apparatus control mechanism ECS, and the like. Note that each of the manufacturing apparatus PE and the inspection apparatus IE is not limited to one.
[0017]
The manufacturing information recording mechanism PIR records semiconductor device manufacturing information registered by the manufacturing information registration mechanism PIE, information that is sequentially updated by the production management system PMS, and a history of changes in these information. The manufacturing information of the semiconductor device includes the manufacturing process sequence of the semiconductor device to be a product, the manufacturing apparatus PE (including the inspection apparatus IE) that can be used for each process (processing can be executed), the processing conditions of the product lot, and the process Production flow information including cycle time, progress of manufacturing semiconductor device as a product (in-process), current position of wafer lot (including during manufacturing process), in-process information including wafer lot status, wafer lot in manufacturing apparatus PE It includes information on stock including reservation information of the port to be carried in, information on the manufacturing apparatus PE including the transport system CS, and the like. For example, when the manufacturing apparatus PE is an exposure apparatus, the wafer lot processing conditions include information on the photomask to be used, the exposure time, the number of shots, and the like.
[0018]
The manufacturing information registration mechanism PIE is means for registering the manufacturing information of the semiconductor device in the manufacturing information recording mechanism PIR. Registration of initial data of manufacturing information of the semiconductor device, manufacturing device PE in the production line (including the inspection device IE) It is used when registering information related to addition or reduction of information and information related to addition or reduction of manufacturing process flow in the production line.
[0019]
The system evaluation mechanism SES has a virtual production line, and the logic applied to the scheduling mechanism SJS can be simulated in advance on the virtual production line and evaluated. In addition, the system evaluation mechanism SES acquires information on the in-process in the actual production line, the state of the manufacturing apparatus PE (including the inspection apparatus IE), the manufacturing process flow, and the like from the production management system PMS, and the actual production line ( The logic applied to the scheduling mechanism SJS) can be evaluated. Thus, for example, new logic can be constructed and applied to an actual production line while avoiding adverse effects on the production line such as extending the TAT and lowering the throughput of the manufacturing apparatus PE.
[0020]
The progress management mechanism AMS manages the progress of manufacturing the semiconductor device according to the present embodiment. The scheduling mechanism SJS determines the start order of the semiconductor devices that are products, the manufacturing apparatus PE (including the inspection apparatus IE) to be started, and the like. The transport system control mechanism CCS controls the operation of the transport system CS. The device control mechanism ECS controls the operation of the manufacturing device PE and the inspection device IE. In the production management system PMS, the progress management mechanism AMS, the scheduling mechanism SJS, the transport system control mechanism CCS, and the apparatus control mechanism ECS communicate information with each other.
[0021]
The transfer system control mechanism CCS controls the transfer system CS so that the wafer lot can be transferred to a predetermined manufacturing apparatus PE or inspection apparatus IE according to the lot assignment information transmitted from the scheduling mechanism SJS. Further, when the state of the transport system CS changes, the transport system control mechanism CCS records the state of the transport system CS and a history of changes in the state in the manufacturing information recording mechanism PIR. Here, the change in the state of the transport system CS refers to a change in the operating state of the transport system CS when, for example, an abnormality occurs in the stocker included in the transport system and the stocker cannot be used. Also, stocker abnormalities refer to the state where stockers cannot be loaded into or removed from the stocker due to a failure of a loading / unloading mechanism (such as a crane) that loads and unloads wafer lots, for example. Say.
[0022]
The apparatus control mechanism ECS manufactures the above processing conditions for each manufacturing apparatus PE to perform various processes on the wafer lot after the product lot is transferred to each manufacturing apparatus PE (including the inspection apparatus IE) by the transfer system CS. The information is acquired from the information recording mechanism PIR, and the processing conditions are transmitted to each manufacturing apparatus PE. Further, when the state of the manufacturing apparatus PE changes, the apparatus control mechanism ECS records the state of the manufacturing apparatus PE and a history of changes in the state in the manufacturing information recording mechanism PIR. Here, the change in the state of the manufacturing apparatus PE means, for example, a case where an abnormality has occurred in the manufacturing apparatus PE and the manufacturing apparatus PE cannot be used. Further, the abnormality of the manufacturing apparatus PE means that, for example, a mechanical failure occurs in the manufacturing apparatus PE or a foreign substance is generated in the processing chamber in which the manufacturing apparatus PE performs predetermined processing on the wafer. A state in which the manufacturing apparatus PE is disabled.
[0023]
The progress management mechanism AMS manages the progress of the wafer lot, and in-process information recorded in the manufacturing information recording means PIR according to the change in the wafer lot status reported from the transfer system control mechanism CCS and the apparatus control mechanism ECS. Update. Here, the state of the wafer lot means, for example, whether the wafer lot is being transferred, whether the wafer lot is under construction at the manufacturing apparatus PE (including the inspection apparatus IE), and the wafer lot is waiting at the stocker or the manufacturing apparatus PE port. It contains information about whether or not it is inside. Further, when the wafer lot is on standby, it includes a case where an abnormality has occurred in the wafer lot and the wafer lot cannot be advanced to the next process. Based on the state of the wafer lot, it is determined whether or not the wafer lot is started in the manufacturing apparatus PE, the start of the start of the process, the start of the start of the process, and the completion of the process, and whether or not the wafer lot is advanced to the next process is determined.
[0024]
The scheduling mechanism SJS has a mechanism for grasping in-process manufacturing process information, a mechanism for grasping in-process information of a wafer lot, a mechanism for grasping information on the state of the manufacturing apparatus PE (including the inspection apparatus IE), and the like. Based on the manufacturing information on the progress of the process, the state of the transfer system CS, the state of each manufacturing apparatus PE, and the like, a schedule is established regarding which wafer lot is to be started by which manufacturing apparatus PE. The process for constructing the schedule will be described later.
[0025]
The schedule interrupt mechanism SIS is a means for artificially interrupting a schedule by a user when a schedule is created by the scheduling mechanism SJS. By using this schedule interruption mechanism SIS, the user can reserve in advance a schedule of a specific manufacturing apparatus PE (including the inspection apparatus IE) at a specific time. When such a reservation is entered, the scheduling mechanism SJS reconstructs the schedule in consideration of the reservation. The reason why the user manually interrupts the schedule by using such a schedule interrupt mechanism SIS is that, for example, a high-priority wafer lot (hereinafter referred to as an express lot) that has been processed later is processed first. For example, when the wafer lot is not transferred to the manufacturing apparatus PE for periodic inspection of the manufacturing apparatus PE.
[0026]
FIG. 2 is a main part plan view showing a part of the production line of the semiconductor device of the present embodiment. The clean room includes a manufacturing apparatus PE (inspection apparatus IE (see FIG. 1)) such as a heat treatment apparatus, an ion implantation apparatus, an etching apparatus, a film forming apparatus, a cleaning apparatus, a photoresist coating apparatus, and an exposure apparatus used for semiconductor manufacturing. Is divided into a plurality of bays (apparatus groups), and the manufacturing apparatus PE shown in FIG. 2 is an exposure apparatus. The above-described transport system CS (see FIG. 1) corresponds to the arrangement of each manufacturing apparatus PE, and is transported between bays, transported within the bay, stocker STC that relays them, and reticle stocker RSC that temporarily stores photomasks. It is configured.
[0027]
Transfer of wafer lots between bays is performed by, for example, OHS (Over Head Shuttle) 1 that transfers wafer lots via a track ORB1 installed on the ceiling in a clean room. The track ORB1 is installed corresponding to the arrangement position of the stocker STC. The wafer lot in the bay is transferred by, for example, an RGV (Rail Guided Vehicle) 2 that travels on the transfer rail ORB 2 laid on the floor of the clean room CR. The transport rail ORB2 is installed corresponding to the arrangement position of the stocker STC and the manufacturing apparatus PE. The transport of the photomask is performed by a carriage 3 that travels via a track ORB3 that is laid in correspondence with the position of the manufacturing apparatus PE. Further, the manufacturing apparatus PE is provided with a port POT1 into which a wafer lot is carried and a port POT2 into which a photomask is carried.
[0028]
Next, a process of constructing a construction plan (first construction plan) about which wafer lot is to be constructed by which manufacturing apparatus PE will be described using the flowchart shown in FIG.
[0029]
In the present embodiment, the apparatus group is a group of manufacturing apparatuses PE (including the inspection apparatus IE) capable of performing the same type of wafer processing. In the example described with reference to FIG. Assume that the exposure apparatus. The in-process list refers to a list of wafer lots that can be started by the manufacturing apparatus PE included in the apparatus group. In the in-process list, first, a plurality of wafer lots are arranged in order of priority. They are arranged in chronological order of the time when the device group is in process or the time when it is scheduled to be in process. The device list is a list of manufacturing devices PE included in the device group, and the processing time for the wafer lot is completed in ascending order regardless of whether or not the processing for the wafer lot is being executed. These manufacturing apparatuses PE are arranged.
[0030]
First, all devices in a predetermined manufacturing apparatus group (hereinafter referred to as a first apparatus group) that performs exposure processing are extracted (step S1). Next, the in-process status of a wafer lot (first wafer lot) having a priority level equal to or higher than a predetermined priority level (hereinafter referred to as a first priority level) is determined from the wafer lots set in the semiconductor production line of the present embodiment. These are extracted and given to the in-process wafer lot group after giving a scheduled time for the first priority wafer lot to be in-process for the first apparatus group. At this time, with respect to the wafer lot to be extracted, a wafer lot that is being processed in what process before the process (hereinafter referred to as the first process) to be processed by the first apparatus group is extracted according to the priority. These shall be set as appropriate. For example, the wafer lot with the highest priority is extracted if it is in process 1 to 3 steps before the first step. In the present embodiment, a wafer lot having a normal priority is added to the in-process wafer lot group when the first process is in progress. For example, when an express lot is not extracted. In addition, even if it is the in-process of the process one process before the first process, it may be added to the in-process wafer lot group (process S2).
[0031]
Next, an in-process rank is assigned to all wafer lots included in the in-process wafer lot group, and an in-process list in which the wafer lots are arranged in the in-process rank order is created. The in-process rank is assigned by first assigning ranks in descending order of priority, and then assigning new ranks between the wafer lots with the same rank. At this time, for example, when the wafer lots whose ranks are overlapped are the express lots, the ranks can be given in the order of the scheduled time to be used for the first apparatus group. Further, for example, when the wafer lots whose ranks are overlapped are normal wafer lots, the ranks can be given in the order of the time when the first device group is started (step S3).
[0032]
Next, a manufacturing order is assigned to all manufacturing apparatuses (first manufacturing apparatuses) PE included in the first apparatus group, and a manufacturing apparatus list arranged in the order of the starting orders is created. For the manufacturing apparatus PE which is not currently started for the wafer lot and there is no wafer lot that has been reserved for the start of the process, the starting order is assigned in the order of the time when the processing for the immediately preceding wafer lot in the manufacturing apparatus PE is completed. Give a ranking. Next, the order subsequent to the order is assigned to the manufacturing apparatus PE having a wafer lot that is currently being started or reserved for the start of the wafer lot in the order from the earliest scheduled time to complete the process on the wafer lot (step S4). .
[0033]
Next, a wafer lot that can be started by the manufacturing apparatus PE at the top of the manufacturing apparatus list is searched from the top of the in-process list (step S5). Here, the wafer lot that can be started is a wafer lot that can be subjected to exposure processing by the manufacturing apparatus PE in consideration of the type of the wafer lot and the processing conditions of the exposure processing performed on the wafer lot. Next, it is determined whether or not a wafer lot that can be started by the manufacturing apparatus PE is found by the search in step S5 (step S6). When a wafer lot that can be started is not found, it is determined whether or not the manufacturing apparatus PE is the last manufacturing apparatus PE in the manufacturing apparatus list (step S7). The flowchart shown in FIG. 3 ends. On the other hand, if it is not the last manufacturing apparatus PE, the manufacturing apparatus PE of the next rank is searched from the manufacturing apparatus list (step S8), and the processes from step S6 are performed on the manufacturing apparatus PE.
[0034]
If a processable wafer lot is found in step S6, it is determined whether the wafer lot meets any of the following conditions (a) to (c) (step S9).
(A) The scheduled time at which the target manufacturing apparatus PE is in progress is earlier than the processing completion time of the wafer lot currently being started by the manufacturing apparatus PE.
(B) It is already in progress for the target manufacturing apparatus PE.
(C) In the target manufacturing apparatus PE, there is no wafer lot currently under construction, and there is no other construction plan.
If none of these (a) to (c) applies, it is determined whether or not the wafer lot is the last wafer lot in the in-process list (step S10). If the wafer lot is not the last wafer lot in the in-process list, the next-order wafer lot is searched from the in-process list (step S11), and the processes from step S9 are performed on the next-order wafer lot. On the other hand, if it is determined in step S10 that the target wafer lot is the last wafer lot in the in-process list, the processes from step S7 described above are performed.
[0035]
If the target wafer lot corresponds to any of the above (a) to (c) in step S9, whether the photomask used for the exposure processing for the wafer lot exists in the target manufacturing apparatus PE It is determined whether or not (step S12). When it is determined that the photomask does not exist in the target manufacturing apparatus PE, it is determined whether the photomask exists in a manufacturing apparatus PE other than the target manufacturing apparatus PE ( Step S13). At this time, the fact that the photomask does not exist in the manufacturing apparatus PE other than the target manufacturing apparatus PE means that the photomask exists in the reticle stocker RSC. When it is determined in step S12 that the target photomask is present in the target manufacturing apparatus PE, and in step S13, the target photomask is not present in any manufacturing apparatus PE other than the target manufacturing apparatus PE. If it is determined, the process proceeds to step S14.
[0036]
In step S14, a start plan (first start plan) for starting the target wafer lot with the target manufacturing apparatus PE is created. Through such steps S1 to S14, the wafer lot incorporated in the start plan is deleted from the in-process list (step S15), and the steps from step S7 are performed again. Such a flowchart of the present embodiment is performed at a predetermined time set in advance, for example, once every 5 minutes, and the above-described steps S6 to S15 are repeated until the flowchart is completed.
[0037]
For example, the manufacturing apparatus PE included in the first apparatus group includes three manufacturing apparatuses (first manufacturing apparatuses) PEA, PEB, and PEC, and each wafer lot has a device as shown in FIG. In this case, if the flowchart shown in FIG. 3 is applied, a construction plan as shown in FIG. 5 is created. At this time, in the limited express lot, the in-process before the first process is also subject to schedule construction, and in the normal wafer lot, only the in-process in the first step is subject to schedule construction. That is, the express lot ELA and the normal wafer lot LB are in process before the first process, the normal wafer lot LC is in process before the first process, and the normal wafer lot LD is the first process. The first wafer process LE is in process, the normal wafer lots LE and LF are the first process (first apparatus group), and the wafer lot LE is the first apparatus group. If the wafer time LF is earlier than the time when the wafer lot LF becomes the work in progress of the first device group, the work order is assigned in the order of the express lot ELA, the wafer lot LE, and the wafer lot LF in the work in process list. Here, in the manufacturing apparatus list, when the start order of each manufacturing apparatus is given in the order of the manufacturing apparatus PEA, the manufacturing apparatus PEB, and the manufacturing apparatus PEC, the express lot ELA is assigned to the manufacturing apparatus PEA, and the manufacturing apparatus A wafer lot LE is assigned to the PEB, and a construction plan is created in which the wafer lot LF is assigned to the manufacturing apparatus PEC. Photomasks corresponding to the express lot ELA, the wafer lot LE, and the wafer lot LF before the express lot ELA, the wafer lot LE, and the wafer lot LF are transferred to the manufacturing apparatus PEA, the manufacturing apparatus PEB, and the manufacturing apparatus PEC, respectively. The (first photomask) is conveyed from the reticle stocker RSC (see FIG. 2) to the manufacturing apparatuses PEA, PEB, and PEC. Thereby, in the manufacturing apparatuses PEA, PEB, and PEC, it is possible to prevent a delay in the start of construction due to waiting for the arrival of the photomask, so that it is possible to shorten the TAT for manufacturing the semiconductor device according to the present embodiment. Further, the waiting time (idling time) of the manufacturing apparatuses PEA, PEB, and PEC can be increased by shortening the TAT of the semiconductor device manufacturing. Due to this increase in the waiting time, the manufacturing apparatuses PEA, PEB, and PEC can start a larger number of wafer lots with the increased waiting time, so that it is possible to increase the throughput of manufacturing the semiconductor device according to the present embodiment. Become. Note that photomasks that have been used in the manufacturing apparatus PEA, the manufacturing apparatus PEB, and the manufacturing apparatus PEC are collected to the reticle stocker RSC at a predetermined timing.
[0038]
In addition, as described above, the express lot ELA is preferentially incorporated into the construction plan by incorporating the express lot ELA into the work-in-process list from a plurality of processes before, so that the express lot ELA is a normal wafer lot. Further, the manufacturing TAT can be greatly shortened. For example, when the express lot ELA is a developed product (prototype), the period until the release of a new product with a high market value can be shortened by significantly reducing the TAT of the production.
[0039]
By the way, the above-mentioned system evaluation mechanism SES (see FIG. 1) is a flowchart described with reference to FIG. 3 for the first step and the portion related to the first device group in the simulation of the production line of the present embodiment. The first process is virtually performed according to the virtual construction plan created along the line, and the virtual construction plan is virtually evaluated. As a result, factors that have an adverse effect on the production line such as TAT extension in the first process and the first apparatus group and a reduction in the throughput of the manufacturing apparatus are discovered at the stage of simulation, and the above-mentioned construction plan is added to the actual production line. It becomes possible to remove the factor that has an adverse effect before applying.
[0040]
The wafer lot start plan created according to the above flowchart (see FIG. 3) and the photomask transfer process according to the start plan, in particular, by appropriately shortening the time interval for executing the flowchart, A great effect can be obtained by applying it to a production line of a small number of various types of semiconductor devices in which a wafer lot is started.
[0041]
Further, in the example described with reference to FIGS. 4 and 5, only the express lot ELA having a high priority is incorporated into the work in process list before being used in the first process, and is incorporated into the start plan. In the case where the number of devices in the first process by the first apparatus group is less than the predetermined number, the wafer lot that has been in the previous number of steps is processed regardless of the priority of the wafer lot. It may be included in the hanging list. As a result, a larger number of wafer lots can be used for the first apparatus group, and the corresponding photomask can be transferred to the predetermined manufacturing apparatuses PEA, PEB, and PEC in the first apparatus group. It is possible to further shorten the TAT for manufacturing the semiconductor device according to the embodiment.
[0042]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0043]
In the above-described embodiment, the case where the wafer lot is transported in the bay has been described using RGV. However, AGV (Automatic Guided Vehicle) may be used instead of RGV.
[0044]
【The invention's effect】
Among the inventions disclosed by the present application, effects obtained by typical ones will be briefly described as follows.
[0045]
That is, TAT for semiconductor device manufacturing can be shortened in a semiconductor manufacturing line in which photomask transport is automated.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing an outline of a system configuration of a production line for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a fragmentary plan view showing a part of a production line for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a flowchart for explaining a process of constructing a start plan for which wafer lot is to be started by which manufacturing apparatus in the manufacturing process of the semiconductor device according to the embodiment of the present invention;
FIG. 4 is an explanatory diagram showing an in-process state of each wafer lot in the semiconductor device manufacturing process according to an embodiment of the present invention;
FIG. 5 is an explanatory diagram showing a relationship between a start plan, an in-process list, and a manufacturing apparatus list as to which wafer lot is to be started by which manufacturing apparatus in a semiconductor device manufacturing process according to an embodiment of the present invention; is there.
[Explanation of symbols]
1 OHS
2 RGV
3 carts
AMS progress management mechanism
CCS transport system control mechanism
CS transport system
ECS device control mechanism
ELA express lot
IE inspection equipment
LB, LC, LD, LE, LF Wafer lot
ORB1, ORB3 orbit
ORB2 transport rail
PE manufacturing equipment (first manufacturing equipment)
PEA, PEB, PEC production equipment (first production equipment)
PIE Manufacturing Information Registration Organization
PIR manufacturing information recording mechanism
PMS production management system
POT1, POT2 port
RSC reticle stocker
S1-S15 process
SES system evaluation mechanism (system evaluation means)
SIS schedule interrupt mechanism
SJS scheduling mechanism
STC stocker

Claims (16)

A semiconductor device including a first step of transporting a wafer lot to a first manufacturing apparatus included in a first apparatus group according to a first start plan, and subjecting the wafer lot to an exposure process in the first manufacturing apparatus. The first construction plan is a manufacturing method of
(A) A first wafer lot having a priority level equal to or higher than a first priority level is extracted from the wafer lots set in the semiconductor manufacturing line, and the first wafer lot is used as a start set for the first device group. A step of adding the first wafer lot to an in-process wafer lot group after giving a scheduled time,
(B) A process of creating an in-process list in which in-process ranks are assigned to all the first wafer lots included in the in-process wafer lot group, and the first wafer lots are arranged in the in-process rank order;
(C) A process of creating a manufacturing apparatus list in which start orders are assigned to all the first manufacturing apparatuses included in the first apparatus group, and the first manufacturing apparatuses are arranged in the order of the start orders;
(D) Select the first manufacturing apparatus in order from the top of the manufacturing apparatus list, and search for the first wafer lot that can be started by the selected first manufacturing apparatus in order from the top of the in-process list; A plan for starting the matching first wafer lot with the selected first manufacturing apparatus is incorporated into the first construction plan, and the first wafer lot incorporated in the first construction plan is used as the work in progress. Process to remove from the list,
(E) performing the step (d) for all the first manufacturing apparatuses included in the manufacturing apparatus list;
The first photomask corresponding to the first wafer lot is produced prior to transferring the first wafer lot to the corresponding first manufacturing apparatus in accordance with the first construction plan. A method of manufacturing a semiconductor device, wherein the semiconductor device is conveyed to the corresponding first manufacturing apparatus. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (a), the number of steps before the first step is a work in progress according to the priority of the first wafer lot. A method for manufacturing a semiconductor device, comprising setting whether to extract up to a first wafer lot. 2. The method of manufacturing a semiconductor device according to claim 1, wherein when the number of devices in the first step by the first device group is less than a predetermined number, the step (a) is more effective than the first step. A method of manufacturing a semiconductor device, characterized in that the first wafer lot that is in process up to a predetermined number of processes is extracted regardless of priority. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (b), the in-process rank is assigned in order from the first wafer lot having a high priority, and the in-process rank is overlapped. A method of manufacturing a semiconductor device, characterized in that the in-process ranking is newly assigned in the order of the scheduled time to be in-process for the first device group. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c),
(C1) The processing for the wafer lot immediately before the first manufacturing apparatus is completed for the first manufacturing apparatus that has not started the wafer lot and has no reservation for the wafer lot. A step of assigning the construction order in the order of early time;
(C2) The process for the wafer lot is completed with respect to the first manufacturing apparatus having the wafer lot for which the start of the process following the step (c1) is being started or is reserved for the start. The process of giving in order from the earliest scheduled time,
A manufacturing method of a semiconductor device, wherein the starting rank is given to the first manufacturing apparatus in a process including: The method of manufacturing a semiconductor device according to claim 1, wherein in the step (d), the suitable first wafer lot is:
(D1) The scheduled time at which the selected first manufacturing apparatus is in progress is earlier than the processing completion time of the wafer lot in which the selected first manufacturing apparatus is under construction (d2) already selected It is a work in progress of the first manufacturing apparatus,
(D3) In the selected first manufacturing apparatus, there is no wafer lot under construction and there is no other construction plan.
A semiconductor device manufacture, wherein a plan for starting the first wafer lot to be matched by the selected first manufacturing apparatus is incorporated into the first start plan when any one of the above conditions is met. Method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (d) is present in the first manufacturing apparatus in which the first photomask used for the exposure process to the suitable first wafer lot is selected. A step of determining whether or not to perform the process, and when it is determined that the first photomask is not present in the selected first manufacturing apparatus, the first photomask is selected. It is determined whether or not the first manufacturing apparatus other than the first manufacturing apparatus exists, and when it is determined that the first photomask exists in the selected first manufacturing apparatus, or In the first manufacturing apparatus in which the first wafer lot is selected in which the first photomask is determined not to exist in the first manufacturing apparatus other than the selected first manufacturing apparatus. Before planning to start construction The method of manufacturing a semiconductor device, characterized in that incorporated in the first production plan. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first construction plan is created at predetermined time intervals. A system including a first step of transporting a wafer lot to a first manufacturing apparatus included in a first apparatus group in accordance with a first start plan, and performing an exposure process on the wafer lot in the first manufacturing apparatus; A semiconductor device manufacturing method including a step of virtually executing a manufacturing step of a semiconductor device including the first step by an evaluation unit, wherein the first construction plan includes:
(A) A first wafer lot having a priority level equal to or higher than a first priority level is extracted from the wafer lots set in the semiconductor manufacturing line, and the first wafer lot is used as a start set for the first device group. A step of adding the first wafer lot to an in-process wafer lot group after giving a scheduled time,
(B) A process of creating an in-process list in which in-process ranks are assigned to all the first wafer lots included in the in-process wafer lot group, and the first wafer lots are arranged in the in-process rank order;
(C) A process of creating a manufacturing apparatus list in which start orders are assigned to all the first manufacturing apparatuses included in the first apparatus group, and the first manufacturing apparatuses are arranged in the order of the start orders;
(D) Select the first manufacturing apparatus in order from the top of the manufacturing apparatus list, and search for the first wafer lot that can be started by the selected first manufacturing apparatus in order from the top of the in-process list; A plan for starting the matching first wafer lot with the selected first manufacturing apparatus is incorporated into the first construction plan, and the first wafer lot incorporated in the first construction plan is used as the work in progress. Process to remove from the list,
(E) performing the step (d) for all the first manufacturing apparatuses included in the manufacturing apparatus list;
The first photomask corresponding to the first wafer lot is produced prior to transferring the first wafer lot to the corresponding first manufacturing apparatus in accordance with the first construction plan. Before carrying out the corresponding first manufacturing apparatus in the semiconductor manufacturing line, it is virtually executed by the system evaluation means, and the first construction plan is virtually evaluated. A method for manufacturing a semiconductor device. 10. The method of manufacturing a semiconductor device according to claim 9, wherein, in the step (a), the number of steps before the first step is a start of the step according to the priority of the first wafer lot. A method for manufacturing a semiconductor device, comprising setting whether to extract up to a first wafer lot. 10. The method of manufacturing a semiconductor device according to claim 9, wherein when the number of devices in the first step by the first device group is less than a predetermined number, the step (a) is more effective than the first step. A method of manufacturing a semiconductor device, characterized in that the first wafer lot that is in process up to a predetermined number of processes is extracted regardless of priority. 10. The method of manufacturing a semiconductor device according to claim 9, wherein in the step (b), the in-process rank is assigned in order from the first wafer lot having the highest priority, and the in-process ranks overlap each other. Then, a method of manufacturing a semiconductor device is characterized in that a new work order is assigned in the order of the scheduled time to be used for the first device group. 10. The method of manufacturing a semiconductor device according to claim 9, wherein in the step (c),
(C1) The processing for the wafer lot immediately before the first manufacturing apparatus is completed for the first manufacturing apparatus that has not started the wafer lot and has no reservation for the wafer lot. A step of assigning the construction order in the order of early time;
(C2) The process for the wafer lot is completed with respect to the first manufacturing apparatus having the wafer lot for which the start of the process following the step (c1) is being started or is reserved for the start. The process of giving in order from the earliest scheduled time,
A manufacturing method of a semiconductor device, wherein the starting rank is given to the first manufacturing apparatus in a process including: 10. The method of manufacturing a semiconductor device according to claim 9, wherein in the step (d), the suitable first wafer lot is
(D1) The scheduled time at which the selected first manufacturing apparatus is in progress is earlier than the processing completion time of the wafer lot in which the selected first manufacturing apparatus is under construction (d2) already selected It is a work in progress of the first manufacturing apparatus,
(D3) In the selected first manufacturing apparatus, there is no wafer lot under construction and there is no other construction plan.
A semiconductor device manufacture, wherein a plan for starting the first wafer lot to be matched by the selected first manufacturing apparatus is incorporated into the first start plan when any one of the above conditions is met. Method. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the step (d) is present in the first manufacturing apparatus in which the first photomask used for the exposure process to the suitable first wafer lot is selected. A step of determining whether or not to perform the process, and when it is determined that the first photomask is not present in the selected first manufacturing apparatus, the first photomask is selected. It is determined whether or not the first manufacturing apparatus other than the first manufacturing apparatus exists, and when it is determined that the first photomask exists in the selected first manufacturing apparatus, or In the first manufacturing apparatus in which the first wafer lot is selected in which the first photomask is determined not to exist in the first manufacturing apparatus other than the selected first manufacturing apparatus. Before planning to start construction The method of manufacturing a semiconductor device, characterized in that incorporated in the first production plan. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the first start plan is created at a predetermined time interval.

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