JP4523531B2 - Semiconductor memory device, reading method thereof, and electronic apparatus - Google Patents

Description

  The present invention relates to a semiconductor memory device and a reading method thereof, and more specifically, a nonvolatile semiconductor memory device capable of storing 2-bit information in each memory cell, and 2-bit information is read from each memory cell. Related to the method. The present invention also relates to an electronic apparatus provided with such a semiconductor memory device.

  Conventionally, a flash memory as shown in FIG. 9 is known as a nonvolatile memory capable of storing 2-bit information in each memory cell. FIG. 9 shows memory cells 136a to 136d connected in series and a circuit for reading information stored in these memory cells. Two bits of data are stored in the floating gates of the memory cells 136a to 136d.

  For example, when reading information stored in the memory cell 136b, first, 4V is applied to the word line 137, the bit lines 138a and 138b are grounded, and 1V is applied to the bit lines 138c to 138d. At this time, a current corresponding to the charge stored in the floating gate of the memory cell 136b flows from the bit line 138c, and the potential of the bit line also changes according to the amount of the current. On the other hand, by applying a voltage to the control line 134c, the column selector 135c is turned on, and the other column selectors 135a, 135b, 135d and 135e are turned off, whereby the bit line 138c and the global bit line 139 are turned on. Electrically connected. Thereby, the read current of the memory cell is transmitted to the global bit line 139.

  Here, since the characteristics of the memory cells constituting the memory cell array generally vary, it corresponds to each storage state “00” “01” “10” “11” stored in the memory cells 138a to 138d. The obtained read current shows distributions 144 to 147 as shown in FIG. For this reason, references 141 to 143 are provided as criteria for determining the respective storage states.

  Then, the references 141 to 143 are sequentially input to the input 133 in FIG. 9, and the determination circuit 132 compares the current supplied to the reference from the input 133 with the read current of the memory cell, and determines the magnitude of both. . In this manner, information stored in the memory cell is read (see, for example, Patent Document 1 (US Pat. No. 5,608,669)).

In recent years, as shown in FIG. 1A or FIG. 2A, one memory cell is provided with two storage units 12a and 12b; 27a and 27b, and by storing 1-bit information in each storage unit, Memory elements that store 2-bit information per memory cell have been proposed (see, for example, Patent Document 2 (Japanese Patent Publication No. 2001-512290) and Patent Document 3 (Japanese Patent Laid-Open No. 2004-221546)). In these configurations, it is only necessary to store 1-bit information in one storage unit, and it is relatively easy to store 2 bits per memory cell as compared to the configuration illustrated in FIG.
US Pat. No. 5,608,669 JP-T-2001-512290 JP 2004-221546 A

  However, with recent progress in microfabrication technology, variations in characteristics of memory cells included in the memory cell array have become prominent. As a result, for example, in the flash memory shown in FIG. 9, the adjacent ones of the current distributions 144 to 147 corresponding to the four storage states shown in FIG. For this reason, it has become difficult to read out information by a method in which one fixed reference level is provided and the magnitude of the current compared with this reference level is compared.

  Further, with respect to the memory cell shown in FIG. 1A or FIG. 2A, the variation in characteristics of the memory cell tends to increase as the microfabrication technology advances. In particular, when reading is performed under voltage conditions in the linear region of the transistor in consideration of reliability, there is a phenomenon that the value of the read current changes due to the influence of the storage state of the storage unit opposite to the storage unit to be read. As a result, the variation is further increased. For this reason, when reading 1-bit information stored in one storage unit, it has become difficult to read with one fixed reference.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device capable of performing a highly reliable and stable reading operation when reading out 2-bit information from a memory cell having two storage units capable of storing information independent of each other, and the reading thereof. It is to provide a method.

  Another object of the present invention relates to an electronic apparatus provided with such a semiconductor memory device.

In order to solve the above problems, a reading method of a semiconductor memory device of the present invention includes:
A reading method for a semiconductor memory device, which reads out the storage states of the pair of storage units of a plurality of memory cells having a pair of storage units capable of storing mutually independent information using first and second current paths opposite to each other. Because
The current flowing through each memory cell takes a minimum value when both storage units are in the programmed state in each current path, and one storage unit corresponding to the direction of the current is in the programmed state and the other storage unit. Takes a first intermediate value greater than the minimum value when the first storage unit is in the erased state, and a second intermediate value greater than the first intermediate value when the one storage unit is in the erased state and the other storage unit is in the programmed state Taking a value and taking a maximum value greater than the second intermediate value when both storage parts are in the erased state,
In common with the plurality of memory cells, a first reference current level that is greater than the minimum value and less than the second intermediate value, and a second reference current level that is greater than the first intermediate value and less than the maximum value. Define the reference current level,
The first current path is set, the current flowing through the memory cell is compared with the first and second reference current levels, and the charge corresponding to the current flowing through the memory cell is stored in the first storage. Store in the department,
The second current path is set to compare the current flowing through the memory cell with the first and second reference current levels, respectively, and charge corresponding to the current flowing through the memory cell is stored in the second storage. Store in the department,
The charge amount stored in the first storage unit is compared with the charge amount stored in the second storage unit.

  Here, “program state” which is one of the storage states means a state where information is written, and “erase state” means a state where information is erased. For example, “program state” can correspond to logic 0, and “erase state” can correspond to logic 1, respectively.

  In general, when viewed from the whole memory cell included in a semiconductor memory device, the distribution of the first intermediate value and the distribution of the second intermediate value partially overlap each other due to variations in characteristics of the memory cell. If only the reference current level is used, the determination circuit may not have a sufficient current margin for accurately determining the storage state of each storage unit. Therefore, in the reading method of the semiconductor memory device of the present invention, the first reference current level that is larger than the minimum value and smaller than the second intermediate value and the first intermediate value in common with respect to the plurality of memory cells. And a second reference current level that is greater than and less than the maximum value. The first reference current level can be set with a margin between the minimum value distribution and the second intermediate value distribution. The second reference current level can be set with a margin between the distribution of the first intermediate value and the distribution of the maximum value. Then, when each of the current paths is set, the current flowing through the memory cell is compared with the first and second reference current levels. As a result, when both storage units are in the programmed state, or when both storage units are in the erased state, this can be accurately determined. When one of the storage units is in the programmed state and the other storage unit is in the erased state, the amount of charge stored in the first storage unit and the amount of charge stored in the second storage unit are An accurate determination can be made based on the comparison result. Therefore, it is possible to perform a more reliable and stable reading operation as compared with the prior art.

The semiconductor memory device of the present invention is
A plurality of memories having a pair of storage units capable of storing mutually independent information, and the storage states of the pair of storage units being read using first and second current paths opposite to each other With cells,
The current flowing through each memory cell takes a minimum value when both storage units are in the programmed state in each current path, and one storage unit corresponding to the direction of the current is in the programmed state and the other storage unit. Takes a first intermediate value greater than the minimum value when the first storage unit is in the erased state, and a second intermediate value greater than the first intermediate value when the one storage unit is in the erased state and the other storage unit is in the programmed state Taking a value and taking a maximum value greater than the second intermediate value when both storage parts are in the erased state,
In common with the plurality of memory cells, a first reference current level that is greater than the minimum value and less than the second intermediate value, and a second reference current level that is greater than the first intermediate value and less than the maximum value. A reference current level is defined,
A current path setting unit for sequentially setting the current paths;
A first determination circuit that compares a current flowing through the memory cell with the first reference current level when each of the current paths is set;
A second determination circuit that compares a current flowing through the memory cell with the second reference current level when each of the current paths is set;
When the first current path is set, a first accumulation unit that accumulates electric charge according to the current flowing through the memory cell;
When the second current path is set, a second accumulation unit that accumulates electric charge according to the current flowing through the memory cell;
A third determination circuit that compares the amount of charge stored in the first storage unit with the amount of charge stored in the second storage unit is provided.

  In the semiconductor memory device of the present invention, when each of the current paths is set, the first and second determination circuits compare the current flowing through the memory cell with the first and second reference current levels, respectively. To do. As a result, when both storage units are in the programmed state, or when both storage units are in the erased state, this can be accurately determined. Further, when any one of the storage units is in the programmed state and the other storage unit is in the erased state, the fact that the third determination circuit further stores the charge amount stored in the first storage unit and the second storage unit. Can be accurately determined based on the result of comparison with the amount of charge stored in the storage section. Therefore, it is possible to perform a more reliable and stable reading operation as compared with the prior art.

In the semiconductor memory device of one embodiment,
The current path setting unit includes first and second bit lines connected to two terminals of the memory cell, and a global bit line connected to the first and second bit lines via a column selector. Including
The first and second determination circuits have a first input terminal connected to the global bit line, and a second input terminal to which the first or second reference current level is applied,
The first and second storage units are connected to the global bit line via first and second selectors, respectively.
The third determination circuit includes a first input terminal connected to the first storage unit via a third selector, and a first input terminal connected to the second storage unit via a fourth selector. 2 input terminals.

  In the semiconductor memory device of this embodiment, the storage state of the pair of storage units can be read by switching the column selector and the first to fourth selectors on and off.

In the semiconductor memory device of one embodiment,
The current path setting unit includes first and second bit lines connected to two terminals of the memory cell, and a global bit line connected to the first and second bit lines via a column selector. Including
The first, second, and third determination circuits are configured as a common determination circuit, and the determination circuit is connected to the global bit line via a first selector and a second selector, respectively. A second input terminal;
The first storage unit is connected to a first input terminal of the determination circuit via a third selector,
The second storage unit is connected to a second input terminal of the determination circuit via a fourth selector,
The first or second reference current level is applied to the first and second input terminals of the determination circuit via the fifth and sixth selectors, respectively.

  In the semiconductor memory device of this embodiment, the storage state of the pair of storage units can be read by switching on and off the column selector and the first to sixth selectors. In addition, since the area occupied by the first, second, and third determination circuits can be reduced to one, the area of the semiconductor memory device can be reduced.

In the semiconductor memory device of one embodiment,
The current path setting unit includes first and second bit lines connected to two terminals of the memory cell, and a global bit line connected to the first and second bit lines via a column selector. Including
The first and second determination circuits are configured as one common determination circuit, and the determination circuit includes a first input terminal connected to the global bit line and the first or second reference current. A second input terminal to which a level is given,
The third determination circuit has first and second input terminals connected to the global bit line via first and second selectors, respectively.
The first storage unit is connected to a first input terminal of the third determination circuit via a third selector,
The second storage unit is connected to the second input terminal of the third determination circuit via a fourth selector.

  In the semiconductor memory device of this embodiment, the storage state of the pair of storage units can be read by switching the column selector and the first to fourth selectors on and off. In addition, since the area occupied by the first, second, and third determination circuits can be reduced to two, the area of the semiconductor memory device can be reduced.

In the semiconductor memory device of one embodiment,
The memory cell
A semiconductor layer;
A gate electrode formed on the semiconductor layer via a gate insulating film;
A channel region having a certain conductivity type provided in a region corresponding to the surface of the semiconductor layer immediately below the gate electrode;
A pair of diffusion regions provided in regions corresponding to both sides of the gate electrode on the surface of the semiconductor layer, each having a conductivity type opposite to that of the channel region;
A pair of memory function bodies provided on the respective diffusion regions so as to be in contact with corresponding side surfaces of the gate electrode and having a function of holding charge or polarization, respectively;
The pair of diffusion regions of the memory cell each have a terminal connected to a bit line.

  In the semiconductor memory device of this embodiment, the information of each memory function body can be written, erased and read by switching the applied voltages to the pair of diffusion regions. That is, the pair of memory function bodies function as the pair of storage units. Accordingly, 2 bits can be stored and read out per memory cell. The memory cell is similar in structure to a transistor element generally used in a logic circuit as compared with a typical nonvolatile memory such as an EPROM or a flash memory. Therefore, the memory portion and the logic circuit portion can be easily mixed on the same semiconductor substrate with a simple manufacturing process.

In the semiconductor memory device of one embodiment,
The memory cell
A semiconductor layer;
A gate electrode formed on the semiconductor layer;
A composite gate insulating film comprising a stack of first, second and third insulating films sandwiched between the semiconductor layer and the gate electrode;
A channel region having a certain conductivity type provided in a region corresponding to the surface of the semiconductor layer immediately below the gate electrode;
A pair of diffusion regions provided in regions corresponding to both sides of the gate electrode in the surface of the semiconductor layer, each having a conductivity type opposite to that of the channel region;
The second insulating film sandwiched between the first and third insulating films of the composite gate insulating film has a pair of storage regions each having a function of holding charge or polarization at the end corresponding to each diffusion region. With
The pair of diffusion regions of the memory cell each have a terminal connected to a bit line.

  In the semiconductor memory device of this embodiment, information in each memory area of the second insulating film can be written, erased, and read by switching the voltages applied to the pair of diffusion areas. That is, the pair of storage areas function as the pair of storage units. Accordingly, 2 bits can be stored and read out per memory cell. In addition, since each storage area is formed immediately above the channel area, the current difference due to the amount of charges stored in the storage area is large, and the writing / erasing speed is high. Further, the shape of the second insulating film in which the memory region is formed is simple, and there is little variation in element characteristics due to manufacturing variations of the second insulating film.

  An electronic apparatus according to the present invention includes the semiconductor memory device.

  In the electronic apparatus according to the present invention, the read operation of the semiconductor memory device is more stable and more reliable than the conventional one, so that the reliability is increased.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

  FIG. 1A illustrates a cross-sectional structure of a memory cell included in a semiconductor memory device of the present invention. A P-type well region 14 forming a channel region is formed on the surface of the semiconductor substrate 10 as a semiconductor layer. This memory cell includes a gate electrode 11 formed on a P-type well region 14 via a gate insulating film 13. A pair of N-type diffusion regions 15 a and 15 b each functioning as a source region or a drain region are formed in regions corresponding to both sides of the gate electrode 11 in the P-type well region 14. The diffusion regions 15a and 15b do not reach the region immediately below the gate electrode 11, and a gap (offset region) is provided between the gate electrode 11 and the diffusion regions 15a and 15b in the channel direction (lateral direction in the figure). It has been. That is, an offset structure is formed. On the diffusion regions 15a and 15b, a pair of memory function bodies 12a and 12b is provided as a storage unit so as to cover the offset region and to be in contact with the corresponding side surface of the gate electrode 11, respectively.

  The memory function bodies 12a and 12b each have a function of holding charge or polarization. A silicon nitride film, a ferroelectric film, or the like can be used as a film having a function of maintaining charge or polarization in the memory function bodies 12a and 12b. Note that, as a configuration of the memory function body, the upper and lower sides of the film that holds the charge or polarization may be covered with an insulating film typified by a silicon oxide film so as to hold the charge or polarization for a longer period. For example, when a silicon nitride film is used as a film having a function of holding charges, the memory function bodies 12a and 12b may have a three-layer structure of silicon oxide film-silicon nitride film-silicon oxide film.

  Further, as another configuration example of the memory function bodies 12a and 12b, the memory function bodies 12a and 12b may have a structure in which fine particles made of a nanometer-sized conductor or semiconductor are distributed in a scattered manner in the insulating film.

  Note that the memory function body is not limited to the above configuration, and may have another configuration as long as it has a function of holding charge or polarization.

  Next, a program (write) operation of the memory cell shown in FIG. 1A will be described. Here, the case where the entire memory function bodies 12a and 12b have a function of holding charges will be described. The program (write) refers to injecting electrons into the memory function bodies 12a and 12b when the memory cell is an N-channel type as in this example. In the following description, the memory cell is assumed to be an N-channel type.

  In order to program by injecting electrons into the memory function body 12b, the N-type diffusion region 15a is handled as a source region, and the N-type diffusion region 15b is handled as a drain region. For example, 0V is applied to the diffusion region 15a and the P-type well region 14, + 5V is applied to the diffusion region 15b, and + 5V is applied to the gate electrode 11.

  Under such a voltage condition, the inversion layer extends from the diffusion region 15a (source region), but a pinch-off point is generated without reaching the diffusion region 15b (drain region). The electrons are accelerated by a high electric field from the pinch-off point to the diffusion region 15b (drain region), and become so-called hot electrons (high energy conduction electrons). Writing is performed by injecting the hot electrons into the memory function body 12b. In the vicinity of the memory function body 12a, no hot electrons are generated, so that writing is not performed.

  On the other hand, in order to program by injecting electrons into the memory function body 12a, the diffusion region 15b is treated as a source region and the diffusion region 15a is treated as a drain region. For example, 0V is applied to the diffusion region 15b and the P-type well region 14, + 5V is applied to the diffusion region 15a, and + 5V is applied to the gate electrode 11.

  As described above, the electrons are injected into the memory function body 12a by switching the applied voltages to the diffusion regions (source / drain regions) 15a and 15b in the case of injecting electrons into the memory function body 12b. be able to.

  Next, the erase operation will be described.

  In order to erase the information stored in the memory function body 12a, a positive voltage (for example, + 5V) is applied to the diffusion region 15a, and 0V is applied to the P-type well region 14, and the diffusion region 15a, the P-type well region 14 and A reverse bias is applied to the PN junction, and a negative voltage (for example, −5 V) is applied to the gate electrode 11. At this time, in the vicinity of the gate electrode 11 in the PN junction, the potential gradient is particularly steep due to the influence of the gate electrode to which a negative voltage is applied. Therefore, hot holes (high energy holes) are generated on the P-type well region 14 side of the PN junction due to the band-to-band tunnel. This hot hole is drawn in the direction of the gate electrode 11 having a negative potential, and as a result, hole injection is performed in the memory function body 12a. In this way, the memory function body 12a is erased. At this time, 0 V may be applied to the diffusion region 15b.

  When erasing the information stored in the memory function body 12b, the potentials of the diffusion region 15a and the diffusion region 15b may be switched in the above.

  Next, a method for reading the information stored as described above will be described.

  When reading the information stored in the memory function body 12a, the leftward current path in FIG. 1A is set as the first current path, and the diffusion region 15a is treated as the source region and the diffusion region 15b is treated as the drain region. For example, 0V is applied to the diffusion region 15a and the P-type well region 14, + 1V is applied to the diffusion region 15b, and + 3V is applied to the gate electrode 11. At this time, if electrons are not accumulated in the memory function body 12a, a drain current tends to flow. On the other hand, when electrons are accumulated in the first memory function body 12a, the inversion layer is not easily formed in the vicinity of the memory function body 12a, and therefore, the drain current hardly flows. Therefore, the storage information of the memory function body 12a can be read by detecting the drain current.

  When reading the information stored in the memory function body 12b, the current path in the right direction in FIG. 1A is set as the second current path, and the diffusion region 15b is treated as the source region and the diffusion region 15a is treated as the drain region. For example, 0V may be applied to the diffusion region 15b and the P-type well region 14, + 1V may be applied to the diffusion region 15a, and + 3V may be applied to the gate electrode 11.

  As described above, the information stored in the memory function body 12b can be read by switching the voltage applied to the diffusion regions (source / drain regions) 15a and 15b in the case of reading the information stored in the memory function body 12a. Can be done.

  As described above, it is possible to store and read 2 bits per memory cell by switching the voltage applied to the pair of diffusion regions 15a and 15b.

  The memory cell shown in FIG. 1A is similar in structure to a transistor element generally used in a logic circuit as compared with a conventional EPROM or flash memory which is a typical nonvolatile memory. Therefore, the memory portion and the logic circuit portion can be mixedly mounted on the same semiconductor substrate with a simple manufacturing process.

  In addition, there is an advantage that the gate insulating film can be easily thinned and miniaturized easily.

  In order to represent the memory cell shown in FIG. 1A, a circuit symbol shown in FIG. 1B is used in a circuit diagram to be described later.

  FIG. 7 illustrates a current level distribution in the case where 1 bit is stored in each of the memory function bodies 12a and 12b of the plurality of memory cells (shown in FIG. 1A). In FIG. 7, the horizontal axis represents current, and the vertical axis represents the number of elements through which the current flows during reading. Here, “00” indicates that both the memory function body on the reading side and the memory function body on the opposite side to the reading side are in the program state, and “01” indicates that the memory function body on the reading side is in the program state. The memory function body on the opposite side to the read side is in the erased state, “10” indicates that the memory function body on the read side is in the erased state, and the memory function body on the opposite side to the read side is in the programmed state “11” indicates that both the memory function body on the reading side and the memory function body on the opposite side to the reading side are both in the erased state.

  For example, when a leftward current path is set, the current flowing through the memory cell takes the minimum value 103 when both memory function bodies 12a and 12b are in the programmed state (corresponding to “00”). When the memory function body 12a on the left side according to the direction of the memory is in the program state and the memory function body 12b on the right side is in the erased state (corresponding to “01”), the first intermediate value 104 larger than the minimum value 103 is taken. When the memory function body 12a of the memory device 12a is in the erased state and the memory function body 12b on the right side is in the program state (corresponding to “10”), the second intermediate value 105 larger than the first intermediate value 104 is taken. When the bodies 12a and 12b are in the erased state (corresponding to “11”), the maximum value 106 larger than the second intermediate value 105 is taken.

  On the contrary, when the right current path is set, the current flowing through the memory cell takes the minimum value 103 when both the memory function bodies 12a and 12b are in the programmed state (corresponding to “00”). When the right memory function body 12b corresponding to the direction of current is in the program state and the left memory function body 12a is in the erased state (corresponding to “01”), the first intermediate value 104 larger than the minimum value 103 is taken. When the right memory function body 12b12a is in the erased state and the left memory function body 12a is in the programmed state (corresponding to “10”), the second intermediate value 105, which is larger than the first intermediate value 104, is taken. When the memory function bodies 12a and 12b are in the erased state (corresponding to “11”), the maximum value 106 larger than the second intermediate value 105 is taken.

  In particular, when the drain current in the linear region of the transistor serving as the memory element is used as the read current, the read current is affected by the storage state of the memory function body on the opposite side to the memory function body on the read side.

  As shown in FIG. 7, if there is no overlap between the distribution of the first intermediate value 104 and the distribution of the second intermediate value 105, the reference current level 101 is set in the gap between the distributions. Then, by comparing the read current of the memory cell with the reference current level 101, the information stored in the memory function body to be read is read.

  However, when viewed from the whole memory cell included in the semiconductor memory device, as shown in FIG. 6, the distribution of the first intermediate value 94 and the distribution of the second intermediate value are equal to each other due to the characteristic variation of the memory cell. In some cases, if only one reference current level is used, there is not a sufficient current margin for accurately determining the storage state of each of the memory function bodies 12a and 12b in the determination circuit. Therefore, in the present invention, the first reference current level 91 that is larger than the minimum value 93 and smaller than the second intermediate value 95 and the maximum value 96 that is larger than the first intermediate value 94 and common to a plurality of memory cells. And a second reference current level 92 that is smaller than the second reference current level 92. The first reference current level 91 can be set with a margin between the distribution of the minimum value 93 and the distribution of the second intermediate value 95. Further, the second reference current level 92 can be set with a margin between the distribution of the first intermediate value 91 and the distribution of the maximum value 96. Then, when the leftward or rightward current path is set, the current flowing through the memory cell is compared with the first and second reference current levels 91 and 92, respectively. Thereby, when both the memory function bodies 12a and 12b are in the program state, or when both the memory function bodies 12a and 12b are in the erased state, this can be accurately determined. Further, when one of the memory function bodies is in the programmed state and the other memory function body is in the erased state, as described later, the charge amount stored in the first storage section and the second storage section Is determined based on the result of comparison with the amount of charge stored in the.

  FIG. 2A illustrates a cross-sectional structure of another memory cell included in the semiconductor memory device of the present invention. A P-type well region 25 forming a channel region is formed on the surface of the semiconductor substrate 20 as a semiconductor layer. This memory cell includes a gate electrode 21 formed on a P-type well region 25 via a composite gate insulating film 28. A pair of N-type diffusion regions 26 a and 26 b each functioning as a source region or a drain region are formed in regions corresponding to both sides of the gate electrode 21 in the P-type well region 25. The gate insulating film 28 is formed by stacking a first insulating film 22, a second insulating film 23, and a third insulating film 24. The second insulating film 23 sandwiched between the first insulating film 22 and the third insulating film 24 has a function of holding charges or polarization at the end portions corresponding to the diffusion regions 26a and 26b, respectively. A pair of storage areas 27a and 27b is provided as a storage unit. As the second insulating film 23, a silicon nitride film or the like can be used as a film that has a function of holding electric charges and hardly causes interference between the storage regions 27a and 27b. Note that the second insulating film 23 is not limited to the above-described configuration, and is formed of a film that has a function of maintaining charge or polarization and that hardly causes interference between the storage regions 27a and 27b at both ends. Just do it.

  Next, the program operation of the memory cell shown in FIG. 2A will be described.

  In order to program by injecting electrons into the storage region 27b, the N-type diffusion region 26a is handled as a source region, and the N-type diffusion region 26b is handled as a drain region. For example, 0V is applied to the diffusion region 26a and the P-type well region 25, + 4.5V is applied to the diffusion region 26b, and + 9V is applied to the gate electrode 21.

  Under such a voltage condition, hot electrons are generated in the boundary region of the channel region formed in the P-type well region 25 with the diffusion region, and writing is performed by injecting the hot electrons into the storage region 27b. Is done. Note that no writing is performed in the vicinity of the storage area 27a because hot electrons are not generated.

  On the other hand, in order to program by injecting electrons into the storage region 27a, the diffusion region 26b is treated as a source region and the diffusion region 26a is treated as a drain region. For example, 0V is applied to the diffusion region 26b and the P-type well region 25, + 4.5V is applied to the diffusion region 26a, and + 9V is applied to the gate electrode 21.

  In this way, programming can be performed by injecting electrons into the storage region 27a by switching the voltage applied to the diffusion regions (source / drain regions) 26a and 26b in contrast to the case where electrons are injected into the storage region 27b. it can.

  Next, the erase operation will be described.

  In order to erase the information stored in the storage region 27a, a positive voltage (for example, + 5.5V) is applied to the diffusion region 27a, and 0V is applied to the P-type well region 25, so that the diffusion region 26a and the P-type well region 25 are applied. And a negative voltage (for example, −8 V) is applied to the gate electrode 21. At this time, in the vicinity of the gate electrode 21 in the PN junction, the potential gradient is particularly steep due to the influence of the gate electrode to which a negative voltage is applied. Therefore, a hot hole is generated on the P-type well region 25 side of the PN junction due to the band-to-band tunnel. This hot hole is drawn in the direction of the gate electrode 21 having a negative potential, and as a result, hole injection is performed in the storage region 27a. In this way, the storage area 27a is erased. At this time, 0 V may be applied to the diffusion region 27b.

  When erasing the information stored in the storage area 27b, the potentials of the diffusion area 26a and the diffusion area 26b may be switched in the above.

  Next, a method for reading the information stored as described above will be described.

  When reading the information stored in the storage area 27a, the diffusion area 26a is treated as a source area and the diffusion area 26b is treated as a drain area. For example, 0V is applied to the diffusion region 26a and the P-type well region 25, + 1.2V is applied to the diffusion region 26b, and + 3.5V is applied to the gate electrode 21. At this time, if electrons are not accumulated in the storage area 27a, a drain current tends to flow. On the other hand, when electrons are accumulated in the first storage area 27a, an inversion layer is hardly formed in the vicinity of the storage area 27a, so that a drain current hardly flows. Therefore, the storage information in the storage area 27a can be read by detecting the drain current.

  When reading the information stored in the storage area 27b, the diffusion area 26b is treated as a source area and the diffusion area 26a is treated as a drain area. For example, 0V may be applied to the diffusion region 26b and the P-type well region 25, + 1.2V to the diffusion region 26a, and + 3.5V to the gate electrode 21.

  As described above, the information stored in the storage area 27b is read by switching the voltage applied to the diffusion areas (source / drain areas) 26a and 26b as compared with the case of reading the information stored in the storage area 27a. Can do.

  As described above, it is possible to store and read 2 bits per memory cell by switching the voltage applied to the pair of diffusion regions 26a and 26b.

  In the memory cell shown in FIG. 2A, since the storage regions 27a and 27b are formed immediately above the P-type well region 25 that forms the channel region, the current difference due to the large amount of charges stored in the storage regions 27a and 27b is large. And the speed of writing and erasing is also fast. In addition, the shape of the insulating film 23 in which the memory regions 27a and 27b are formed is simple, and there is little variation in element characteristics due to manufacturing variations of the insulating film in which the memory regions are formed.

  Note that the circuit symbol shown in FIG. 2B can be used to represent the memory cell shown in FIG. 2A.

  The relationship between the storage state of the storage area and the current level in the memory cell shown in FIG. 2A can be described with reference to FIGS. 7 and 6, just like FIG. 1A.

  Note that the voltage applied to each terminal in each of the program, erase, and read operations of the memory cell shown in FIGS. 1A and 2A is not limited to the above value, and may be higher or lower. I do not care.

(First embodiment)
FIG. 3 shows a circuit configuration of the semiconductor memory device according to the embodiment of the present invention. Note that the memory cell of this semiconductor memory device has the structure shown in FIG. 1A, and is represented in FIG. 3 by using the circuit symbol shown in FIG. 1B.

  As the memory cell, the memory cell shown in FIG. 2A may be used regardless of the memory cell shown in FIG. 1A. The memory cell shown in FIG. 1A and the memory cell shown in FIG. 2A are similar in write / erase / read methods, and the gate electrode 11 is replaced with 21, the diffusion region 15a is replaced with 26a, and the diffusion region 15b is replaced with 26b. By optimizing the voltage applied during operation, the memory cell shown in FIG. 1A can be easily replaced with the memory cell shown in FIG. 2A.

  The semiconductor memory device shown in FIG. 3 generally includes memory cells 39a to 39d constituting a memory cell array, column selectors 38a to 38e made of N channel type MOS transistors, and selectors 35a to 35d made of N channel type MOS transistors. And accumulating units 33a and 33c composed of capacitors, and determination circuits 32a to 32c composed of comparators.

  In this memory cell array, the memory cells shown in FIG. 1A are arranged in a matrix, but for simplicity, only one row of memory cells 39a to 39d electrically connected in series is illustrated. The gate electrodes of these memory cells are connected to word lines 40 extending in the row direction for each row. Connection portions between the memory cells are connection portions between the corresponding diffusion regions 15a and 15b (see FIG. 1A). Bit lines 41a to 41e extending in the column direction are connected to connection portions between these memory cells. A global bit line 42 is connected to these bit lines 41a to 41e via column selectors 38a to 38e. The bit lines 41a to 41e, the column selectors 38a to 38e, the global bit line 42, and a bias applying unit (not shown) that applies a bias to these bit lines include a current path setting unit that sets a left or right current path in each memory cell. It is composed.

  The first determination circuit 32 a has a first input terminal connected to the global bit line 42 and a second input terminal 34 a to which a first reference current level 91 is applied.

  The second determination circuit 32c has a first input terminal connected to the global bit line 42, and a second input terminal 34c to which a second reference current level 92 is applied.

  The first storage unit 33a is connected to the global bit line 42 via the first selector 35a.

  The second storage unit 33c is connected to the global bit line 42 via the second selector 35a.

  The third determination circuit 32b is connected to the first input terminal connected to the first storage unit 33a via the third selector 35b, and connected to the second storage unit 33c via the fourth selector 35c. And a second input terminal.

  As an example, a method of reading information stored in the pair of memory function bodies 39b1 and 39b2 of the memory cell 39b will be described below.

  In the following, the step of setting a right current path for each memory cell in FIG. 3 and reading the current mainly corresponding to the storage information of the memory function body that the memory cell has on the right side is referred to as “right current. This is referred to as “reading by path”. Further, in FIG. 3, a step of setting a left current path for each memory cell and reading the current mainly corresponding to the storage information of the memory function body that the memory cell has on the left side is referred to as “reading in the left current path”. "

  First, reading in the leftward current path is performed. Specifically, 3V is applied to the word line 40, the bit lines 41a and 41b are grounded, and 1V is applied to the bit lines 41c, 41d, and 41e. At this time, a read current mainly corresponding to the charge stored in the memory function body 39b1 on the left side of the memory cell 39b flows from the bit line 41c, and the potential of the bit line 41c also changes according to the amount of the current.

  On the other hand, the voltage is applied to the control line 37c to turn on the column selector 38c, and the other column selectors 38a, 38b, 38d, and 38e are turned off to electrically connect the bit line 41c and the global bit line 42. Connect.

  In the determination circuits 32a and 32c, the magnitudes of the read current of the memory cell transmitted to the global bit line 42 and the first and second reference current levels 91 and 92 are respectively compared. The comparison results are output to the output terminals 31a and 31c, respectively.

  On the other hand, in parallel with this, or after obtaining the output results from the determination circuits 32a and 32c, by turning on the selector 35a, the charge corresponding to the state of the global bit line 42 is stored in the storage unit 33a. Accumulated.

  Next, reading is performed in the rightward current path. Specifically, 1V is applied to the bit lines 41a and 41b, and the bit lines 41c, 41d, and 41e are grounded. At this time, a read current mainly corresponding to the charge stored in the memory function body 39b2 on the right side of the memory cell 39b flows from the bit line 41b, and the potential of the bit line 41b also changes according to the amount of the current.

  On the other hand, the voltage is applied to the control line 37b to turn on the column selector 38b, and the other column selectors 38a, 38c, 38d, and 38e are turned off to electrically connect the bit line 41b and the global bit line 42. Connect.

  In the determination circuits 32a and 32c, the magnitudes of the read current of the memory cell transmitted to the global bit line 42 and the first and second reference current levels 91 and 92 are respectively compared. The comparison results are output to the output terminals 31a and 31c, respectively. This is the same as the case of reading the information stored in the left memory function body 39b1.

  On the other hand, in parallel with this, or after obtaining the output results from the determination circuits 32a and 32c, the selector 35d is turned on so that the charge corresponding to the voltage of the global bit line 42 is stored in the storage unit 33b. Accumulated.

  Next, the selectors 35a and 35d are turned off, and the selectors 35b and 35c are turned on. Thus, the determination circuit 32b compares the amount of charge stored in the storage unit 33a with the amount of charge stored in the storage unit 33b, and outputs the result from the output terminal 31b.

Table 1 shows the correspondence between the outputs 31a, 31b and 31c obtained as described above and the data stored in the memory function bodies 39b1 and 39b2 of the memory cell 39b.

  Here, the symbol “*” in Table 1 indicates that the data is determined without depending on the output result of the portion to which the symbol is attached.

  In the determination circuits 32a and 32c, “1” is output when the read current of the memory cell is larger than the first and second reference current levels 91 and 92, and the read current of the memory cell is the first and second. It is assumed that “0” is output when the reference current level is smaller than 2 reference current levels 91 and 92.

  In the determination circuit 31b, “1” is output when the amount of charge stored in the storage unit 33a is smaller than the amount of charge stored in the storage unit 33b, and conversely, the amount of charge stored in the storage unit 33a. Is greater than the amount of charge stored in the storage unit 33b, "0" is output.

  First, when the output 31a and the output 31c are both “0” in reading in the leftward current path (mainly reading from the memory function body 39b1), the storage state of the memory cell 39b is “00” in FIG. The state is “01”.

  Therefore, when the output 31a and the output 31b are both “0” in the right-direction reading (mainly reading the memory function body 39b2), “0” of the memory function body 39b1 and the memory function body 39b2 is When the output 31a is “1” and the output 31c is “0” or “1”, “0” of the memory function body 39b1 and “1” of the memory function body 39b2 are determined.

  Next, when the output 31a and the output 31b are both “1” in reading in the leftward current path (mainly reading the memory function body 39b1), the storage state of the memory cell 39b is “10” in FIG. Alternatively, the state is “11”.

  For this reason, when the output 31a and the output 31b are both “1” in the right-direction reading (mainly reading the memory function body 39b2), “1” of the memory function body 39b1 and the memory function body 39b2 is When the output 31a is “1” or “0” and the output 31c is “0”, “1” of the memory function body 39b1 and “0” of the memory function body 39b2 are determined.

  Further, when the output 31a is “0” and the output 31c is “1” in the reading in the leftward current path (mainly reading of the memory function body 39b1), the memory function body 39b1 and the memory function body 39b2 Is either “0” and the other is “1”.

  For this reason, when the output 31a and the output 31c are both “0” in the right-direction reading (mainly reading out the memory function body 39b2), “0” of the memory function body 39b1 and the memory function body 39b2 When “1” is confirmed and both the output 31a and the output 31c are “1”, “1” of the memory function body 39b1 and “0” of the memory function body 39b2 are confirmed.

  However, when the output 31a is “0” and the output 31c is “1” in the reading in the rightward current path (mainly reading from the memory function body 39b2), data is obtained only from the results of the output 31a and the output 31c. Cannot be determined.

  In this case, reference is made to the output 31b. When the output 31b is “0”, “0” of the memory function body 39b1 and “1” of the memory function body 39b2 are determined, and when the output 31b is “1”, the memory function body 39b1 “1” and “0” of the memory function body 39b2 are determined.

  Note that the output 31a is “0” in both reading in the left-direction current path (mainly reading out of the memory function body 39b1) and reading out in the right-direction current path (mainly reading out of the memory function body 39b2). In addition, since it is impossible in principle that the output 31b is “1”, if any output is performed, a read error signal (“Fail” signal) is output.

  As described above, in the conventional reading method, a large number of memory cells constituting the memory cell array are determined by one fixed reference, and current distribution 104 of “01” and “10” as shown in FIG. When reading a memory cell array having a sufficient current difference with respect to the current distribution 105, the reading can be performed accurately, but as shown in FIG. 6, the current distribution 94 of “01” and the current of “10” When the distribution 95 is not sufficiently separated (there is no current difference), it has been impossible to read accurately. On the other hand, in the present invention, as shown in FIG. 6, the first reference current level 91 is set between the current distribution 94 of “01” and the current distribution 96 of “11”, and “10”. The determination is performed by setting the second reference current level 92 between the current distribution 95 and the current distribution 96 of “11”. Therefore, the current distribution 93 of “00” and the current distribution 95 of “10” are far enough to be determined by the determination circuit, and the current distribution 94 of “01” and the current distribution 96 of “11” are In principle, it is possible to accurately read out information stored in the memory cell as long as the distance is far enough to be determined by the determination circuit.

  Therefore, as shown in FIG. 6, data can be read accurately even when reading memory cells in a memory cell array in which the current distribution 94 of “01” and the current distribution 95 of “10” are not sufficiently separated. That is, it is possible to realize reading with higher reliability that is strong against variations in characteristics between memory cells constituting the memory cell array.

  According to the read method of the present embodiment, the bit lines connected to the diffusion regions on both sides of the channel region of the memory cell from the start of the read operation until the data is determined and the read operation of the memory cell is completed. Therefore, a long access time is required as compared with the conventional reading method. However, since it is possible to read 2-bit information with a single read operation, when reading multi-bit data continuously, the access time is not greatly increased compared to the conventional read method. . In addition, as described above, even if there is a large variation in element characteristics between the memory cells and reading is impossible with the conventional reading method, the memory function of the memory cell is accurately determined according to the reading method of this embodiment. Information stored in the body can be read, and a more reliable and stable reading operation can be performed.

(Second Embodiment)
FIG. 4 shows a circuit configuration of a semiconductor memory device according to another embodiment of the present invention.

  This semiconductor memory device is generally characterized in that a single determination circuit 52 is provided in place of the three determination circuits 32a to 32c of the semiconductor memory device shown in FIG. Note that the reference numerals of the constituent elements in FIG. 4 are those obtained by adding 20 to the corresponding constituent elements in FIG.

  In this semiconductor memory device, the determination circuit 52 has first and second input terminals 63a and 63b connected to the global bit line 62 via first and second selectors 55a and 55b, respectively.

  The first storage unit 53a is connected to the first input terminal 63a of the determination circuit 52 via the third selector 55c, and the second input terminal 63b of the determination circuit 52 is connected to the second input via the fourth selector 55f. The storage unit 53b is connected.

  Reference input lines 54a and 54b are connected to first and second input terminals 63a and 63b of the determination circuit 52 via fifth and sixth selectors 55b and 55e, respectively. In this example, the reference input line 54a is switched between two types of levels, a first reference current level 91 and a second reference current level 92 in FIG. Similarly, the reference input line 54b is provided with two types of levels, a first reference current level 91 and a second reference current level 92 in FIG.

  As an example, a method of reading information stored in the memory function bodies 59b1 and 59b2 of the memory cell 59b will be described below.

  First, reading in the leftward current path is performed. Specifically, 3V is applied to the word line 60, the bit lines 61a and 61b are grounded, and 1V is applied to 61c, 61d, and 61e. At this time, a read current mainly corresponding to the charge stored in the memory function body 59b1 on the left side of the memory cell 59b flows from the bit line 61c, and the potential of the bit line 61c also changes according to the amount of the current.

  On the other hand, the voltage is applied to the control line 57c to turn on the column selector 58c, and the other column selectors 58a, 58b, 58d, 58e are turned off to electrically connect the bit line 61c and the global bit line 62. Connect.

  Furthermore, the current path from the memory cell 59b to the input terminal 63a of the determination circuit 52 is set by turning the selector 55a on and the selector 55d off.

  On the other hand, the reference input line 54b is connected to the input terminal 63b of the determination circuit 52 by turning on the selector 55e.

  As a result, the determination circuit 52 compares the read current of the memory cell transmitted to the global bit line 62 with the first and second reference current levels 91 and 92 applied to the reference input line 54b. .

  On the other hand, the charge corresponding to the state of the global bit line 62 is stored in the storage unit 53a by turning on the selector 55c in parallel with this or after obtaining the output result from the determination circuit 52. The

  Next, reading is performed in the rightward current path. Specifically, 1V is applied to the bit lines 61a and 61b, and the bit lines 61c, 61d, and 61e are grounded. At this time, a read current mainly corresponding to the charge stored in the memory function body 59b2 on the right side of the memory cell 59b flows from the bit line 61b, and the potential of the bit line 61b also changes according to the amount of the current.

  On the other hand, by applying a voltage to the control line 57b to turn on the column selector 58b and turning off the other column selectors 58a, 58c, 58d, and 58e, the bit line 61b and the global bit line 62 are electrically connected. Connect.

  Further, the current path from the memory cell 59b to the input terminal 63b of the determination circuit 52 is set by turning the selector 55d on and the selector 55a off.

  On the other hand, the reference input line 54a is connected to the input terminal 63a of the determination circuit 52 by turning on the selector 55b.

  As a result, the determination circuit 52 compares the read current of the memory cell transmitted to the global bit line 62 with the first and second reference current levels 91 and 92 applied to the reference input line 54a.

  On the other hand, in parallel with this, or after obtaining the output result from the determination circuit 52, the selector 55f is turned on and the selector 55c is turned off, so that the storage unit 53b is brought into the state of the global bit line 62. Accumulate the corresponding charge.

  Thereafter, the selectors 55c and 55f are turned on, and the selectors 55a, 55b, 55d, and 55e are turned off. Thereby, in the determination circuit 52, the amount of charge stored in the storage unit 53a is somewhat compared with the amount of charge stored in the storage unit 53b, and the result is output from the output terminal 51.

Table 2 shows the correspondence between the output 51 obtained as described above and the data stored in the memory function bodies 39b1 and 39b2 of the memory cell 39b.

  Here, “51-I” in Table 1 is a comparison result between the read current of the memory cell 59b and the first reference current level 91, and “51-II” is the read current of the memory cell 59b and the second reference current. As a result of comparison with the level 92, “51-III” indicates a comparison result between the charge amount stored in the storage unit 53a and the charge amount stored in 53b. “*” Indicates that the data is determined without depending on the output result of the part to which the symbol is attached.

  The determination circuit 52 outputs “1” when the read current of the memory cell is larger than the first and second reference current levels 91 and 92, and the read current of the memory cell is the first and second reference currents. It is assumed that “0” is output when the current level is lower than 91 and 92.

  Further, in the determination circuit 52, when the amount of charge stored in the storage unit 53a is smaller than the amount of charge stored in the storage unit 53b, “1” is output, and the amount of charge stored in 33a is stored in 33b. It is assumed that “0” is output when the charge amount is larger than the charged amount.

  First, in reading in the left current path (mainly reading of the memory function body 59b1), the comparison result with the first reference current level 91 and the comparison result with the second reference current level 92 input to the reference 54b are as follows. When both are “0”, the storage state of the memory cell 59b is “00” or “01” in FIG. For this reason, in the reading in the rightward current path (mainly reading out of the memory function body 59b2), the comparison result with the first reference current level 91 given to the reference input line 54b, the second reference current level 92 and When the comparison results are both “1”, “0” of the memory function body 59b1 and the memory function body 59b2 is determined, the comparison result with the first reference current level 91 is “1”, and the second When the comparison result with the reference current level 92 is “0” or “1”, “0” of the memory function body 59b1 and “1” of the memory function body 59b2 are determined.

  Next, in reading in the left current path (mainly reading of the memory function body 59b1), the comparison result with the first reference current level 91 and the comparison result with the second reference current level 92 are both “1”. In some cases, the storage state of the memory cell 59b is “10” or “11” in FIG. For this reason, in reading on the rightward current path (mainly reading of the memory function body 59b2), the comparison result with the first reference current level 91 and the comparison result with the second reference current level 92 are both “0”. In some cases, “1” of the memory function body 59b1 and the memory function body 59b2 is determined, the comparison result with the first reference current level 91 is “0” or “1”, and the second reference current level 92 When the comparison result is “1”, “1” of the memory function body 59b1 and “0” of the memory function body 59b2 are determined.

  Further, in the reading in the leftward current path (mainly reading out of the memory function body 59b1), the comparison result with the first reference current level 91 is “1” and the comparison with the second reference current level 92 is made. When the result is “1”, the storage state of the memory cell 59b is “01” or “10” in FIG.

  For this reason, in reading in the rightward current path (mainly reading of the memory function body 59b2), the comparison result with the first reference current level 91 and the comparison result with the second reference current level 92 are both “1”. In some cases, “0” of the memory function body 59b1 and “1” of the memory function body 59b2 are determined, and the comparison result with the first reference current level 91 and the comparison result with the second reference current level 92 are both In the case of “0”, “1” of the memory function body 59b1 and “0” of the memory function body 59b2 are determined.

  However, in reading in the rightward current path (mainly reading of the memory function body 59b2), the comparison result with the first reference current level 91 is “0” and the comparison with the second reference current level 92 is made. When the result is “1”, data cannot be read out only from the comparison result with the first and second reference current levels 91 and 92.

  In this case, the charge amount stored in the storage unit 53a is compared with the charge amount stored in the storage unit 53b. When the output of the determination circuit 52 is “0”, “0” of the memory function body 59b1 and “1” of the memory function body 59b2 are determined, and when the output of the determination circuit 52 is “1”, the memory “1” of the functional unit 59b1 and “0” of the memory functional unit 59b2 are determined.

  Note that in the reading in the leftward current path (mainly reading of the memory function body 59b1), the comparison result with the first reference current level 91 is “0”, and the comparison result with the second reference current level 92 is In the case of “1” and reading in the rightward current path (mainly reading of the memory function body 59b2), the comparison result with the first reference current level 91 is “1”, and the second reference current In principle, the comparison result with the level 92 cannot be “0”. Therefore, when such a comparison result is temporarily output, a read error signal (“Fail” signal) is output.

  The semiconductor memory device shown in FIG. 4 requires a longer access time for reading than the semiconductor memory device shown in FIG. 3, but the area occupied by the determination circuit in the semiconductor memory device can be reduced. The area of the storage device can be reduced.

(Third embodiment)
FIG. 5 shows a circuit configuration of a semiconductor memory device according to still another embodiment of the present invention. In addition, the code | symbol of the component in FIG. 5 shall add 20 further to the code | symbol of the corresponding component in FIG.

  In the semiconductor memory device shown in FIG. 4, the comparison between the read current from the memory cell and the reference current levels 91 and 92 and the comparison between the charge amounts stored in the two storage units 53a and 53b are performed in common. This is performed by one determination circuit 52. However, these two comparisons differ in the nature of the objects being compared. One input level is fixed in the magnitude comparison between the read current from the memory cell and the reference current levels 91 and 92, whereas in the comparison between the charge amounts stored in the two storage units 53a and 53b. , Both inputs change. As described above, the most sensitive sense sensitivity is required for the comparison between the read current from the memory cell and the reference current levels 91 and 92 and the comparison between the charge amounts stored in the two storage units 53a and 53b. The areas to be processed are greatly different, which may cause problems.

  Therefore, in the semiconductor memory device shown in FIG. 5, the determination circuit 72b for comparing the magnitude of the read current of the memory cell and the reference current levels 91 and 92, and the amount of charge stored in the two storage units 73a and 73b are compared. And a separate determination circuit 72a for comparing the two. In other words, the determination circuit 72b corresponds to a configuration in which the first and second determination circuits 32a and 32c in FIG. 3 are configured as one common determination circuit, and the determination circuit 72a is the third determination circuit in FIG. This corresponds to the circuit 32b.

  As shown in FIG. 5, the determination circuit 72b includes a first input terminal connected to the global bit line 82 and a second input terminal to which the first or second reference current levels 91 and 92 are switched. 74.

  The determination circuit 72b has first and second input terminals 83a and 83b connected to the global bit line 82 via first and second selectors 75a and 75b, respectively.

The first storage unit 73a is connected to the first input terminal 83a of the determination circuit 72b via the third selector 75b.
The second storage unit 73b is connected to the second input terminal 83b of the determination circuit 72b via the fourth selector 75d.

  As an example, a method of reading information stored in the memory function bodies 79b1 and 79b2 of the memory cell 79b will be described below.

  First, reading in the leftward current path is performed. Specifically, 3V is applied to the word line 80, the bit lines 81a and 81b are grounded, and 1V is applied to the bit lines 81c, 81d, and 81e. At this time, a read current mainly corresponding to the charge stored in the memory function body 79b1 on the left side of the memory cell 79b flows from the bit line 81c, and the potential of the bit line 81c also changes according to the amount of the current.

  On the other hand, the voltage is applied to the control line 77c to turn on the column selector 78c, and the other column selectors 78a, 78b, 78d, and 78e are turned off to electrically connect the bit line 81c and the global bit line 82. Connect.

  Thereafter, the determination circuit 72 b compares the read current of the memory cell transmitted to the global bit line 82 with the first and second reference current levels 91 and 92 applied to the reference input terminal 74. Thereby, the output 71b of the determination circuit 72b is obtained.

  Further, in parallel with this, or after obtaining the output result from the determination circuit 71b, the selectors 75a and 75b are turned on, and the selectors 75c and 75d are turned off, thereby bringing the global bit line 82 into a state. Corresponding charges are accumulated in the accumulating unit 73a.

  Next, reading is performed in the rightward current path. Specifically, with 3V applied to the word line 80, 1V is applied to the bit lines 81a and 81b, and the bit lines 81c, 81d, and 81e are grounded. At this time, a read current mainly corresponding to the charge stored in the memory function body 79b2 on the right side of the memory cell 79b flows from the bit line 81b, and the potential of the bit line 81b also changes according to the amount of the current.

  On the other hand, the voltage is applied to the control line 77b to turn on the column selector 78b, and the other column selectors 78a, 78c, 78d, and 78e are turned off to electrically connect the bit line 81b and the global bit line 82. Connect.

  Thereafter, the determination circuit 72 b compares the read current of the memory cell transmitted to the global bit line 82 with the first and second reference current levels 91 and 92 applied to the reference input terminal 74. Thereby, the output 71b of the determination circuit 72b is obtained.

  Further, in parallel with this, or after obtaining the output result from the determination circuit 72b, the selectors 75c and 75d are turned on and the selectors 75a and 75b are turned off, so that the state of the global bit line 82 is achieved. Corresponding charges are accumulated in the accumulating unit 73b.

  Further, after that, the selectors 75a and 75c are turned off and the selectors 55b and 55d are turned on. In the determination circuit 72a, the amount of charge stored in the storage unit 73a and the amount of charge stored in the storage unit 73b are somewhat different. The comparison is made and the result is output from the output terminal 71a.

Table 3 shows the correspondence between the outputs 71a and 71b and the data stored in the memory function bodies 79b1 and 79b2 of the memory cell 79b as described above.

  Here, “71-I” in Table 3 is a comparison result between the read current of the memory cell 79b and the first reference current level 91, and “71-II” is the read current of the memory cell 79b and the second reference current. Comparison results with level 92 are shown respectively. “*” Indicates that the data is determined without depending on the output result of the part to which the symbol is attached.

  The determination circuit 71b outputs “1” when the read current of the memory cell is larger than the first and second reference current levels 91 and 92, and the read current of the memory cell is the first and second read currents. It is assumed that “0” is output when it is smaller than the reference current levels 91 and 92.

  In the determination circuit 71a, “1” is output when the amount of charge stored in 73a is smaller than the amount of charge stored in 73b, and the amount of charge stored in 33a is greater than the amount of charge stored in 33b. If there are too many, “0” is output.

  First, in the reading in the leftward current path (mainly reading out of the memory function body 79b1), the comparison result with the first reference current level 91 and the comparison result with the second reference current level 92 are both “0”. In this case, the storage state of the memory cell 79b is “00” or “01” in FIG. For this reason, in reading on the rightward current path (mainly reading of the memory function body 79b2), the comparison result with the first reference current level 91 and the comparison result with the second reference current level 92 are both “0”. In some cases, “0” of the memory function body 79b1 and the memory function body 79b2 is fixed, the comparison result with the first reference current level 91 is “1”, and the second reference current level 92 is compared with the second reference current level 92. When the comparison result is “0” or “1”, “0” of the memory function body 79b1 and “1” of the memory function body 79b2 are determined.

  Next, in the reading in the leftward current path (mainly reading out of the memory function body 79b1), the comparison result with the first reference current level 91 and the comparison result with the second reference current level 92 are both “1”. In some cases, the storage state of the memory cell 79b is either “10” or “11” in FIG. Therefore, in the case of reading in the rightward current path (mainly reading of the memory function body 79b2), the comparison result with the first reference current level and the comparison result with the second reference current level are both “1”. Indicates that “1” of the memory function body 79b1 and the memory function body 79b2 is determined, the comparison result with the first reference current level is “1” or “0”, and the comparison result with the second reference current level Is “0”, “1” of the memory function body 79b1 and “0” of the memory function body 79b2 are determined.

  Further, in the reading in the leftward current path (mainly reading out of the memory function body 79b1), the comparison result with the first reference current level 91 is “1” and the comparison with the second reference current level 92 is made. When the result is “0”, the storage state of the memory cell 79b is “01” or “10” in FIG. For this reason, in reading on the rightward current path (mainly reading of the memory function body 79b2), the comparison result with the first reference current level 91 and the comparison result with the second reference current level 92 are both “0”. In some cases, “0” of the memory function body 79b1 and “1” of the memory function body 79b2 are determined, and the comparison result with the first reference current level 91 and the comparison result with the second reference current level 92 are both In the case of “1”, “1” of the memory function body 79b1 and “0” of the memory function body 79b2 are determined.

  However, in reading in the rightward current path (mainly reading out of the memory function body 79b2), the comparison result with the first reference current level 91 is “1”, and the comparison result with the second reference current level 92 is When it is “0”, data cannot be read out only from the comparison result with the first and second reference current levels 91 and 92.

  In this case, reference is made to the output 71a. When the output 71a is “0”, “0” of the memory function body 79b1 and “1” of the memory function body 79b2 are determined, and when the output 71a is “1”, “0” of the memory function body 79b1 is determined. 1 ”and“ 0 ”of the memory function body 79b2 are determined.

Note that the output 31a is “0” in both reading in the left-direction current path (mainly reading out of the memory function body 79b1) and reading out in the right-direction current path (mainly reading out of the memory function body 79b2). In principle, the output 31b cannot be “1”. Therefore, if such an output is performed, a read error signal (“Fail” signal) is output. The semiconductor memory device shown in FIG. 5 is read out in comparison with the semiconductor memory device shown in FIG. Therefore, the area occupied by the determination circuit in the semiconductor memory device can be reduced, so that the area of the entire semiconductor memory device can also be reduced.

  Further, since the semiconductor memory device illustrated in FIG. 5 can improve the accuracy of the determination circuit as compared with the semiconductor memory device illustrated in FIG. 4, a more reliable read operation can be realized. It becomes.

  In the first to third embodiments, the memory cell array is configured with a virtual ground array structure. However, the present invention is not limited to this and may be configured with another arrangement structure.

  Further, the power supply voltage for reading out the memory is not limited to the above voltage, and may be a voltage higher than this or a voltage lower than this.

(Fourth embodiment)
FIG. 8 shows a configuration of a mobile phone as an electronic apparatus in which the semiconductor memory device is incorporated.

  This mobile phone includes a display unit 111, a ROM (read only memory) 112, a RAM (random access memory) 113, a control circuit 114, an antenna 115, a radio circuit 116, a power circuit 117, an audio circuit 118, a camera module 119, a memory card. 120.

  Of these, the ROM 112 is built in the main body of the mobile phone shown in FIG. 8, and is nonvolatile and rewritable, and is taken by the camera module 119, program data for operating the control circuit. Data such as image data and audio data to be reproduced by the audio circuit 118 are stored.

  The data may be stored in the memory card 120. Similar to the ROM 112, the memory card 120 has non-volatility and is rewritable. The memory card 120 is further detachable, and plays a role such as backup of the data, data transfer to other devices, and storage of data that cannot be stored in the ROM 112.

  The ROM 112 and the memory card 120 send stored data to the control circuit 114 when requested by the control circuit 114. Data read from the ROM 112 and the memory card 120 is also transferred to the RAM 113 as necessary.

  In general, the reliability of nonvolatile memory plays a major role in the reliability of mobile phones. For this reason, high reliability is required for reading information stored in the ROM 1122 and the memory card 120 which are nonvolatile memories. For this reason, there has been a demand for a nonvolatile memory capable of performing a more reliable read operation.

  By using the semiconductor memory device of the present invention for the ROM 112 and the memory card 120, a more reliable reading operation can be performed and a more reliable mobile phone can be obtained.

  In particular, by using the memory element shown in FIG. 1A as a memory cell of a semiconductor memory device, a semiconductor memory device in which a mixed process of a memory portion and a logic circuit portion is simple and inexpensive can be obtained. Therefore, it is possible to obtain a portable electronic device that is highly reliable and inexpensive.

It is a figure which shows the cross-section of the memory cell in the semiconductor memory device of one Embodiment of this invention. It is a figure which shows the circuit symbol showing the memory cell of FIG. 1A. It is a figure which shows the cross-section of another memory cell in the said semiconductor memory device. It is a figure which shows the circuit symbol showing the memory cell of FIG. 2A. It is a figure which shows the circuit structure of the semiconductor memory device of one Embodiment of this invention. It is a figure which shows the circuit structure of the semiconductor memory device of another embodiment of this invention. It is a figure which shows the circuit structure of the semiconductor memory device of further another embodiment of this invention. FIG. 3 is a schematic diagram for explaining a distribution of current flowing through a memory cell and first and second reference current levels in the semiconductor memory device. It is the schematic for demonstrating another distribution of the electric current which flows into a memory cell, and a reference current level. It is a schematic block diagram of the portable electronic device incorporating the semiconductor memory device of this invention. It is a figure which shows the circuit structure of the conventional semiconductor memory device. It is the schematic for demonstrating distribution of the electric current which flows into the memory cell contained in the conventional semiconductor memory device, and a reference current level.

Explanation of symbols

39b1, 39b2, 59b1, 59b2, 79b1, 79b2 Memory function bodies 39a-39d, 59a-59d, 79a-79d Memory cells 91, 92 Reference current levels 41a-41d, 61a-61d, 81a-81d Bit lines 38a-38e, 58a-58e, 78a-78e Column selectors 35a-35d, 55a-55f, 75a-75d Selectors 42, 62, 82 Global bit lines 31a-31c, 51, 71a, 71b Determination circuits 33a, 33b, 53a, 53b, 73a, 73b Storage part 11, 21 Gate electrode 13, 28 Gate insulating film 14, 25 Channel region 15a, 15b, 26a, 26b Diffusion region 12a, 12b Memory function body 22, 23, 24 Insulating film 27a, 27b Storage region

Claims (8)

A reading method for a semiconductor memory device, which reads out the storage states of the pair of storage units of a plurality of memory cells having a pair of storage units capable of storing mutually independent information using first and second current paths opposite to each other. Because
The current flowing through each memory cell takes a minimum value when both storage units are in the programmed state in each current path, and one storage unit corresponding to the direction of the current is in the programmed state and the other storage unit. Takes a first intermediate value greater than the minimum value when the first storage unit is in the erased state, and a second intermediate value greater than the first intermediate value when the one storage unit is in the erased state and the other storage unit is in the programmed state Taking a value and taking a maximum value greater than the second intermediate value when both storage parts are in the erased state,
In common with the plurality of memory cells, a first reference current level that is greater than the minimum value and less than the second intermediate value, and a second reference current level that is greater than the first intermediate value and less than the maximum value. Define the reference current level,
The first current path is set, the current flowing through the memory cell is compared with the first and second reference current levels, and the charge corresponding to the current flowing through the memory cell is stored in the first storage. Store in the department,
The second current path is set to compare the current flowing through the memory cell with the first and second reference current levels, respectively, and charge corresponding to the current flowing through the memory cell is stored in the second storage. Store in the department,
A method for reading a semiconductor memory device, comprising: comparing a charge amount stored in the first storage unit with a charge amount stored in the second storage unit. A plurality of memories having a pair of storage units capable of storing mutually independent information, and the storage states of the pair of storage units being read using first and second current paths opposite to each other With cells,
The current flowing through each memory cell takes a minimum value when both storage units are in the programmed state in each current path, and one storage unit corresponding to the direction of the current is in the programmed state and the other storage unit. Takes a first intermediate value greater than the minimum value when the first storage unit is in the erased state, and a second intermediate value greater than the first intermediate value when the one storage unit is in the erased state and the other storage unit is in the programmed state Taking a value and taking a maximum value greater than the second intermediate value when both storage parts are in the erased state,
In common with the plurality of memory cells, a first reference current level that is greater than the minimum value and less than the second intermediate value, and a second reference current level that is greater than the first intermediate value and less than the maximum value. A reference current level is defined,
A current path setting unit for sequentially setting the current paths;
A first determination circuit that compares a current flowing through the memory cell with the first reference current level when each of the current paths is set;
A second determination circuit that compares a current flowing through the memory cell with the second reference current level when each of the current paths is set;
When the first current path is set, a first accumulation unit that accumulates electric charge according to the current flowing through the memory cell;
When the second current path is set, a second accumulation unit that accumulates electric charge according to the current flowing through the memory cell;
A semiconductor memory device, comprising: a third determination circuit that compares the amount of charge stored in the first storage unit with the amount of charge stored in the second storage unit. The semiconductor memory device according to claim 2,
The current path setting unit includes first and second bit lines connected to two terminals of the memory cell, and a global bit line connected to the first and second bit lines via a column selector. Including
The first and second determination circuits have a first input terminal connected to the global bit line, and a second input terminal to which the first or second reference current level is applied,
The first and second storage units are connected to the global bit line via first and second selectors, respectively.
The third determination circuit includes a first input terminal connected to the first storage unit via a third selector, and a first input terminal connected to the second storage unit via a fourth selector. A semiconductor memory device having two input terminals. The semiconductor memory device according to claim 2,
The current path setting unit includes first and second bit lines connected to two terminals of the memory cell, and a global bit line connected to the first and second bit lines via a column selector. Including
The first, second, and third determination circuits are configured as a common determination circuit, and the determination circuit is connected to the global bit line via a first selector and a second selector, respectively. A second input terminal;
The first storage unit is connected to a first input terminal of the determination circuit via a third selector,
The second storage unit is connected to a second input terminal of the determination circuit via a fourth selector,
The semiconductor memory device, wherein the first or second reference current level is applied to the first and second input terminals of the determination circuit via the fifth and sixth selectors, respectively. . The semiconductor memory device according to claim 2,
The current path setting unit includes first and second bit lines connected to two terminals of the memory cell, and a global bit line connected to the first and second bit lines via a column selector. Including
The first and second determination circuits are configured as one common determination circuit, and the determination circuit includes a first input terminal connected to the global bit line and the first or second reference current. A second input terminal to which a level is given,
The third determination circuit has first and second input terminals connected to the global bit line via first and second selectors, respectively.
The first storage unit is connected to a first input terminal of the third determination circuit via a third selector,
A semiconductor memory device, wherein the second storage section is connected to a second input terminal of the third determination circuit via a fourth selector. The semiconductor memory device according to claim 2,
The memory cell
A semiconductor layer;
A gate electrode formed on the semiconductor layer via a gate insulating film;
A channel region having a certain conductivity type provided in a region corresponding to the surface of the semiconductor layer immediately below the gate electrode;
A pair of diffusion regions provided in regions corresponding to both sides of the gate electrode on the surface of the semiconductor layer, each having a conductivity type opposite to that of the channel region;
A pair of memory function bodies provided on the respective diffusion regions so as to be in contact with corresponding side surfaces of the gate electrode and having a function of holding charge or polarization, respectively;
2. A semiconductor memory device according to claim 1, wherein each of the pair of diffusion regions of the memory cell forms a terminal connected to a bit line. The semiconductor memory device according to claim 2,
The memory cell
A semiconductor layer;
A gate electrode formed on the semiconductor layer;
A composite gate insulating film comprising a stack of first, second and third insulating films sandwiched between the semiconductor layer and the gate electrode;
A channel region having a certain conductivity type provided in a region corresponding to the surface of the semiconductor layer immediately below the gate electrode;
A pair of diffusion regions provided in regions corresponding to both sides of the gate electrode in the surface of the semiconductor layer, each having a conductivity type opposite to that of the channel region;
The second insulating film sandwiched between the first and third insulating films of the composite gate insulating film has a pair of storage regions each having a function of holding charge or polarization at the end corresponding to each diffusion region. With
2. A semiconductor memory device according to claim 1, wherein each of the pair of diffusion regions of the memory cell forms a terminal connected to a bit line. An electronic apparatus comprising the semiconductor memory device according to claim 2.

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