JP4521534B2 - Connection method between boards - Google Patents

Connection method between boards Download PDF

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Publication number
JP4521534B2
JP4521534B2 JP2006140644A JP2006140644A JP4521534B2 JP 4521534 B2 JP4521534 B2 JP 4521534B2 JP 2006140644 A JP2006140644 A JP 2006140644A JP 2006140644 A JP2006140644 A JP 2006140644A JP 4521534 B2 JP4521534 B2 JP 4521534B2
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Prior art keywords
substrates
connection method
metal wire
chip
quasi
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JP2007312229A (en
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弘毅 山森
彰 東海林
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National Institute of Advanced Industrial Science and Technology AIST
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National Institute of Advanced Industrial Science and Technology AIST
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Landscapes

  • Waveguide Connection Structure (AREA)
  • Waveguides (AREA)
  • Combinations Of Printed Boards (AREA)

Description

本願発明は、マイクロ波を代表とする高周波信号を基板間でインピーダンスミスマッチに起因するリターンロスが少なくなるように接続したジョセフソン電圧標準用チップとプリント基板から構成されるジョセフソン電圧標準装置等に関する。   The present invention relates to a Josephson voltage standard device composed of a Josephson voltage standard chip and a printed circuit board in which a high-frequency signal typified by a microwave is connected between substrates so as to reduce return loss due to impedance mismatch. .

ジョセフソン電圧標準装置は、周波数を正確に電圧に変換できる交流ジョセフソン効果という物理法則に基づいている。ジョセフソン電圧標準装置は、一般に電圧−周波数変換器とみなすことができる。ジョセフソン接合に周波数ｆの交流を印加すると、電圧Ｖ＝ｆ／ＫＪ（ＫＪ＝４８３５９７．９ＧＨｚ／Ｖ；ジョセフソン定数）の整数倍のステップ電圧が得られる。周波数は、非常に精度の良い物理量であるため、周波数と物理定数のみで定まるこの電圧もまた、周波数と同程度の正確さが得られる。 The Josephson voltage standard is based on the physical law of AC Josephson effect that can accurately convert frequency to voltage. The Josephson voltage standard device can generally be considered a voltage-frequency converter. When an alternating current with a frequency f is applied to the Josephson junction, a step voltage that is an integral multiple of the voltage V = f / K J (K J = 483597.9 GHz / V; Josephson constant) is obtained. Since the frequency is a highly accurate physical quantity, this voltage determined only by the frequency and the physical constant can also be as accurate as the frequency.

ジョセフソン電圧標準チップは、チップキャリア上に実装され、同軸ケーブルを通してマイクロ波が供給される。シリコンなどを材料とするチップ上のジョセフソン接合にマイクロ波を供給するためにはマイクロ波伝送線路が用いられる。   The Josephson voltage standard chip is mounted on a chip carrier and supplied with microwaves through a coaxial cable. A microwave transmission line is used to supply microwaves to a Josephson junction on a chip made of silicon or the like.

マイクロ波伝送線路としては、準平面型導波路（Coplanar Waveguide：ＣＰＷ）が利用されてきた。ＣＰＷは、信号配線が接地導体にはさまれた構造になっており、誘電体の一面のみを使って信号伝送ができるため、回路の特性評価や他の回路との接続が容易である。基板とチップ上に作製された準平面型導波路同士の接続には、一般にアルミ線またはアルミリボンのボンディングが用いられる（下記特許文献参照）。
特開２００５−２２３４６８号公報 As a microwave transmission line, a quasi-planar waveguide (CPW) has been used. CPW has a structure in which signal wiring is sandwiched between ground conductors, and can transmit signals using only one surface of a dielectric, so that it is easy to evaluate circuit characteristics and connect to other circuits. In general, bonding of an aluminum wire or an aluminum ribbon is used to connect the quasi-planar waveguides formed on the substrate and the chip (see the following patent document).
JP 2005-223468 A

電圧標準用チップは、取り扱いを容易にするために、チップキャリア上に実装される。チップキャリアは、バイアス電流を供給するための配線やマイクロ波を電圧標準用チップに供給するための準平面型導波路がガラスエポキシ樹脂やテフロン（登録商標）系樹脂などの誘電体の表面に銅薄膜などで構成されたプリント基板と、そのプリント基板にマイクロ波を供給するために半田付けされた同軸ケーブルから構成される。   The voltage standard chip is mounted on a chip carrier for easy handling. In the chip carrier, a wiring for supplying a bias current and a quasi-planar waveguide for supplying a microwave to a voltage standard chip have copper on the surface of a dielectric such as glass epoxy resin or Teflon (registered trademark) resin. The printed circuit board is composed of a thin film and the like, and a coaxial cable soldered to supply microwaves to the printed circuit board.

図１に、従来の接続方法を示す。図１において、プリント基板４とチップ５の準平面型導波路はアルミ線ボンディングやアルミリボンボンディングなどの手法により接続される。通常は、中心導体同士を接続するリボン状金属線１の両側に並行に、リボン状金属線２および３が外部導体同士を接続する。   FIG. 1 shows a conventional connection method. In FIG. 1, the quasi-planar waveguides of the printed circuit board 4 and the chip 5 are connected by a technique such as aluminum wire bonding or aluminum ribbon bonding. Usually, the ribbon-like metal wires 2 and 3 connect the outer conductors in parallel to both sides of the ribbon-like metal wire 1 that connects the central conductors.

図２に、図１の接続方法における等価回路を示す。該回路に示すように、ＣＰＷの特性インピーダンスZ0は、信号配線のインダクタンスＬと接地導体との静電容量ＣからZ0＝√（L/C）で与えられる。 FIG. 2 shows an equivalent circuit in the connection method of FIG. As shown in the circuit, the CPW characteristic impedance Z 0 is given by Z 0 = √ (L / C) from the capacitance L between the inductance L of the signal wiring and the ground conductor.

ところが、プリント基板の材料４およびチップの材料５は、ガラスエポキシ樹脂やシリコンなどの比誘電率が３〜１１程度の材料であるのに対して、ボンディングされた基板間の金属線は比誘電率が１の空気中に存在するため、金属線１と金属線２および３間の静電容量がどうしても小さくなってしまう。その結果、基板４上の準平面型導波路の特性インピーダンスとチップ５上の準平面型導波路の特性インピーダンスに対して、金属線１、２、３で構成される部分の特性インピーダンスは非常に大きくなる。こうして生じたインピーダンスミスマッチにより高周波信号はそこで反射してしまうという問題点があった。   However, the printed board material 4 and the chip material 5 are materials having a relative dielectric constant of about 3 to 11 such as glass epoxy resin and silicon, whereas the metal wire between the bonded substrates is a relative dielectric constant. Exists in the air of 1, the capacitance between the metal wire 1 and the metal wires 2 and 3 is inevitably reduced. As a result, the characteristic impedance of the portion composed of the metal wires 1, 2, and 3 is very high with respect to the characteristic impedance of the quasi-planar waveguide on the substrate 4 and the characteristic impedance of the quasi-planar waveguide on the chip 5. growing. There is a problem that the high frequency signal is reflected there due to the impedance mismatch.

図３に見られるように、金属線１の上を金属線２および金属線３がわずかの空間を空けて上から見て重なるように交差させることによって静電容量を稼ぎ、インピーダンスの上昇を最小限に抑えることによってインピーダンスミスマッチによるリターンロスを減らすことが期待できる。   As shown in FIG. 3, the capacitance is increased by intersecting the metal wire 1 and the metal wire 3 so that the metal wire 2 and the metal wire 3 overlap each other when viewed from above with a small space, and the increase in impedance is minimized. By limiting to the limit, it can be expected to reduce return loss due to impedance mismatch.

金属線１、２、３で構成される部分の特性インピーダンスの過剰な増加を防止し、インピーダンスミスマッチもさほど大きくならず、高周波信号がそこで反射することも抑制することができる。   It is possible to prevent an excessive increase in the characteristic impedance of the portion constituted by the metal wires 1, 2, and 3, and the impedance mismatch does not increase so much, and the high-frequency signal can be prevented from being reflected there.

以下に、図面を用いて本願発明を詳細に説明する。   Below, this invention is demonstrated in detail using drawing.

基板間の大きなインピーダンスを減らしてインピーダンスミスマッチを減らすためには、金属線１のインダクタンスＬを小さくするか、金属線１と金属線２および３の間の静電容量Ｃを大きくする必要がある。インダクタンスＬを小さくするためには、細いアルミ線ではなく、幅の大きいアルミリボンを用いることが行われている。   In order to reduce impedance mismatch by reducing a large impedance between the substrates, it is necessary to reduce the inductance L of the metal wire 1 or increase the capacitance C between the metal wire 1 and the metal wires 2 and 3. In order to reduce the inductance L, an aluminum ribbon having a large width is used instead of a thin aluminum wire.

静電容量Ｃを大きくするには金属線１と金属線２および３の間の静電容量を大きくする必要がある。そのためには金属線1と金属線２および、金属線１と金属線３の距離を小さくすれば良いが、並行に接続した場合は限界があり、期待するほど静電容量を得ることは困難である。   In order to increase the capacitance C, it is necessary to increase the capacitance between the metal wire 1 and the metal wires 2 and 3. For that purpose, the distance between the metal wire 1 and the metal wire 2 and between the metal wire 1 and the metal wire 3 can be reduced, but there is a limit when connected in parallel, and it is difficult to obtain the capacitance as expected. is there.

そこで図３に示すように、金属線１の上を金属線６および金属線７が接触しない範囲で可能な限りわずかの空間を空けて上から見て重なるように交差させることによって静電容量を稼ぎ、インピーダンスの上昇を最小限に抑えることによってインピーダンスミスマッチによるリターンロスを減らすことが期待できる。   Therefore, as shown in FIG. 3, the capacitance is obtained by intersecting the metal wire 1 so as to overlap as viewed from above with as little space as possible as long as the metal wire 6 and the metal wire 7 do not contact each other. Earning and minimizing the rise in impedance can be expected to reduce return loss due to impedance mismatch.

あるいは図４に示すように、従来の並行にアルミリボンをボンディングした上に、さらに、金属線２の基板側から金属線３のチップ側に金属線６を、金属線３の基板側から金属線２のチップ側に金属線７をわずかの空間を空けて上から見て重なるように交差させることによってさらに特性インピーダンスを下げることが期待できる。   Alternatively, as shown in FIG. 4, the aluminum ribbon is bonded in parallel with the conventional method, and the metal wire 6 is further connected from the substrate side of the metal wire 2 to the chip side of the metal wire 3. It is expected that the characteristic impedance can be further lowered by crossing the metal wires 7 on the chip 2 side so as to overlap each other when viewed from above with a small space.

図５に、図４に示した実施例の顕微鏡写真を示す。   FIG. 5 shows a photomicrograph of the example shown in FIG.

図６に、実際にネットワークアナライザで測定した透過係数S21を示す。横軸は周波数(GHz)である。細線が従来の平行線の透過係数であり、太線が図５に示したクロス状に交差した場合の透過係数である。透過係数S21の値は、ケーブルの損失や、同軸とチップキャリアの半田付け部分のリターンロスなども含んでいるので、絶対値そのものにはあまり意味が無いが、細線で示した従来の方法と、太線で示した本発明の方法で、これらの損失やリターンロスはほぼ同一であるため、両者の差が意味を持ち、本発明の効果によって、周波数16GHzのマイクロ波に対して約2dB透過係数が改善されていることがわかる。 Figure 6 shows the transmission coefficient S 21 measured actually with a network analyzer. The horizontal axis is frequency (GHz). The thin line is the transmission coefficient of the conventional parallel line, and the thick line is the transmission coefficient when intersecting in the cross shape shown in FIG. The value of the transmission coefficient S 21 is lost and the cable, since it contains well as return loss of soldered portions of the coaxial and the chip carrier, although much sense is not the absolute value itself, the conventional method shown by the thin line In the method of the present invention indicated by the bold line, since these losses and return losses are almost the same, the difference between them is significant, and due to the effect of the present invention, the transmission coefficient is about 2 dB for a microwave of frequency 16 GHz. It can be seen that is improved.

従来の接続方法Conventional connection method 従来の接続方法の等価回路Equivalent circuit of conventional connection method 本発明の接続方法Connection method of the present invention 従来の接続方法と本発明の両方を組み合わせた接続方法Connection method combining both the conventional connection method and the present invention 本発明の実施例の顕微鏡写真Micrograph of an embodiment of the present invention 従来および本発明（図５）の接続方法をネットワークアナライザで測定した透過係数Transmission coefficient measured with a network analyzer for the connection method of the prior art and the present invention (FIG. 5)

符号の説明Explanation of symbols

１：信号配線
２：接地導体
３：接地導体
４：誘電体
５：誘電体
６：接地導体
７：接地導体
1: Signal wiring 2: Ground conductor 3: Ground conductor 4: Dielectric 5: Dielectric 6: Ground conductor 7: Ground conductor

Claims (2)

高周波信号を伝達するための２つの基板間の接続方法であって、２つの基板上の準平面型導波路の中心導体同士を接続する第１のリボン状金属線の上をわずかな距離をあけて２つの基板上の準平面型導波路の中心導体の両側に配置された外部導体同士を交差するように接続した第２及び第３のリボン状金属線からなる構造を特徴とする基板間の接続方法。   A connection method between two substrates for transmitting a high-frequency signal, wherein a slight distance is formed on a first ribbon-like metal line connecting the central conductors of quasi-planar waveguides on the two substrates. Between the substrates characterized by a structure comprising second and third ribbon-like metal wires connected so that the outer conductors arranged on both sides of the central conductor of the quasi-planar waveguide on the two substrates intersect each other Connection method. 上記基板は、ジョセフソン電圧標準用チップ及びプリント基板であることを特徴とする請求項１記載の基板間の接続方法。
2. The method for connecting between substrates according to claim 1, wherein the substrate is a Josephson voltage standard chip and a printed circuit board.
JP2006140644A 2006-05-19 2006-05-19 Connection method between boards Expired - Fee Related JP4521534B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009170777A (en) * 2008-01-18 2009-07-30 National Institute Of Advanced Industrial & Technology Programmable josephson voltage standard apparatus
JP2019169504A (en) * 2018-03-22 2019-10-03 日本電信電話株式会社 Wire bonding structure
JP7242613B2 (en) * 2020-07-30 2023-03-20 アンリツ株式会社 Inter-board connection structure and inter-board connection method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11346106A (en) * 1998-05-29 1999-12-14 Nec Corp Microstrip line connecting method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11346106A (en) * 1998-05-29 1999-12-14 Nec Corp Microstrip line connecting method

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