JP4519151B2 - Cache control circuit - Google Patents

Description

  The present invention generally relates to a memory control circuit, and more particularly to a cache control circuit that controls a cache memory.

  In general, in a computer system, a small-capacity and high-speed cache memory is provided separately from the main memory. A part of the information stored in the main memory is copied to the cache, and when this information is accessed, the information is read from the cache instead of the main memory, thereby enabling high-speed information reading.

  A processor used in the field of communication or the like is required to have a trade-off condition of high processing performance and low power consumption that satisfy the requirements of the communication method. There is a close relationship between the processing performance of the processor and the hit rate of the cache, and the higher the hit rate, the better the processor can exhibit its original performance. A hit is when the current access is applied to the access history to the external memory stored in the cache, that is, when the access target data is stored in the cache. Conversely, when the current access does not apply to the access history, it is called a cache miss. In this case, a new history is stored, but when there is no capacity for storing a new history, the history needs to be overwritten and updated.

  Generally, out of all bits of the address, a predetermined number of lower bits serve as a cache index, and the remaining bits positioned higher than that serve as a cache tag (history). When accessing data, a tag (history) of the corresponding index in the cache is read using the index portion in the address indicating the access destination. It is determined whether or not the read tag matches the bit pattern of the tag portion in the address. If they do not match, a cache miss occurs. If they match, a cache hit occurs, and the cache data corresponding to the index (data of a predetermined number of bits for one cache line) is accessed.

  A cache configuration in which only one tag is provided for each cache line is called a direct mapping method. A cache configuration in which N tags are provided for each cache line is called an N-way set associative. In the N-way cache, N data can be stored in one cache line.

  The larger the cache size, the higher the hit rate. However, since the cache operates at high speed near the core, there is a problem that the power consumption increases when the cache size is increased. It is known that the ratio of the power consumption of the cache to the power consumption of the entire processor is high.

  Generally, the required cache capacity varies depending on the state of the application. Therefore, there is a technique for controlling the cache capacity and power consumption by changing the number of drive ways by providing a mechanism that can control the start and stop of the cache in units of ways (Patent Document 1). In this technique, the cache miss hit rate is always measured, and when the miss hit rate becomes high, the way is started, and when the miss hit rate becomes low, the way is sequentially stopped. As a result, by dynamically minimizing the cache size to the minimum necessary, power consumption is reduced while preventing performance degradation.

However, if the measurement item is only the miss-hit rate, there is a problem as described below. For example, if the current cache size (current number of drive ways) is optimal for the current application state and the hit ratio is high, the measured miss-hit ratio remains low, so the way is stopped. Is determined to be appropriate and one way is stopped. However, if one way is stopped, the current cache size (current number of drive ways) is not sufficient, and the measured miss-hit rate is high. As a result, it is determined that it is appropriate to activate the way, and one way is activated. In this way, the way is stopped and started repeatedly, and the performance deteriorates. This phenomenon is considered to be caused by determining whether the current number of ways is right or wrong based only on the miss hit rate, and ignoring information on how much the cache is used (filling level and usage rate).
Japanese Patent Laid-Open No. 9-50401

  In view of the above, an object of the present invention is to provide a cache control circuit capable of controlling the cache capacity to an appropriate size for the current application state.

  A cache control circuit for controlling a set associative cache memory including a plurality of ways has a data occupancy ratio according to a ratio of valid data in the plurality of ways of the cache memory, and the cache memory is accessed. A measurement unit that obtains a usage rate according to the frequency and a miss rate according to the miss rate of access to the cache memory, the data occupation rate, the usage rate, and the miss rate according to the miss rate. A control unit that controls activation and deactivation of the plurality of ways of the cache memory is included.

  According to at least one embodiment of the present invention, not only the miss rate, but also the data occupation rate according to the proportion of valid data in a plurality of ways and the usage rate according to the frequency at which the cache memory is accessed, Considering the above, it becomes possible to perform start control and stop control for each way in accordance with the current application state. As a result, the cache capacity can be controlled to an appropriate size for the current application state.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a cache device according to the present invention.

  1 includes a tag storage unit 11, a data register unit 12, a determination unit 13, a controller 14, an address conversion unit 15, and a selector 16. For example, if the logical address is 32 bits long, the least significant 4 bits of the address become the address offset, a predetermined number of bits positioned higher than that become the cache index, and the remaining bits positioned higher than that Becomes the tag of the cache.

  When accessing data, the index part (7 bits from the 7th bit (6) to the 13th bit (12) of the logical address) in the address indicating the access destination is used to correspond to the corresponding index in the tag storage unit 11. Read the tag. At this time, the tag may be read as valid data only when the valid bit V of the index in the tag storage unit 11 is a valid value 1. In parallel with the reading of the tag, the upper bits (logical address [31:13]: the 14th bit (13) to the 32nd bit (31) of the logical address) of the address indicating the access destination are physically Convert to address [31:13].

  The tag read out from the tag storage unit 11 in this manner and the physical address [31:13] output from the address conversion unit 15 are compared by the comparator 13a of the determination unit 13, and whether or not the bit patterns match. Judging. The comparison operation is executed for four tags of four ways, and when the comparison result indicates coincidence for one of them, the output of the corresponding determination unit 13 is asserted. When the access is hit, any output of the determination unit 13 is asserted. When the access is miss, any output of the determination unit 13 is not asserted.

  Of the four way data read from the data register unit 12 according to the logical address of the access destination, the way data corresponding to the assert output of the determination unit 13 is supplied to the selector 16. The selector 16 selects the word indicated by the offset portion in the logical address of the access destination and sets it as read data from the cache.

  The controller 14 executes various control operations related to cache management. For example, a valid bit V can be set, a tag can be set, an available cache line can be searched by checking a valid bit, and a replacement target can be determined based on, for example, an LRU (least recently used) algorithm. Or a data write operation to the data register unit 12 is controlled. The controller 14 also executes cache start / stop control according to the present invention. The block configuration of the controller 14 shown in FIG. 1 corresponds to the part related to the cache start / stop control.

  The controller 14 includes a power control unit 21, a dynamic threshold control unit 22, a way number control unit 23, a comparison unit 24, a miss rate measurement unit 25, a usage rate measurement unit 26, a cache state measurement unit 27, and a setting register 28. . The cache state measurement unit 27 monitors the following two states as needed and holds them as a usage rate table.

  The first state to be monitored is the degree of filling for each cache line. For example, if three cache ways are activated and valid data is stored in all three ways on a line, the line is filled with 1, and the valid of these three ways is valid. If there is even one way that does not contain data, the degree of filling of this line is zero. As described above, when valid data is inserted in all active ways for each line, the degree of filling of the line is 1, and when there is a way without any valid data, the degree of filling of the line is 0. It is defined as As shown in FIG. 2, the usage rate table 31 shows the active way, and 1 is recorded as a flag in the way containing valid data. By taking the AND of the flag of the way being activated, the data 1/0 of the filling state is obtained.

  The first status to be monitored is the usage rate for each cache line. Here, the usage rate is obtained as follows. For each cache access, the number (line number) of the accessed cache line is stored in the FIFO 32 shown in FIG. The usage rate of the line of the line number newly stored in the FIFO 32 is increased by 1 in the usage rate table 31. Further, the usage rate of the line of the line number output from the FIFO 32 is decreased by 1 in the usage rate table 31. If the length of the FIFO 32 is N + 1 and m of the past N + 1 cache accesses are accesses to the line k, the usage rate of the line k in the usage rate table 31 is m.

  The miss rate measurement unit 25 generates a numerical value that is 0 if hit for each cache access and 1 if it is a miss. If the degree of filling of the accessed line is 1, a coefficient C greater than a preset value C is set to 1. Multiply the value and store the result in the FIFO 32 (see FIG. 2). The total value of the data stored in the FIFO 32 is output from the miss rate measuring unit 25 as a measured value (miss rate) for the way activation determination criterion. The miss rate, which is an output measurement value, increases as the number of misses in the past predetermined number of accesses increases, and increases as the accessed line in the case of a miss has no free space. This output measurement value is used as a criterion for way activation. By obtaining the product of the coefficient C, the activation detection is twice as fast as the coefficient set value than the conventional one.

The usage rate measuring unit 26 calculates a measurement value for determining whether or not it is appropriate to stop the way from the degree of cache filling and the usage frequency. As shown in FIG. 3, when the cache is in a missing state, it is possible to obtain a power reduction effect without significantly affecting the hit rate even if the way is stopped and the use location is closed. . For example, with respect to line 0 in which the degree of filling is 1 (that is, there is no vacancy), the usage rate is relatively small, so it is considered that there is little influence even if the ways are reduced. Specifically, i is the sum of i, where i is a line number. Σ {embedding _i × usage _i } (Expression 1)
If the value of is small, it is considered reasonable to reduce the way. The usage rate measurement unit 26 outputs the value obtained as described above as the total usage rate. The comparison unit 24 calculates the error rate from the error rate measurement unit 25 and the total usage rate from the usage rate measurement unit 26, respectively. Compare with the threshold value. These threshold values are values determined in advance by simulation or the like, and are values that can be variably set by register settings, for example. When the error rate exceeds the threshold value, the comparison unit 24 issues an activation instruction to the way number control unit 23. When the total usage rate becomes equal to or less than the threshold value when the error rate does not exceed the threshold value, the comparison unit 24 issues a stop instruction to the way number control unit 23. When neither condition is satisfied, the comparison unit 24 does not give any instruction of starting and stopping.

  FIG. 4 is a diagram illustrating an example of the configuration of the way number control unit 23.

  The way number control unit 23 controls the number of ways based on the activation / stop instruction from the comparison unit 24 and the activation state of the current way. A way usage count measurement unit 35 is provided inside, and the usage status of each way at a predetermined number of accesses is stored as a table. In addition, a way activation state is stored as a way activation state table 36. The activation determination is performed by the control determination unit 39 when there is an activation instruction from the comparison unit 24, there is a way that is stopped, and the timer is not waiting. When the activation determination is made, the control determination unit 39 updates the activation status and sends the activation status to the power control unit 21 together with the activation instruction. The timer wait state is the time from the last activation until the way power is stabilized, and the time required for storing the history in the cache when the first access immediately after the way activation is missed (α register 37 ) (The time indicated by the stored value). This time is determined in advance by simulation or the like, and the register 37 can be variably set. It has a timer 38 that is activated together with the activation determination and measures the waiting time.

  The stop determination by the way number control unit 23 is performed by the control determination unit 39 when there is no activation instruction, there is no timer waiting, there is a stop instruction, and two or more ways are activated. When the stop determination is made, the control determination unit 39 stops the way number having the lowest usage rate based on the measured usage rate for each way, updates the way activation status, and sets the activation status as a stop instruction. Together, it is sent to the power controller 21.

  The power control unit 21 controls the power on / off of each way according to an instruction from the way number control unit 23.

  The threshold value may be dynamically variably controlled. It is assumed that the set value of the threshold value is a reasonable value measured in advance by simulation or the like. However, when an appropriate simulation cannot be performed, etc., there is no choice but to set an appropriate guess value. As a result, there is a case where the way start / stop operation does not occur at all. Even in such a case, the threshold value can be changed by register setting. However, the dynamic threshold value control unit 22 may be provided as an auxiliary function in the case where it is desired to change the threshold value automatically without relying on human hands or to change it faster.

  FIG. 5 is a diagram illustrating an example of the configuration of the dynamic threshold value control unit 22. When the dynamic control is turned on, the timer 40 starts. The counter 41 counts the number of activation instructions. In the case of start threshold control, the selector 42 selects a value that is “+1” to the previous value (FF value) if the count value of the counter 41 exceeds the threshold at the end of the timer. When the count value of the counter 41 is 0, a value obtained by subtracting “−1” from the previous value (FF value) is selected. If the count value of the counter 41 is not equal to or greater than the threshold value and not 0, the previous value (FF value) is selected. The timer 40 and the counter 41 are reset when the timer ends. The control operation for the stop threshold is the same. However, the number of stop instructions is monitored instead of the number of activation instructions, and the opposite is the case when the threshold “±” is the activation threshold.

  FIG. 6 is a flowchart showing the flow of cache start / stop control according to the present invention. The processing shown in this flowchart is performed for each cache access.

  In the measurement value update phase (S1), each measurement value is calculated. This corresponds to the operation of the cache state measuring unit 27 in FIG.

  In the activation condition measurement phase (S2), the miss rate is calculated based on the measured value to determine the presence or absence of activation. This corresponds to the operation of the activation-related portion of the error rate measurement unit 25 and the comparison unit 24 in FIG.

  In the stop condition determination phase (S3), the total usage rate is calculated based on the measured value, and the result is compared with a threshold value to determine stop. This corresponds to the operation of the stop-related portion of the usage rate measurement unit 26 and the comparison unit 24 in FIG.

  In the start / stop phase (S4), the start / stop determination of the way is performed. This corresponds to the operation of the way number control unit 23 in FIG.

  In the dynamic threshold control phase (S5), each threshold is dynamically controlled. This corresponds to the operation of the dynamic threshold control unit 22 in FIG. This process only operates in synchronization with the clock cycle counted by the timer, not the cache access cycle. Note that the dynamic threshold control phase may be executed at the head of the procedure shown in FIG. 6, and the processing of each step shown in FIG. 6 may be executed using the threshold after control. The dynamic threshold control function may be controlled to be turned on / off by register setting or the like.

  In the power control start (S6) and the power control stop (S7), the way activation and the least frequently used way stop operation are performed, respectively. This corresponds to the operation of the power control unit 21 in FIG. Thereafter, the process is terminated and the next cache access is awaited.

  FIG. 7 is a flowchart showing a procedure for calculating each measurement value corresponding to S1 of FIG. The order of each step is random. In the padding state update (S1), the result of ANDing is held as a table when the valid data exists for each line of the activation way, and when there is no valid data, it is 0. In the usage rate update (S2), the number of used lines corresponding to the oldest access line number held is reduced by 1, and the number of used line numbers accessed this time is increased by 1. In the usage number update for each way (S3), the way usage number indicated by the oldest access information is reduced by 1, and the usage number of the way accessed this time is incremented by "+1".

  FIG. 8 is a flowchart showing a procedure for determining the activation condition corresponding to S2 of FIG.

  First, the oldest hit or miss information is deleted (S1). The hit / miss of the current access is determined (S2), and if it is a hit, the measured value (miss rate) is set to ± 0 (S3). If the missed line is missed in S2 and the filling level of the missed line is 1 (YES in S4), the measured value is incremented by + C (S5). If the missed line is missed in S2 and the filling level of the missed line is 0 (NO in S4), the measured value is incremented by 1 (S6). The measured value is compared with the threshold value (S7), and if the threshold value is exceeded, it is determined that the activation condition is satisfied, and the process proceeds to the activation stop phase (S8). If the threshold is not exceeded, the process proceeds to the stop condition determination phase (S9).

  FIG. 9 is a flowchart showing a stop condition determination procedure corresponding to S3 of FIG.

  The total usage rate is calculated according to a predetermined formula (S1). If the total usage rate is equal to or greater than the threshold (YES in S2), the process proceeds to the start / stop phase (S3). If the total usage rate is smaller than the threshold (NO in S2), the process is terminated and the next cache access is awaited (S4).

  FIG. 10 is a flowchart showing the procedure of the start / stop operation corresponding to S4 of FIG.

  If there is a start instruction (YES in S1), the timer for power stabilization + α waiting has ended (YES in S2), and if there is a stop way (YES in S3), a timer for power stabilization + α waiting is started ( S4), together with the way activation instruction, shifts to the dynamic threshold control phase (S5). Even if there is an activation instruction, if the timer waits for power stabilization + α (NO in S2) or if there is no stop way (NO in S3), the process proceeds to the dynamic threshold control phase without issuing an instruction (S6). If there is no start instruction (NO in S1), there is a stop instruction (YES in S7), and the number of operating ways is 2 or more (YES in S8), the process proceeds to the dynamic threshold control phase together with the stop instruction (S9). . If there is no stop instruction (NO in S7) or the number of operating ways is one (NO in S8), the process proceeds to the dynamic threshold control phase without issuing an instruction (S10).

  FIG. 11A is a flowchart showing a procedure of the dynamic threshold control operation corresponding to S5 of FIG. FIG. 11A shows a procedure for controlling the activation threshold.

  When the dynamic control setting is turned on (YES in S1), the change command value (a value that holds how many threshold values are changed) is reset, and the timer is started. While the timer is running, the start command is counted (S2, S3). When the timer ends (YES in S4), if the counter is equal to or greater than the threshold (YES in S5), it is determined that the threshold is too low, the change command value is incremented by "+1", and the counter is reset (S6). If the counter is not equal to or greater than the threshold (NO in S5) and 0 (YES in S7), it is determined that the threshold is too high and the change command value is decremented by 1 (S8). If it is neither, the change command value is left as it is. The timer is reset and restarted, and the change command value and the change width are multiplied and added to the threshold value and used in the comparison unit (S9).

  FIG. 11B is a flowchart showing the procedure of the dynamic threshold control operation corresponding to S5 of FIG. FIG. 11B shows a procedure for controlling the stop threshold.

  While the timer is running, the stop command is counted (S1, S2). When the timer ends (YES in S3), if the counter is equal to or greater than the threshold (YES in S4), it is determined that the threshold is too high, the change command value is decremented by 1, and the counter is reset (S5). If the counter is not equal to or greater than the threshold (NO in S4) and 0 (YES in S6), it is determined that the threshold is too low, and the change command value is incremented by 1 (S7). If it is neither, the change command value is left as it is. The timer is reset and restarted, and the change command value and the change width are multiplied and added to the threshold value and used in the comparison unit (S8).

  FIG. 12 is a diagram illustrating an example of the configuration of the cache state measurement unit 27.

  Based on the activation way information, the valid data flag of the stop way is masked and the valid data flag of the activation way is left as it is, and the AND of the valid data flags of a plurality of ways is taken for each line, and the result is filled up. To store. In the usage rate table 52, the line number selected for each cache access is stored in the FIFO 53, the input number A and the output number B are compared, and if the situation does not apply to both, the usage rate is ± 0. The updated value is held as +1 if applicable to -1, -1 if applicable to output, or ± 0 if applicable to both. The way usage rate includes a FIFO 54 for each way, and 1 is input for access to its own way for each cache access, and 0 is stored otherwise, and the total of the FIFOs 54 is held as the number of uses.

  FIG. 13 is a diagram illustrating an example of the configuration of the miss rate measurement unit 25. When the cache access is hit, 0 is inserted into the FIFO 55, and when the missed and missed line is filled with a coefficient C, the coefficient C is inserted. When the missed and missed line is filled with 0, 1 is inserted into the FIFO 55. The total sum of the values of each register of the FIFO 55 is taken as a measurement value (miss rate).

  In addition, by setting the coefficient C of the miss rate measurement to 1 or deleting the selection mechanism itself of C or 1, a simple hit / miss rate that does not consider the degree of filling is used as a criterion (miss rate). You may do it. Even in this case, the cache control different from the conventional one can be performed by using the stop control method of the present application. When it is not desired to drop the performance (hit rate) below a certain value, it is effective to change the threshold value for measuring the miss rate.

  FIG. 14 is a diagram illustrating an example of the configuration of the usage rate measurement unit 26. A plurality of multipliers 56 and adders 57 obtain a product sum of the degree of filling for each line and the usage rate from the usage rate table and output it as a measured value (total usage rate).

  FIG. 15 is a diagram illustrating an example of the configuration of the comparison unit 24. The comparison unit 24 includes adders 61 and 62 and comparison circuits 63 and 64. The adder and the comparison circuit compare the measured value and the threshold value for each of starting and stopping. When the threshold is exceeded, a start or stop instruction is issued. The threshold value is a value obtained by adding the change value of the threshold value from the dynamic threshold value control unit 22 to the register setting value. When the dynamic threshold value control unit 22 is not provided, the register setting value may be used as the threshold value as it is.

  FIG. 16 is a diagram illustrating an example of the configuration of the power control unit 21. The power control unit 21 includes an instruction detection circuit 71, an operation state register 72, and a plurality of AND circuits 73. The instruction detection circuit 71 detects a start / stop instruction signal supplied from the way number control unit 23 and outputs a capture trigger signal. In response to this capture trigger signal, the operation state register 72 captures the updated way operation state information supplied from the way number control unit 23. As a result, the internal way operation state information is updated. By controlling the AND circuit 73 according to the update result and masking each power supply line, the power supply of each way is controlled on / off.

  FIG. 17 is a block diagram showing a modification of the cache device according to the present invention. In FIG. 17, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted.

  The cache device of FIG. 17 differs from the cache device of FIG. 1 in that a controller 14A is provided instead of the controller 14. The controller 14A includes a power control unit 21, a way number control unit 23A, a cache state measurement unit 27A, and a setting register 28A.

  In this configuration, the degree of filling is seen not for each line but for the entire active way. That is, the total number of data valid flags in the entire active way is filled. Also, a FIFO that operates in units of core clocks, not cache access units, is provided so that 1 is input to the FIFO when there is cache access and 0 is input when there is no cache access. The total (number of 1) of the data stored in the FIFO is used. With such a configuration, the structure of the holding register and the calculation circuit is simple and small.

  FIG. 18 is a diagram illustrating an example of the configuration of the cache state measurement unit 27A. In FIG. 18, the same elements as those of FIG. 12 are referred to by the same numerals, and a description thereof will be omitted.

  In the case of the configuration of FIG. 18, based on the activation way information, the effective data flag of the stop way is masked and the effective data flag of the activation way is left as it is, and the sum of all the effective data flags is obtained, and the result is used. It is stored in Table 81 as the degree of filling. In this case, since the degree of filling in line units is not known, the coefficient C cannot be applied to the miss rate. Miss rate uses cache miss rate as it is. The usage rate of the cache is obtained by the FIFO 82, and the result is stored in the usage rate table 81.

  FIG. 19 is a table showing a correspondence relationship between the value of the degree of filling, the usage rate, the error rate, and the control operation. Based on the table of FIG. 19, the operations in the column of operations (way activation, as it is, as it is stopped) may be executed. Specifically, when the error rate is low and at least one of the degree of filling and the usage rate is low, it is determined that the way is stopped. Further, when the error rate is high and at least one of the degree of filling and the usage rate is high, it is determined that the way is activated. In other cases, the way is not started or stopped.

  FIG. 20 is a diagram illustrating an example of the configuration of the way number control unit 23A. The way number control unit 23A includes comparators 85 to 87, a determination unit 88, and a way activation state table 89. The comparators 85 to 87 respectively compare the filling level, the usage rate, and the miss rate with the register setting threshold values. The determination unit 88 makes a determination according to the comparison result and the current way activation state indicated by the way activation state table 89, and outputs an activation instruction, a stop instruction, and a way operation status. The determination conditions are the conditions described in the determination unit 88 in FIG. 20, and correspond to the table in FIG.

  FIG. 21 is a block diagram showing a further modification of the cache device according to the present invention. In FIG. 21, the same components as those in FIGS. 1 and 17 are referred to by the same numerals, and a description thereof will be omitted.

  The cache device of FIG. 21 differs from the cache device of FIG. 17 in that a controller 14B is provided instead of the controller 14. The controller 14B includes a power control unit 21, a dynamic threshold control unit 22, a way number control unit 23B, a cache state measurement unit 27A, and a setting register 28A. By providing the dynamic threshold control unit 22, the same dynamic threshold control as in the configuration of FIG. 1 can be performed.

  FIG. 22 is a diagram illustrating an example of the configuration of the way number control unit 23B. In FIG. 22, the same components as those of FIG. 20 are referred to by the same numerals, and a description thereof will be omitted.

  The way number control unit 23B further includes adders 91 to 93 in addition to the configuration of FIG. The adders 91 to 93 add the threshold increase value from the dynamic threshold control unit 22 to the register setting threshold, and generate a dynamically changing threshold. This dynamically changing threshold is used for the comparison operation in the comparators 85-87.

  FIG. 23 is a flowchart showing the flow of cache start / stop control in the configuration shown in FIG. The processing shown in this flowchart is performed for each cache access.

  In the measurement value update phase (S1), each measurement value is calculated. This corresponds to the operation of the cache state measuring unit 27A of FIG.

  In the condition measurement phase (S2), it is determined whether or not there are start and stop conditions. The determination of activation and the determination of stop can be simplified by integrating them into the condition determination phase. In the start / stop phase (S3), the start / stop determination of the way is performed. This corresponds to the operation of the way number control unit 23A in FIG.

  In the power control start (S4) and the power control stop (S5), the way activation and the least frequently used way stop operation are performed, respectively. This corresponds to the operation of the power control unit 21 in FIG. Thereafter, the process is terminated and the next cache access is awaited.

  FIG. 24 is a flowchart showing the procedure for calculating each measured value corresponding to S1 in FIG. The degree of filling is calculated by obtaining the sum of the valid data flags of the cache valid ways (S1). The usage rate is obtained by deleting the oldest cache usage information and updating it by setting it to +1 if the cache is used and +0 if it is not used (S2). The way usage number update is the same as in FIG. Note that these steps may be performed in any order.

  FIG. 25 is a flowchart showing the procedure of the condition determination process corresponding to S2 in FIG. First, a threshold determination of a miss rate is performed (S1). If the error rate is greater than or equal to the threshold (YES in S1), the threshold determination for usage rate (S2) and the threshold determination for the degree of filling (S3) are performed. (S4, S5). When the miss rate is not equal to or greater than the threshold (NO in S1) and is equal to or less than the threshold (YES in S6), the threshold determination for the usage rate (S7) and the threshold determination for the degree of filling (S8) are performed. If it is determined that the following is true, it is determined to be stopped (S9, S10). In other cases, start and stop are not performed. Note that the order of determination of the usage rate and the degree of filling can be changed.

  FIG. 26 is a flowchart showing the flow of cache start / stop control in the configuration shown in FIG. The processing shown in this flowchart is performed for each cache access. 26 differs from the flowchart of FIG. 23 only in that a dynamic threshold control phase (SA) is added. Other processes are the same as those in FIG. The dynamic threshold control phase (SA) may be processed according to the procedure shown in FIGS. 11A and 11B.

  In the description of the above modification, the user may be able to change the setting of the relationship between the cache state and the operation shown in the table of FIG. That is, the contents of the operation column in the table of FIG. 19 may be variable by, for example, register setting. With the configuration using such register setting, for example, the operation defined as “stop” for the state 1 in FIG. 19 can be changed to “start” or “as it is”. The determination unit 88 shown in FIG. 20 or FIG. 22 may execute the determination result according to the register setting.

  FIG. 27 shows a flowchart of the condition determination phase when the operation contents can be set in the register. Threshold determination is performed with respect to the degree of filling, usage rate, and miss rate, and comparison with each threshold value is performed (S1). The setting contents of the register are read according to the comparison result (S2). High and low indicate values above and below the threshold value, and medium indicates a value that is not above and below the threshold value. The process branches to “start”, “stop”, or “as is” according to the result read from the register (S3).

  The effects of at least one embodiment of the present invention will be described below.

  The value shown in (Expression 1) is an expression that measures the cache usage efficiency as needed. As shown in the explanation of FIG. 3, when the value of this equation is low, the use rate of the buried line is low, and the vacancy of the line is large, that is, the upper body to be pinched is shown.

  For example, in the case of image processing such as JPEG, specific processing is repeatedly performed as shown in FIG. At this time, when looking at the instruction code area, a specific area in the memory space is repeatedly used because the specific process is repeated during the encoding process. Therefore, the cache has a high usage rate, a high degree of filling, and a high hit rate. During idle processing, usually simple processing such as branching to itself is repeated, so that only a specific memory area is used. Therefore, the usage rate of the cache is high, the degree of filling is low, and the hit rate is high. FIG. 29 shows the difference in effect between the present invention and the prior art (Patent Document 1) in this case.

  In the case of the prior art, the way is stopped when a state with a high hit rate continues because it depends only on the hit rate. Therefore, the cache capacity is insufficient and the miss rate is increased. For this reason, this time the system satisfies the start determination condition and starts up. Then, it returns to a state with a high hit rate again. Since this is repeated, the processing time is delayed. When entering the idle state, the way is stopped. Compared to the case without cache control, power consumption is reduced, but throughput is also reduced.

  On the other hand, in the case of the present invention, since the degree of burying for each line is also added to the judgment criterion, the way stop judgment is not made even in this case where the state of high hit rate continues. Therefore, the performance is maintained in the same manner as when there is no cache control. Since the usage rate is lowered in the idle state, the way is stopped, and the same power saving effect as in the prior art can be expected. That is, power can be saved without reducing the throughput as compared with the case without cache control.

  In FIG. 30, the error rate and the time change of activation determination are compared between the present invention and the prior art. In the present invention, since the coefficient C is multiplied, the measured error rate increases rapidly, so that the activation determination can be performed quickly.

  Furthermore, the comparison results are summarized quantitatively in FIG. As a result of faster start-up, the average performance is higher with the present invention. In addition, the detection is faster by an average C times than the conventional technique.

  The cache includes a plurality of cache lines, and copying of information from the main memory to the cache is executed in units of cache lines. The memory space of the main memory is divided in units of cache lines, and the divided memory areas are sequentially assigned to the cache lines. Since the capacity of the cache is smaller than the capacity of the main memory, the memory area of the main memory is repeatedly assigned to the same cache line.

  The cache decodes the address to store the access history. At that time, all bits of the normal address are not decoded. The cache is divided into lines, and a part of the address is assigned to the line number as it is. For this reason, the addresses that can be used for each line are periodically determined. Therefore, if the use frequency of the place where the same line is used is high, the number of lines increases and the hit rate increases (performance improvement) when the way is activated. Applying the coefficient C when the filling level is 1 in FIG. 2 is for emphasizing a case where a mistake is made by frequently using the same line. Therefore, improvement in startup detection efficiency can be expected.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a block diagram which shows an example of a structure of the cache apparatus by this invention. It is a figure for demonstrating a utilization rate, a filling condition, and a mistake rate. It is a figure for demonstrating the way stop based on a utilization rate table. It is a figure which shows an example of a structure of a way number control part. It is a figure which shows an example of a structure of a dynamic threshold value control part. It is a flowchart which shows the flow of the cache starting stop control by this invention. It is a flowchart which shows the procedure of calculation of each measured value. It is a flowchart which shows the procedure of starting condition determination. It is a flowchart which shows the procedure of stop condition determination. It is a flowchart which shows the procedure of start-stop operation | movement. It is a flowchart which shows the procedure of dynamic threshold value control operation | movement. It is a flowchart which shows the procedure of dynamic threshold value control operation | movement. It is a figure which shows an example of a structure of a cache state measurement part. It is a flowchart which shows the procedure of stop condition determination. It is a flowchart which shows the procedure of start-stop operation | movement. It is a figure which shows an example of a structure of a comparison part. It is a figure which shows an example of a structure of a power control part. It is a block diagram which shows the modification of the cache apparatus by this invention. It is a figure which shows an example of a structure of a cache state measurement part. It is a table | surface which shows the correspondence of the value of a filling condition, a usage rate, and a mistake rate, and control action. It is a figure which shows an example of a structure of a way number control part. It is a block diagram which shows the further modification of the cache apparatus by this invention. It is a figure which shows an example of a structure of a way number control part. It is a flowchart which shows the flow of the cache starting stop control in the structure shown in FIG. It is a flowchart which shows the procedure of calculation of each measured value. It is a flowchart which shows the procedure of a condition determination process. It is a flowchart which shows the flow of the cache starting stop control in the structure shown in FIG. The flowchart of the condition determination phase at the time of enabling operation setting of a register is shown. It is a figure which shows the example of the use condition of the cache in the case of image processing. It is a figure for demonstrating the difference of the effect of this invention and a prior art. It is the figure which compared the error rate and the time change of starting determination by this invention and the prior art. It is a figure which shows the effect of the present invention quantitatively.

Explanation of symbols

11 Tag storage unit 12 Data register unit 13 Determination unit 14 Controller 15 Address conversion unit 16 Selector 21 Power control unit 22 Dynamic threshold control unit 23 Way number control unit 24 Comparison unit 25 Miss rate measurement unit 26 Usage rate measurement unit 27 Cache state Measurement unit 28 setting register

Claims (5)

A cache control circuit for controlling a cache memory including a plurality of ways,
The data occupying ratio occupied by valid data among the plurality of ways of the cache memory, the usage ratio according to the frequency of accessing the cache memory, and the miss according to the ratio of miss of accessing the cache memory A measuring unit for determining the rate,
A cache control circuit comprising: a control unit that controls activation and deactivation of each of the plurality of ways of the cache memory according to the data occupying ratio, the usage rate, and the miss rate.   The control unit controls the way to start when the miss rate is equal to or higher than a predetermined threshold and any of the data occupation ratio and the usage rate is equal to or higher than the predetermined threshold. 2. The cache control circuit according to claim 1, wherein the control is performed so that the way is stopped when either of the data occupation ratio and the usage ratio is equal to or less than a predetermined threshold. The measurement unit is
The data occupation ratio corresponding to the ratio occupied by valid data among the plurality of ways is obtained for each cache line, and the usage ratio according to the frequency at which the target cache line is accessed in the past predetermined cache accesses For each cache line,
Among the predetermined number of cache accesses in the past, the weight of the frequency of missed cache access to the cache line whose data occupancy ratio indicates that there is free space, and the cache access to the cache line whose data occupancy ratio indicates that there is no space A miss rate measurement unit that calculates the miss rate as a miss frequency by differentiating the weight of the miss frequency,
A usage rate measuring unit for obtaining a total usage rate obtained by summing up the products of the data occupying ratio and the usage rate for each cache line for all the cache lines;
The control unit controls activation and stop of the cache memory for each of the plurality of ways according to a comparison result between the miss rate and a predetermined threshold and a comparison result between the total usage rate and a predetermined threshold. The cache control circuit according to claim 1. Weight of frequency of cache access of the data occupancy ratio to the cache line indicating the free-free misses is characterized in that the data occupancy ratio is greater than the weight of the frequency of missed cache access to the cache line indicating the free Yes The cache control circuit according to claim 3.   The cache control circuit according to claim 2, further comprising a dynamic threshold value control unit that dynamically controls the predetermined threshold value.

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