JP2008269365A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor capable of suppressing power consumption. <P>SOLUTION: The information processor comprises a load storage unit 227 which loads data from a main memory; an information processing core 103 which contains the load store unit 227 and performs predetermined processing in reference to the data loaded by the load store unit 227; a PLL which generates a clock signal of a frequency enabling operation of the information processor core 103 and supplies it to the information processing core 103; and a clock control logic circuit 233 which controls the supply and stop of the clock signal from the PLL to the information processing core 103. The clock control logic circuit 233 stops the supply of the clock signal from the PLL to a component circuit of the information processing core 103 other than the load store unit 227 over a part or the whole of the period where the load store unit 227 starts loading operation of data and acquires the data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a general information processing apparatus such as a microprocessor, and more particularly to an information processing apparatus with low power consumption.

  In a conventional CPU (Central Processing Unit), load delay is one of the major causes of performance degradation. Particularly in recent years, since the memory access speed has been sluggish compared to the improvement in the operating frequency of the processor, the problem for the improvement in performance has become more serious. Conventionally, the following measures have been widely put into practical use as a load delay avoidance measure.

(1) A memory or buffer for buffering access speed such as a cache is provided between a processor and a memory having a low access speed.
(2) When a large delay occurs such as loading from a DRAM (Dynamic Random Access Memory), the currently executing thread is switched to another thread. This can conceal the load delay. However, there is a problem that processing overhead occurs at the time of thread switching, and the circuit scale increases to implement the switching mechanism.
(3) When a small delay occurs as in the case of loading from a built-in SRAM (Static Random Access Memory), the order of instructions is changed for delay loading in which an independent instruction for the load instruction is packed in the load slot. However, when the load slot cannot be filled, there is a problem that the processing performance deteriorates.
(4) Although related to (3) above, the memory is prefetched by changing the processing procedure of the program. Data prefetching is possible when there is no data dependency between the data loaded by the load process and the subsequent process of the load.

  Among the above, the means (2) does not lead to a substantial improvement in the access speed, but can improve the throughput of the entire system. Each means may not be applicable depending on conditions, and its effectiveness is not always guaranteed.

  The memory is generally hierarchized according to capacity, access speed, cost, purpose of use, and the like. An SRAM mounted on a processor, an externally connected DRAM, a flash memory, a hard disk drive (HDD) other than a semiconductor, an optical disk drive, and other input / output (I / O) devices can be widely regarded as a memory. An access speed improvement technique suitable for the characteristics and hierarchy of the memory to be accessed is selected.

Alternatively, a direction that reduces power consumption is one option instead of a measure to eliminate load delay and increase effective performance. Examples include Patent Documents 1 to 4 below.
Japanese Patent Laid-Open No. 2002-189591 Japanese Patent Laid-Open No. 8-221411 JP-A-11-96105 Japanese National Patent Publication No. 05-506323

  However, according to the prior art, when conditions such as cache hits are met, the processing performance can be improved, but the effects of the prior art cannot be fully exerted depending on the situation, such as situations where cache misses occur frequently. There is a case. In this way, the purpose of the prior art is to improve performance on average, and the main focus is on maximizing the degree of effect when the condition of performance improvement × performance improvement condition is met. It was. In other words, since the conventional technology aims only at improving performance, it has been impossible to achieve both performance improvement and power consumption reduction.

  An object of the present invention is to provide an information processing apparatus capable of suppressing power consumption under conditions that cannot be relieved by the conventional technology while maintaining a performance compensation function associated with load delay that can be relieved by the prior art. This purpose differs from the effects and directions provided by the prior art.

  In order to achieve the above object, an information processing apparatus according to an aspect of the present invention executes a predetermined process with reference to data loading means for loading data from a main memory and data loaded by the data loading means. An information processing unit; a clock generating unit configured to generate a clock signal having a frequency at which the data loading unit and the information processing unit are operable; and to supply the data loading unit and the information processing unit; Clock control means for controlling supply and stop of the clock signal to the processing means, and the clock control means is a period from when the data loading means starts data loading until data is acquired. The clock signal from the clock generating means to the information processing means over a part or all of the period And wherein the stopping the supply.

  The information processing unit cannot execute the process until the data is acquired after the data loading unit starts the data loading operation. For this reason, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means during that time.

  Preferably, the main memory requires a predetermined time or more for loading data, the information processing apparatus further includes a sub-memory capable of loading data in the predetermined time or less, and data loaded by the data loading means Load source address space identification logic means for determining which address space of the main memory or the sub memory belongs to the address storing the address, and the clock control means includes the address of the main memory. If it is determined that the data belongs to the space, the clock generation unit performs the information processing over a part or all of the period from when the data load unit starts the data load operation until the data is acquired. The supply of the clock signal to the means is stopped.

  For example, when the main memory is a RAM and the sub memory is an SRAM, a load delay occurs when data is loaded from the RAM. Therefore, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means until the data loading of the RAM is completed.

  More preferably, the information processing apparatus further includes main memory control means for controlling reading of data from the main memory in response to a data load request from the data load means for the main memory, and the main memory And a data cache that temporarily holds a copy of data read from the main memory, and the data loading means loads data when loading data from the main memory. If the data to be stored is held in the data cache, the data is loaded from the data cache, and when the data loading means tries to load the data from the main memory, the data from the data cache When a miss access occurs during read access It said main memory control means may initiate the loading of data from said main memory, said clock control means is characterized by stopping the supply of the clock signal to the information processing means.

  When a cache miss occurs, data must be loaded from the main memory to the data cache, during which load delay occurs. Therefore, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means until the data is held in the data cache.

  More preferably, the clock control means is configured to store data read from the main memory in the data cache when the data load means tries to load data from the data cache and causes a miss-hit. The supply of the clock signal to the information processing means is resumed.

  When data is loaded into the data cache in this way, processing by the information processing means becomes possible. Therefore, the supply of the clock signal to the information processing can be resumed at this point.

  More preferably, the clock control means stops supply of a clock signal to a part or all of the constituent circuits of the information processing means when data is written back from the data cache to the main memory. To do.

  For example, data may need to be written back from the data cache to the main memory in order to maintain data consistency between the data cache and the main memory. In such a case, a load delay occurs until data is stored in the main memory. Therefore, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means during that time.

  More preferably, the information processing apparatus further includes a main memory control unit that controls reading of data from the main memory in response to a data load request from the data load unit to the main memory. The memory control means further includes a unique access to the main memory after the main memory control means makes a data read request to the main memory when the data load means loads data from the main memory. Predicting the time when the time elapses, outputting a clock stop release signal a predetermined time before the predicted time, the clock control means in response to the clock stop release signal output from the main memory control means, The supply of the clock signal to the information processing means is resumed. .

  In this way, the timing for restarting the supply of the clock signal can be determined by focusing on the access time unique to the main memory.

  More preferably, the information processing apparatus further includes a main memory control unit that controls reading of data from the main memory in response to a data load request from the data load unit to the main memory. The memory control means is further outputted from the main memory after the main memory control means makes a data read request to the main memory when the data loading means loads data from the main memory. Based on the output timing of the response signal, the data read completion time from the main memory is predicted, and a clock stop release signal is output a predetermined time before the predicted data read completion time. The clock stop release signal output from the memory control means. In response to, and wherein the resuming the supply of the clock signal to said information processing means.

  In this manner, by focusing on the output timing of the response signal output from the main memory, it is possible to determine the restart timing of the supply of the clock signal.

  More preferably, the information processing apparatus further includes a load buffer unit that temporarily holds data read from the main memory, and the clock control unit is configured such that the data load unit stores data from the main memory. When attempting to load, the supply of the clock signal is stopped for a part or all of the period from the start of the load operation until the data read from the main memory is stored in the load buffer means. It is characterized by.

  A load delay occurs when data is read from the main memory to the load buffer. For this reason, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means during that time.

  More preferably, the information processing apparatus further includes DMA (Direct Memory Access) control means for controlling data transfer from the main memory to the load buffer means, and the load buffer means receives the information from the main memory. It functions as an intermediate temporary buffer for holding data in a first-in first-out manner for data transfer to the processing means, and the clock control means is in a part or all of a period in which no data is stored in the load buffer means. Further, the supply of the clock signal to a part or all of the constituent circuits of the information processing means is stopped.

  If no data is stored in the load buffer used for DMA transfer, there is no data to be processed by the information processing means. For this reason, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means during that time.

  More preferably, the information processing apparatus further includes a main memory control unit that controls reading of data from the main memory in response to a data load request from the data load unit to the main memory, and an interrupt signal. In response, the main memory control means further comprises an interrupt control means for controlling the operation of the clock control means, and the main memory control means further includes a main memory control means when the data load means loads data from the main memory. Predicts the time at which the access time unique to the main memory elapses after making a data read request to the main memory, outputs a clock stop release signal a predetermined time before the predicted time, and The means accepts the clock stop cancellation signal as an interrupt signal, and Notify click control means, said clock control means is responsive to the notification, and wherein the resuming the supply of the clock signal to said information processing means.

In this way, the supply of the clock signal may be resumed by interrupt processing.
More preferably, the information processing apparatus further includes store buffer means for temporarily storing data to be stored in the main memory, and store means for storing data held by the store buffer means in the main storage device. When the store means tries to store the data held by the store buffer means in the main memory, the clock control means until the data is written to the main memory from the start of the store operation. The supply of the clock signal is stopped over part or all of the period.

  When data stored in the store buffer is written back to the main memory, a load delay occurs. For this reason, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means during that time.

  More preferably, the information processing means has a processing structure based on a pipeline type processing method, and the clock control means stops clock supply for the pipeline stage to which the process that stopped the clock supply belongs. In the next cycle, the clock supply to the circuit of the information processing means constituting the next stage of the pipeline stage is stopped.

  With such a configuration, for example, a clock signal to a component belonging to a stage where no processing is executed is stopped. For this reason, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed.

  An information processing apparatus according to another aspect of the present invention includes an instruction fetch unit that fetches an instruction from a main memory, an information processing unit that executes an instruction fetched by the instruction fetch unit, the instruction fetch unit, and the information processing unit. Generates a clock signal having an operable frequency, and controls the clock generation means to be supplied to the instruction fetch means and the information processing means, and the supply and stop of the clock signal from the clock generation means to the information processing means. Clock control means, the clock control means from the clock generation means for a part or all of the period from the start of the instruction fetch operation of the instruction until the acquisition of the instruction The supply of the clock signal to the information processing means is stopped.

  The information processing means cannot execute the process until the instruction is acquired after the instruction fetch means starts the instruction fetch operation. For this reason, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means during that time.

  Preferably, the main memory requires a predetermined time or more for fetching an instruction, and the information processing apparatus further includes a sub-memory capable of loading data in the predetermined time or less, and an instruction fetched by the instruction fetch means Fetch address space identification logic means for determining which address space of the main memory and the sub memory belongs to the address storing the address, and the clock control means includes the address space of the main memory. If the instruction fetching means determines that it belongs to the information processing means from the clock generation means to the information processing means for a part or all of the period from the start of the instruction fetch operation to the acquisition of the instruction. The supply of the clock signal is stopped.

  For example, when the main memory is a RAM and the sub memory is an SRAM, a load delay occurs when data is loaded from the RAM. Therefore, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means until the data loading of the RAM is completed.

  More preferably, the information processing apparatus further includes a main memory control unit that controls reading of an instruction from the main memory in response to an instruction fetch request from the instruction fetch unit with respect to the main memory; And an instruction cache that temporarily holds a copy of the instruction read from the main memory, and when the instruction fetch means tries to fetch the instruction from the main memory, the instruction When there is a miss hit in the read access of the instruction from the cache, the main memory control means starts fetching the instruction from the main memory, and the clock control means supplies the clock to the information processing means. It is characterized by being stopped.

  When a cache miss occurs, data must be loaded from the main memory to the instruction cache, during which load delay occurs. Therefore, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means until the instruction is held in the instruction cache.

  More preferably, the clock control means stores an instruction read from the main memory in the instruction cache when the instruction fetch means tries to fetch an instruction from the instruction cache and makes a miss-hit. The supply of the clock signal to the information processing means is resumed.

  When data is loaded into the instruction cache in this way, processing by the information processing means becomes possible. Therefore, the supply of the clock signal to the information processing can be resumed at this point.

  More preferably, the information processing apparatus further includes main memory control means for controlling reading of an instruction from the main memory in response to an instruction fetch request from the instruction fetch means for the main memory, and the main memory Further, when the instruction fetch unit fetches an instruction from the main memory, an access time unique to the main memory has elapsed after the main memory control unit makes a request to read the instruction to the main memory. A clock stop cancellation signal is output a predetermined time before the predicted time, and the clock control means responds to the clock stop cancellation signal output from the main memory control means in response to the information processing. The supply of the clock signal to the means is resumed.

  In this way, the timing for restarting the supply of the clock signal can be determined by focusing on the access time unique to the main memory.

  More preferably, the information processing apparatus further includes main memory control means for controlling reading of an instruction from the main memory in response to an instruction fetch request from the instruction fetch means for the main memory, and the main memory The control means further includes a response output from the main memory after the main memory control means makes a request to read the instruction to the main memory when the instruction fetch means fetches an instruction from the main memory. A command read completion time from the main memory is predicted based on a signal output timing, and a clock stop release signal is output a predetermined time before the predicted command read completion time. In response to the clock stop cancellation signal output from the control means. , Characterized in that resuming the supply of the clock signal to said information processing means.

  In this manner, by focusing on the output timing of the response signal output from the main memory, it is possible to determine the restart timing of the supply of the clock signal.

  More preferably, the information processing apparatus further includes an instruction buffer unit that temporarily holds an instruction read from the main memory, and the clock control unit fetches the instruction from the main memory. When trying to do so, the supply of the clock signal is stopped for a part or all of the period from the start of the fetch operation to the instruction buffer means storing the instruction read from the main memory. Features.

  A load delay occurs when an instruction is read from the main memory to the instruction buffer. For this reason, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means during that time.

  More preferably, the information processing apparatus further responds to an interrupt signal with a main memory control means for controlling reading of an instruction from the main memory in response to an instruction fetch request from the instruction fetch means for the main memory. And an interrupt control means for controlling the operation of the clock control means. The main memory control means is further configured so that when the instruction fetch means fetches an instruction from the main memory, the main memory control means The interrupt control means predicts a time at which an access time unique to the main memory elapses after a command read request to the main memory, outputs a clock stop release signal a predetermined time before the predicted time, and Accepts the clock stop cancellation signal as an interrupt signal, Notify the control means, said clock control means is responsive to the notification, and wherein the resuming the supply of the clock signal to said information processing means.

In this way, the supply of the clock signal may be resumed by interrupt processing.
An information processing apparatus according to still another aspect of the present invention includes a data loading unit that loads data from a main memory, an information processing unit that performs predetermined processing with reference to data loaded by the data loading unit, and A clock generating means for generating a clock signal having a frequency at which the data loading means and the information processing means can operate and supplying the clock signal to the data loading means and the information processing means; and the clock from the clock generation means to the information processing means A clock control means for controlling supply and stop of a signal; and a data cache that can be accessed at a higher speed than the main memory and that temporarily holds a copy of data read from the main memory. The control means writes the data back from the data cache to the main memory. When, characterized in that to stop the supply of the part or the clock signal to all of the constituent circuit of the information processing means.

  For example, data may need to be written back from the data cache to the main memory in order to maintain data consistency between the data cache and the main memory. In such a case, a load delay occurs until data is stored in the main memory. Therefore, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means during that time.

  An information processing apparatus according to still another aspect of the present invention includes a data loading unit that loads data from a main memory, an information processing unit that performs predetermined processing with reference to data loaded by the data loading unit, and A clock generating means for generating a clock signal having a frequency at which the data loading means and the information processing means can operate and supplying the clock signal to the data loading means and the information processing means; and the clock from the clock generation means to the information processing means Clock control means for controlling signal supply and stop, load buffer means for temporarily holding data read from the main memory, and DMA control for controlling data transfer from the main memory to the load buffer means And the load buffer means receives the information from the main memory. It functions as an intermediate temporary buffer for holding data in a first-in first-out manner for data transfer to the processing means, and the clock control means is in a part or all of a period in which no data is stored in the load buffer means. Further, the supply of the clock signal to a part or all of the constituent circuits of the information processing means is stopped.

  If no data is stored in the load buffer used for DMA transfer, there is no data to be processed by the information processing means. For this reason, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means during that time.

  An information processing apparatus according to still another aspect of the present invention includes a data loading unit that loads data from a main memory, an information processing unit that performs predetermined processing with reference to data loaded by the data loading unit, and A clock generating means for generating a clock signal having a frequency at which the data loading means and the information processing means can operate and supplying the clock signal to the data loading means and the information processing means; and the clock from the clock generation means to the information processing means Clock control means for controlling supply and stop of signals, store buffer means for temporarily holding data to be stored in the main memory, and store for storing data held by the store buffer means in the main storage device And the clock control means is configured such that the store means stores the store back. When trying to store the data held by the memory means into the main memory, the supply of the clock signal is stopped for a part or all of the period from the start of the store operation until the data is written into the main memory. It is characterized by making it.

  When data stored in the store buffer is written back to the main memory, a load delay occurs. For this reason, the power consumed by the information processing means can be reduced by stopping the supply of the clock signal to the information processing means during that time.

  An information processing apparatus according to still another aspect of the present invention includes a data load unit that loads data from a main memory, and a pipeline type that executes predetermined processing with reference to the data loaded by the data load unit Information processing means having a processing structure based on a processing method; clock generation means for generating a clock signal having a frequency at which the data loading means and the information processing means can operate, and supplying the clock signals to the data loading means and the information processing means; Clock control means for controlling the supply and stop of the clock signal from the clock generation means to the information processing means, the clock control means for the pipeline stage to which the process that stopped the clock supply belongs, In the cycle following the cycle in which the clock supply is stopped, the pipeline is The clock supply to the circuit of the information processing means constituting the next stage of the stages of the emission stage, wherein the stopping.

  With such a configuration, for example, a clock signal to a component belonging to a stage where no processing is executed is stopped. For this reason, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed.

  An information processing apparatus according to still another aspect of the present invention is characterized in that the information processing apparatus includes power supply cutoff means for cutting off power supply to the information processing apparatus instead of the clock control means, and the power supply cutoff. The means is characterized in that power supply to the information processing apparatus is cut off during a period in which the clock control means stops the supply of the clock signal to the information processing means.

  Power consumption can be suppressed by cutting off the power supply instead of supplying the clock signal.

  An information device according to still another aspect of the present invention comprises any one of the information processing apparatuses described above.

  Specific examples of the information device include a mobile phone, a portable game machine, a video camera, a still image camera, a PDA (Personal Digital Assistant), a portable PC (Personal Computer), an electronic dictionary, and the like. In addition, in-vehicle products such as car navigation are examples of information devices that are strongly demanded to reduce power consumption.

  Note that the present invention can be realized not only as an information processing apparatus including such characteristic means but also as an information processing method using characteristic means included in the information processing apparatus as a step, It can also be realized as a program that causes a computer to execute characteristic steps included in the processing method. Needless to say, such a program can be distributed via a recording medium such as a CD-ROM (Compact Disc-Read Only Memory) or a communication network such as the Internet.

  According to the present invention, it is possible to reduce power consumption during operation while maintaining the performance and cost of the prior art.

  In particular, since power consumption at the time of memory access can be reduced, a large effect can be exhibited in an information processing apparatus that frequently accesses an external low-speed memory such as a DSP (Digital Signal Processor).

  Hereinafter, a low power consumption type information processing apparatus according to an embodiment of the present invention will be described. Prior to the description of each embodiment, matters common to each embodiment will be described.

  The low power consumption type information processing apparatus according to the embodiment of the present invention employs a widely spread five-stage pipeline process, and the concept of the process steps is shown in FIG. Each pipeline stage is mainly responsible for the processing described in Table 1.

  Table 2 shows the relationship between each pipeline stage and the components operating in that stage.

  Table 3 shows the classification of instructions implemented by the low power consumption information processing apparatus according to the embodiment of the present invention. The information processing apparatus according to the embodiment of the present invention employs a so-called load / store architecture.

  In the circuit / block configuration diagram described in the following embodiments, the bus signal line notation shown in FIG. 2 is adopted. The double line represents the instruction data bus. A thin broken line represents an instruction address bus. A thick solid line represents a data bus for data. A thick broken line represents a data address bus. Other thin solid lines represent control signals and the like.

(Embodiment 1)
FIG. 3 is a diagram showing a configuration of a system including the low power consumption information processing apparatus according to Embodiment 1 of the present invention. This system is realized as a system LSI (Large Scale Integration) or an information equipment system.

The system includes a DRAM 102 and a low power consumption information processing apparatus 101.
The DRAM 102 is a DRAM that stores instructions executed by the low power consumption information processing apparatus 101, various data used by the low power consumption information processing apparatus 101, and the storage capacity thereof is compared with other SRAMs. However, the access time and cycle time are relatively long.

  The low power consumption information processing apparatus 101 is configured by a semiconductor LSI for information processing or a SoC (System on a Chip). The low power consumption type information processing apparatus 101 is a processing apparatus that loads instructions and data stored in the DRAM 102 and executes the instructions. The information processing core 103, the instruction ROM 104, the data SRAM 106, and the bus control unit 108. A peripheral circuit 109, a memory control unit 110, and a PLL (Phase Locked Loop) 111.

  The information processing core 103 is a general-purpose processing unit in the low power consumption information processing apparatus 101, and plays a central role in information processing, data processing, and system control over the entire system.

  The instruction ROM 104 is a read-only memory that stores an instruction sequence as a program executed by the information processing core 103.

  The data SRAM 106 is a so-called static RAM for temporarily storing work data when the information processing core 103 executes processing.

  The bus control unit 108 is a processing unit that controls an internal bus accessed by the information processing core 103 and peripheral circuits connected thereto.

  The peripheral circuit 109 is composed of a dedicated circuit group having several roles. For example, an interrupt control circuit, a timer, a counter, a serial input / output circuit, a host interface circuit, an A / D (Analog to Digital) conversion circuit, a D / A (Digital to Analog) conversion circuit, DMAC (Direct Memory Access Controller), debugger and the like.

  The memory control unit 110 is a processing unit that controls reading and writing of data with an external memory such as the DRAM 102.

  The PLL 111 is a circuit that is connected to an externally connected crystal oscillator (crystal oscillator), generates a clock signal, and supplies the clock signal to each circuit block of the low power consumption information processing apparatus 101.

  The low power consumption information processing apparatus 101 is generally called a microprocessor, a microcontroller, a DSP (Digital Signal Processor), and the like, and is exemplified as a semiconductor integrated circuit that is widely commercialized. The low power consumption information processing apparatus 101 according to the present embodiment employs a so-called Harvard architecture.

FIG. 4 is a diagram illustrating a configuration of the information processing core 103.
The information processing core 103 includes an instruction fetch unit 221, an instruction decode unit 222, an operand address calculation unit 223, an instruction address calculation unit 224, an instruction execution unit 225, a register file 226, a load store unit 227, a register A file write path selector 228, a program counter 231, a load source address space identification logic circuit 232, and a clock control logic circuit 233 are included.

  The instruction fetch unit 221 is a processing unit that fetches an instruction from an external instruction memory such as the instruction ROM 104 or the DRAM 102, an instruction cache in which instructions previously fetched from them are stored, or an internal instruction buffer.

  The instruction decode unit 222 is a processing unit that decodes the instruction fetched by the instruction fetch unit 221 and controls the behavior of the circuit after the next stage according to the result of decoding.

  The operand address calculation unit 223 is a processing unit that calculates the source address of the load instruction and the destination address of the store instruction.

  The instruction address calculation unit 224 is a processing unit that calculates a branch destination address of a branch instruction.

  The instruction execution unit 225 is a processing unit that includes an arithmetic logic unit, a multiplier, a barrel shifter, and the like, and executes an arithmetic logic operation designated by the operation instruction.

  The register file 226 includes a plurality of general-purpose registers and can be accessed at high speed from an instruction. Each register is a storage unit for storing data or address information.

  The load / store unit 227 includes a load buffer 229 and a store buffer 230, and is a processing unit that controls a load operation and a store operation between a memory and a register.

  The load buffer 229 is a storage unit that stores an instruction loaded by a load instruction and wakes up an information processing core circuit that has entered a sleep state upon completion of loading.

  The store buffer 230 includes a plurality of FIFO queues, and is a storage unit that holds data stored in a memory from a store request to a store completion.

  The register file write path selector 228 is a processing unit that selects a write path to one write port of the register file 226 according to the type of instruction.

  The program counter 231 is a register that stores an address of a program (instruction) to be fetched and decoded next in the IF stage and the DEC stage.

  The load source address space identification logic circuit 232 determines the address space into which data is loaded when executing a load instruction, and determines whether or not the load time from the space requires the number of cycles equal to or greater than a specified value It is.

  When executing the load instruction, the clock control logic circuit 233 determines that the load source address space identification logic circuit 232 requires the number of cycles equal to or greater than a specified value, and stops the supply of the clock signal to the predetermined circuit. It is.

  For simplification, it is assumed that the access time of the data SRAM 106 and the instruction ROM 104 is one cycle by the clock of the information processing core 103. On the other hand, the access time and cycle time of the DRAM 102 are often several tens of cycles by the clock of the information processing core 103.

  FIG. 1 shows the pipeline logic configuration and operation of the low power consumption type information processing apparatus 101, particularly the information processing core 103, in this embodiment. A pipeline operation composed of five basic stages changes adaptively according to the type of instruction. The operation and function of the low power consumption type information processing apparatus 101, particularly the information processing core 103 in this embodiment will be described below for each type of instruction.

  First, Table 4 shows a schematic processing operation of the low-power consumption information processing apparatus 101, particularly the information processing core 103, regarding “arithmetic instructions”.

  Secondly, Table 5 shows a schematic processing operation of the low power consumption type information processing apparatus 101, particularly the information processing core 103, regarding the “data transfer instruction”.

  Thirdly, Table 6 shows a schematic processing operation of the low power consumption type information processing apparatus 101, particularly the information processing core 103, for the “load instruction”.

  Fourth, Table 7 shows a schematic processing operation of the low power consumption type information processing apparatus 101, particularly the information processing core 103, for the "store instruction".

  FIG. 5 shows a mechanism in which the clock control logic circuit 233 stops the clock signal supply to a specific circuit block by clock gating.

  In FIG. 5, a description will be given assuming that a D-FF (Flip Flop) 301 is a circuit to which a clock signal is supplied. The clock control logic circuit 233 outputs a clock control signal for determining whether or not to supply a clock signal for each clock signal supply target circuit included in the information processing core 103. The PLL 111 outputs a clock signal for each supply target circuit. The information processing core 103 further includes a buffer 303 and an AND gate 305 provided for each supply target circuit. The buffer 303 is connected to the PLL 111 and temporarily holds the clock signal output from the PLL 111. The AND gate 305 is connected to the clock control logic circuit 233 and the buffer 303, and outputs a logical sum of the clock control signal output from the clock control logic circuit 233 and the clock signal held in the buffer 303. The D-FF 301 operates in accordance with a gated clock signal that is a logical sum output from the AND gate 305.

  While the clock control signal output from the clock control logic circuit 233 is fixed at the low level, the output of the AND gate 305 is always low. For this reason, the supply of the clock signal to the D-FF 301 is stopped. Therefore, the output value Q of the D-FF 301 does not change regardless of the change of the input value D.

  In the above description, the circuit to be supplied with the clock signal is D-FF 301. However, the circuit to be supplied is configured as each component of the information processing core 103, and a gated clock signal is input to each component. As a result, the clock control logic circuit 233 can stop the clock signal supply to a specific circuit block by clock gating.

  As described above, in the present embodiment, when the instruction executed in the information processing core 103 is a “load instruction”, in the MEM stage at the time of execution of the load instruction, other than the load buffer 229 in the information processing core 103. The supply of the clock signal to this circuit is stopped. As a result, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. The low power consumption information processing apparatus according to the second embodiment stops supplying a clock signal to a predetermined circuit when it takes time to fetch an instruction.

  FIG. 3 is a diagram illustrating a configuration of a system including the low power consumption information processing apparatus according to the present embodiment. The configuration of the low power consumption information processing apparatus 101 is the same as that of the first embodiment. Therefore, detailed description thereof will not be repeated here.

FIG. 6 is a diagram showing a configuration of the information processing core 103 according to the second embodiment.
The information processing core 103 uses the fetch address space identification logic circuit 252 instead of the load source address space identification logic circuit 232 in the information processing core 103 according to the first embodiment shown in FIG.

  The fetch address space identification logic circuit 252 determines an address space in which an instruction is fetched when executing an instruction fetch, and determines whether a fetch time from the space requires a number of cycles equal to or greater than a specified value.

  When the instruction address is fetched, the clock control logic circuit 233 determines that the fetch address space identification logic circuit 252 requires a cycle number equal to or greater than a specified value, and stops supplying a clock signal to a predetermined circuit.

  The case where the instruction fetch requires a number of cycles equal to or greater than a specified value is a case where the instruction to be fetched is not stored in the instruction ROM 104 and must be fetched from the DRAM 102. In other cases, that is, the case where the number of cycles of instruction fetching is less than the prescribed value is sufficient when the instruction to be fetched is stored in the instruction ROM 104 and can be fetched from the instruction ROM 104. The fetch address space identification logic circuit 252 determines that an instruction fetch requires a number of cycles equal to or greater than a prescribed value when an address (fetch address) where an instruction to be fetched is stored belongs to an address space on the DRAM 102. In other cases, that is, when the fetch address belongs to the address space on the instruction ROM 104, the fetch address space identification logic circuit 252 determines that the instruction fetch ends with the number of cycles less than the specified value.

  FIG. 1 shows the pipeline logic configuration and operation of the low power consumption type information processing apparatus 101, particularly the information processing core 103, in this embodiment. A pipeline operation composed of five basic stages changes adaptively according to the type of instruction.

  The operations and functions related to instruction fetching of the low power consumption type information processing apparatus 101, particularly the information processing core 103 in this embodiment relate to instruction fetching, but the instruction fetching operation does not depend on the type of instruction. For this reason, a data operation instruction will be described below as an example.

  Table 8 shows a schematic processing operation related to the “instruction fetch” of the low power consumption type information processing apparatus 101, particularly the information processing core 103, regarding the arithmetic instruction.

  As described above, according to the present embodiment, when it is known that a load delay occurs in advance at the time of instruction fetch, the clock signal to the circuits in the information processing core 103 other than the instruction fetch unit 221 is obtained. Supply has been stopped. As a result, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. The low power consumption type information processing apparatus according to the third embodiment is an apparatus using a cache, and stops supplying a clock signal to a predetermined circuit when a cache miss occurs when a load instruction is executed.

  FIG. 7 is a diagram illustrating a configuration of a system including the low power consumption information processing apparatus according to the present embodiment.

  The low power consumption information processing apparatus 101 according to the present embodiment uses an instruction cache 105 instead of the instruction ROM 104 in the configuration of the low power consumption information processing apparatus 101 according to the first embodiment illustrated in FIG. A data cache 107 is used instead of the data SRAM 106.

  The instruction cache 105 temporarily stores an instruction sequence fragment of the information processing core 103 instead of the instruction ROM 104, and is a small-capacity memory that can be accessed faster than the DRAM 102 on average.

  The data cache 107 temporarily stores work data for the information processing core 103 instead of the data SRAM 106, and is a small-capacity memory that can be accessed at a higher speed on average than the DRAM 102.

  FIG. 8 is a diagram illustrating a configuration of the information processing core 103. The information processing core 103 shown in the figure includes a cache controller 261 that controls the data cache 107 except for the load source address space identification logic circuit 232 in the configuration of the information processing core 103 according to the first embodiment shown in FIG. It is what was used.

  As shown in the figure, the data cache 107 includes a data part 235 and a tag part 236. The data unit 235 holds temporary data as a copy of the DRAM 102. The tag unit 236 gives address information to the data held in the data unit 235. The data cache 107 is associative memory. For this reason, when reading data from the data cache 107, the information processing core 103 first searches the tag part 236 with the load source address, and if the address information matches (cache hit), then extracts the data from the data part 235. If the address information does not match (cache miss), there is no data to be requested from the data cache 107, and the information processing core 103 then accesses the DRAM 102.

  When the information processing core 103 accesses the data cache 107, the tag unit 236 supplies a cache hit / miss determination logic signal indicating whether a cache hit or a cache miss has occurred to the load store unit 227 and the clock control logic circuit 233. To do.

  Note that the data SRAM 106 and the data cache 107 shown in FIG. 3 are not deleted, but the data SRAM 106 and the data cache 107 are connected to the information processing core 103 in parallel, and the information processing core 103 is connected to each cycle from one of the data SRAM 106 and the data cache 107. A circuit configuration that allows data to be selectively loaded is also conceivable.

  Table 9 lists the schematic processing operations of the low power consumption information processing apparatus 101, particularly the information processing core 103, for the load instruction.

  As described above, according to the present embodiment, when a cache miss occurs in the MEM stage at the time of executing the load instruction, the circuit in the information processing core 103 other than the load buffer 229 in the load store unit 227 is transferred to the circuit. The clock signal supply is stopped. As a result, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs.

(Embodiment 4)
Embodiment 4 of the present invention will be described below. The low power consumption type information processing apparatus according to the fourth embodiment stops the supply of a clock signal to a predetermined circuit when a cache miss occurs during instruction fetch.

  FIG. 7 is a diagram illustrating a configuration of a system including the low power consumption information processing apparatus according to the present embodiment. The configuration of the low power consumption information processing apparatus 101 is the same as that of the third embodiment. Therefore, detailed description thereof will not be repeated here.

  FIG. 9 is a diagram illustrating a configuration of the information processing core 103 according to the fourth embodiment. The information processing core 103 shown in this figure is obtained by removing the fetch address space identification logic circuit 252 from the configuration of the information processing core 103 shown in FIG.

  As shown in the figure, the instruction cache 105 includes a data part 237 and a tag part 238. The data unit 237 holds temporary data as a copy of the DRAM 102. The tag unit 238 gives address information to the data held in the data unit 237. The instruction cache 105 is associative memory. Therefore, when reading data from the instruction cache 105, the information processing core 103 first searches the tag part 238 with the fetch address, and if the address information matches (cache hit), then extracts the data from the data part 237. If the address information does not match (cache miss), there is no data to be requested from the instruction cache 105, and the information processing core 103 then accesses the DRAM 102.

  When the information processing core 103 accesses the instruction cache 105, the tag unit 238 supplies a cache hit / miss determination logic signal indicating whether a cache hit or a cache miss has occurred to the load store unit 227 and the clock control logic circuit 233. To do.

  Note that the instruction ROM 104 and the instruction cache 105 shown in FIG. 3 are not deleted, but the instruction ROM 104 and the instruction cache 105 are connected in parallel to the information processing core 103, and the information processing core 103 selects one of the instruction ROM 104 and the instruction cache 105 for each cycle. It is also possible to consider a circuit configuration that enables fetching automatically.

  The operations and functions related to instruction fetching of the low power consumption type information processing apparatus 101, particularly the information processing core 103 in this embodiment relate to instruction fetching, but the instruction fetching operation does not depend on the type of instruction. For this reason, an operation instruction will be described below as an example.

  Table 10 shows a schematic processing operation related to “instruction fetch” of the low power consumption type information processing apparatus 101, particularly the information processing core 103, regarding the arithmetic instruction.

  As described above, according to the present embodiment, when a cache miss occurs during instruction fetch, the clock signal supply to the circuits in the information processing core 103 other than the instruction fetch unit 221 is stopped. ing. As a result, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs.

(Embodiment 5)
Next, a fifth embodiment of the present invention will be described. In the power consumption type information processing apparatus according to the fifth embodiment, the memory control unit 110 predicts the data read completion time when the load instruction is executed, and stops supplying the clock signal to a predetermined circuit until the data read is completed. To do.

FIG. 10 shows a system configuration including the low power consumption type information processing apparatus according to the present embodiment.
The low power consumption information processing apparatus 101 according to the present embodiment has a data read completion time in the memory control unit 110 in the configuration of the low power consumption information processing apparatus 101 according to the first embodiment shown in FIG. A prediction unit 110a is provided.

  The data read completion time prediction unit 110a is a processing unit that predicts a data read completion time from the DRAM 102 and outputs a clock stop release signal 112 a predetermined time before the prediction time. A method for predicting the data read completion time will be described later.

  FIG. 11 is a diagram illustrating a configuration of the information processing core 103. The information processing core 103 shown in this figure is different in the configuration of the clock control logic circuit 233 from the configuration of the information processing core 103 according to the first embodiment shown in FIG. That is, the clock control logic circuit 233 receives the clock stop cancellation signal 112 output from the data read completion time prediction unit 110a, and cancels the supply stop of the clock signal in response to the clock stop cancellation signal 112.

  Hereinafter, a data load operation from the DRAM 102 by a load instruction will be described.

(1) The load / store unit 227 requests read access from the DRAM 102 to the memory control unit 110 through the bus control unit 108.
(2) Since the load source address space identification logic circuit 232 identifies access to the DRAM 102, the clock control logic circuit 233 outputs a clock signal to circuits in the information processing core 103 other than the load buffer 229 in the load store unit 227. Stop supplying.
(3) The memory control unit 110 reads the source operand from the load source address of the DRAM 102.
(4) The memory control unit 110 sends the source operand loaded from the DRAM 102 to the information processing core 103 through the bus control unit 108.
(5) The data read completion time prediction unit 110a of the memory control unit 110 predicts the read completion time and sends a clock stop cancellation signal 112 to the information processing core 103 a predetermined time before the prediction time.
(6) The clock control logic circuit 233 releases the stop of the clock signal supply in response to the clock stop release signal 112.

  As the method for determining the timing at which the memory control unit 110 asserts the clock stop cancellation signal 112, the following two methods are assumed.

(1) The data read completion time prediction unit 110a predicts the data read completion time from the DRAM 102 as follows. When the DRAM 102 is an asynchronous DRAM, the data read completion time prediction unit 110a can predict the data read completion time based on the timing of asserting an OE (Output Enable) signal to the DRAM 102. When the DRAM 102 is a synchronous DRAM (SDRAM), the data read completion time prediction unit 110a predicts that the first data is read when “RAS-CAS latency (RAS to CAS delay time) + CAS latency (CAS access time)” elapses. To do. However, this prediction is effective in the case of random access, and the read timing of the second and subsequent data in burst access does not follow the above prediction. However, since the cycle time of burst transfer is generally short, the effect of the present invention in burst access is reduced.
(2) The data read timing is known by looking at the response signal (ACK) from the DRAM 102 to the read request.

  As described above, according to the present embodiment, when the instruction executed in the information processing core 103 is a “load instruction”, to the circuit in the information processing core 103 other than the load buffer 229 in the load store unit 227. The clock signal supply is stopped. Further, the supply of the clock signal is resumed at the data read completion time predicted by the data read completion time prediction unit 110a. As a result, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs when the load instruction is executed.

(Embodiment 6)
Next, a sixth embodiment of the present invention will be described. In the power consumption type information processing apparatus according to the sixth embodiment, the memory control unit 110 predicts the read completion time at the time of instruction fetch and stops supplying the clock signal to a predetermined circuit until the data read is completed. It is.

  The low power consumption information processing apparatus according to the present embodiment has the same configuration as the low power consumption information processing apparatus 101 according to the fifth embodiment shown in FIG. Therefore, detailed description thereof will not be repeated here.

  FIG. 12 is a diagram illustrating a configuration of the information processing core 103. The information processing core 103 shown in this figure is different in the configuration of the clock control logic circuit 233 from the configuration of the information processing core 103 according to the second embodiment shown in FIG. That is, the clock control logic circuit 233 receives the clock stop release signal 112 output from the data read completion time prediction unit 110a a predetermined time before the read completion time, and in response to the clock stop release signal 112, Release the supply stop.

  Hereinafter, an instruction fetch operation from the DRAM 102 will be described. The instruction fetch operation does not depend on the type of instruction. For this reason, an operation instruction will be described below as an example.

(1) The instruction fetch unit 221 requests a read access from the DRAM 102 to the memory control unit 110 through the bus control unit 108.
(2) Since the fetch address space identification logic circuit 252 identifies access to the DRAM 102, the clock control logic circuit 233 stops supplying the clock signal to the circuits in the information processing core 103 other than the instruction fetch unit 221.
(3) The memory control unit 110 reads the next instruction from the fetch address of the DRAM 102.
(4) The memory control unit 110 sends the next instruction fetched from the DRAM 102 to the information processing core 103 through the bus control unit 108.
(5) The data read completion time prediction unit 110 a of the memory control unit 110 sends a clock stop cancellation signal 112 to the information processing core 103.
(6) The clock control logic circuit 233 releases the stop of the clock signal supply in response to the clock stop release signal 112.

  The method for determining the timing at which the data read completion time prediction unit 110a of the memory control unit 110 asserts the clock stop cancellation signal 112 is as described in the fifth embodiment.

  As described above, according to the present embodiment, at the time of instruction fetch, supply of the clock signal to the circuits in the information processing core 103 other than the instruction fetch unit 221 is stopped. Further, the supply of the clock signal is resumed at the data read completion time predicted by the data read completion time prediction unit 110a. Thereby, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs at the time of instruction fetch.

(Embodiment 7)
Next, a seventh embodiment of the present invention will be described. The low power consumption type information processing apparatus according to the seventh embodiment is different from the fifth embodiment in the method for determining the stop release timing of the clock signal supply. That is, in the seventh embodiment, when the load instruction is executed, the stop of the supply of the clock signal is released when the load data is written in the load buffer 229 of the information processing core 103.

  The configuration of the low power consumption information processing apparatus according to Embodiment 7 is the same as that of the low power consumption information processing apparatus 101 according to Embodiment 1 shown in FIG. Therefore, detailed description thereof will not be repeated here.

FIG. 13 is a diagram illustrating a configuration of the information processing core 103 according to the seventh embodiment.
The information processing core 103 is different from the information processing core 103 according to Embodiment 1 shown in FIG. 4 in the configuration of the load buffer 229 and the clock control logic circuit 233. That is, the load buffer 229 outputs an arrival signal when the load data arrives. In response to the arrival signal output from the load buffer 229, the clock control logic circuit 233 releases the supply stop of the clock signal.

  Hereinafter, a data load operation from the DRAM 102 by a load instruction will be described.

(1) The load / store unit 227 requests read access from the DRAM 102 to the memory control unit 110 through the bus control unit 108.
(2) Since the load source address space identification logic circuit 232 identifies access to the DRAM 102, the clock control logic circuit 233 outputs a clock signal to circuits in the information processing core 103 other than the load buffer 229 in the load store unit 227. Stop supplying.
(3) The memory control unit 110 reads the source operand from the load source address of the DRAM 102.
(4) The memory control unit 110 sends the source operand loaded from the DRAM 102 to the information processing core 103 through the bus control unit 108.
(5) Load data is written to the load buffer 229.
(6) The load buffer 229 detects that the load data has arrived, and notifies the clock control logic circuit 233 of the arrival.
(7) The clock control logic circuit 233 cancels the supply stop of the clock signal and restores the clock signal supply.

  As described above, according to the present embodiment, when the instruction executed in the information processing core 103 is a “load instruction”, to the circuit in the information processing core 103 other than the load buffer 229 in the load store unit 227. The clock signal supply is stopped. Further, after detecting that the load data has been written into the load buffer 229, the supply of the clock signal is resumed. As a result, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs when the load instruction is executed.

  In the fifth embodiment, the data read completion time prediction unit 110a predicts the load data read completion time. However, in the seventh embodiment, the clock signal can be generated without providing such a special circuit. The supply stop can be released.

(Embodiment 8)
Next, an eighth embodiment of the present invention will be described. The low power consumption type information processing apparatus according to the eighth embodiment is different from the sixth embodiment in the method for determining the stop release timing of the clock signal supply. That is, in the sixth embodiment, the timing at which the data read completion time prediction unit 110a cancels the stop of the clock signal supply is determined. On the other hand, in this embodiment, the supply stop of the clock signal is released when the next instruction is written in the instruction buffer 239 provided in the instruction fetch unit 221.

  The configuration of the low power consumption information processing apparatus according to this embodiment is the same as that of the low power consumption information processing apparatus 101 according to Embodiment 1 shown in FIG.

  FIG. 14 is a diagram showing a configuration of the information processing core according to the present embodiment. The configuration of the information processing core according to the present embodiment is different from the configuration of the information processing core 103 according to the second embodiment shown in FIG. 6 in the configurations of the instruction fetch unit 221 and the fetch address space identification logic circuit 252. That is, the instruction fetch unit 221 has a built-in instruction buffer 239 that is a temporary storage unit for storing a plurality of instructions subsequent to the instruction currently being decoded, but the instruction buffer 239 outputs an arrival signal when the instruction arrives. . In response to the arrival signal output from the instruction buffer 239, the fetch address space identification logic circuit 252 releases the supply stop of the clock signal.

FIG. 15 is a diagram showing a configuration of the instruction fetch unit 221. As shown in FIG.
The instruction fetch unit 221 includes an instruction buffer 239, an instruction register 239a, an incrementer 239b, and a program counter 239c.

  The instruction buffer 239 is a memory that temporarily stores data using a FIFO method. The instruction buffer 239 outputs an arrival signal when an instruction is written.

  The instruction register 239a is a register that is connected to the output of the instruction buffer 239 and temporarily stores an instruction that is next decoded by the instruction decoding unit 222.

  The program counter 239c is a counter that stores an instruction fetch address in the IF stage.

  The incrementer 239b is an arithmetic unit that increments the fetch address by a predetermined number each time an instruction is fetched.

  Hereinafter, an instruction fetch operation from the DRAM 102 will be described. The instruction fetch operation does not depend on the type of instruction. For this reason, an operation instruction will be described below as an example.

(1) The instruction fetch unit 221 requests a read access from the DRAM 102 to the memory control unit 110 through the bus control unit 108.
(2) Since the fetch address space identification logic circuit 252 identifies access to the DRAM 102, the clock control logic circuit 233 stops supplying the clock signal to the circuits in the information processing core 103 other than the instruction fetch unit 221.
(3) The memory control unit 110 reads the next instruction from the fetch address of the DRAM 102.
(4) The memory control unit 110 sends the next instruction fetched from the DRAM 102 to the information processing core 103 through the bus control unit 108.
(5) The next instruction is written into the instruction buffer 239.
(6) The instruction buffer 239 detects that the next instruction has arrived and notifies the clock control logic circuit 233 of it.
(7) The clock control logic circuit 233 cancels the supply stop of the clock signal and restores the clock signal supply.

  As described above, according to the present embodiment, at the time of instruction fetch, supply of the clock signal to the circuits in the information processing core 103 other than the instruction fetch unit 221 is stopped. In addition, after detecting that an instruction has been written in the instruction buffer 239, the supply of the clock signal is resumed. Thereby, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs at the time of instruction fetch.

  In the sixth embodiment, the data read completion time prediction unit 110a predicts the load data read completion time. However, in this embodiment, the clock signal can be generated without providing such a special circuit. The supply stop can be released.

(Embodiment 9)
Next, a ninth embodiment of the present invention will be described. In the low power consumption type information processing apparatus according to the present embodiment, the method for determining the stop release timing of the clock signal supply is different from that of the fifth embodiment. That is, the information processing core of the low power consumption information processing apparatus according to the present embodiment cancels the supply stop of the clock signal based on the interrupt.

  The configuration of the low power consumption information processing apparatus according to the present embodiment is the same as that of the low power consumption information processing apparatus 101 according to the fifth embodiment shown in FIG.

FIG. 16 is a diagram showing a configuration of the information processing core according to the present embodiment.
The information processing core 103 is obtained by changing the configuration of the clock control logic circuit 233 by adding an interrupt control unit 240 to the configuration of the information processing core 103 according to the first embodiment shown in FIG.

  The interrupt control unit 240 receives the clock stop release signal 112 output from the data read completion time prediction unit 110 a of the memory control unit 110 as an interrupt, and transmits the stop release signal to the clock control logic circuit 233.

  The clock control logic circuit 233 releases the supply stop of the clock signal in response to the stop release signal transmitted from the interrupt control unit 240.

  In the present embodiment, two operation states called “clock stop mode” and “normal operation mode” are defined when the load instruction described in the fifth embodiment is executed.

  The “clock stop mode” is a load data wait state for waiting for data to be loaded into the load buffer 229, or a low power consumption operation state in which the supply of the clock signal is stopped. The “normal operation mode” is a state where a clock is supplied to each circuit in the information processing core 103 and an original functional operation synchronized with the clock is possible.

  In this embodiment, since the information processing core 103 is provided with the interrupt control unit 240, the state transition from the clock stop mode to the normal operation mode is realized as a wakeup from the clock stop state due to the interrupt. The clock stop cancellation signal 112 output from the data read completion time prediction unit 110a described in the fifth embodiment is input to the interrupt control unit 240 as a wakeup interrupt. When releasing the supply stop of the clock signal when executing the load instruction, the following procedure is performed. Note that the processing up to the stop of the supply of the clock signal (transition processing from the normal operation mode to the clock stop mode) is the same as in the fifth embodiment.

(1) When the memory control unit 110 receives data to be loaded, the memory control unit 110 asserts a clock stop cancellation signal 112.
(2) The clock stop cancellation signal 112 is input to the interrupt control unit 240 as a wakeup interrupt. The interrupt factor is implemented as a non-maskable interrupt (NMI) so that the interrupt factor is always enabled (permitted). The interrupt control unit 240 receives the interrupt factor. The operating state of the information processing core 103 transitions from the clock stop mode to the normal operation mode.
(3) The interrupt control unit 240 notifies the clock control logic circuit 233 that the supply of the clock signal is stopped. The clock control logic circuit 233 wakes up the information processing core 103 by restoring the supply of the clock signal.
(4) The information processing core 103 returns to the MEM stage of the load instruction, and resumes operation from the WB stage that is the next stage.

The relationship between the operation modes described in this embodiment is shown in the state transition diagram of FIG.
The clock stop mode 1 and the clock stop mode 2 are different in the circuit range in which the supply of the clock signal is stopped. That is, in the clock stop mode 1, the supply of the clock signal to all the circuits in the information processing core 103 is stopped. On the other hand, in the clock stop mode 2, the supply of the clock signal to the circuits in the information processing core 103 other than the load buffer 229 in the load store unit 227 is stopped. That is, the state transition described in the present embodiment is a state transition between the normal operation mode and the clock stop mode 2.

  As described above, according to the present embodiment, when the instruction executed in the information processing core 103 is a “load instruction”, to the circuit in the information processing core 103 other than the load buffer 229 in the load store unit 227. The clock signal supply is stopped. Further, the supply of the clock signal is resumed at the data read completion time predicted by the data read completion time prediction unit 110a. As a result, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs when the load instruction is executed.

(Embodiment 10)
Next, an embodiment 10 of the invention will be described. The low power consumption type information processing apparatus according to the present embodiment is different from the sixth embodiment in the method for determining the stop release timing of the clock signal supply. That is, the information processing core of the low power consumption information processing apparatus according to the present embodiment cancels the supply stop of the clock signal based on the interrupt.

  The configuration of the low power consumption information processing apparatus according to the present embodiment is the same as that of the low power consumption information processing apparatus 101 according to Embodiment 5 shown in FIG.

FIG. 18 is a diagram showing a configuration of the information processing core according to the present embodiment.
The information processing core 103 is obtained by adding a new interrupt control unit 240 to the configuration of the information processing core 103 according to the second embodiment shown in FIG.

  The interrupt control unit 240 receives the clock stop release signal 112 output from the data read completion time prediction unit 110 a of the memory control unit 110 as an interrupt, and transmits the stop release signal to the clock control logic circuit 233.

  The clock control logic circuit 233 releases the supply stop of the clock signal in response to the stop release signal transmitted from the interrupt control unit 240.

  In the present embodiment, at the time of executing the instruction fetch described in the sixth embodiment, two operation states called “clock stop mode” and “normal operation mode” are defined.

  The “clock stop mode” is a state of waiting for an instruction fetched from the DRAM 102 or an operating state of low power consumption in which the supply of a clock signal is stopped. The “normal operation mode” is an operation state other than the “clock stop mode”.

  In this embodiment, since the information processing core 103 is provided with the interrupt control unit 240, the state transition from the clock stop mode to the normal operation mode is realized as a wakeup from the clock stop state due to the interrupt. The clock stop cancellation signal 112 output from the data read completion time prediction unit 110a described in the sixth embodiment is input to the interrupt control unit 240 as a wakeup interrupt. When releasing the supply of the clock signal at the time of instruction fetch, the following procedure is performed. Note that the processing up to the stop of the supply of the clock signal (transition processing from the normal operation mode to the clock stop mode) is the same as in the sixth embodiment.

(1) When the memory control unit 110 receives an instruction fetched from the DRAM 102, the memory control unit 110 asserts a clock stop cancellation signal 112.
(2) The clock stop cancellation signal 112 is input to the interrupt control unit 240 as a wakeup interrupt. The interrupt factor is implemented as an interrupt factor NMI so that the interrupt factor is always enabled (permitted). The interrupt control unit 240 receives the interrupt factor. The operating state of the information processing core 103 transitions from the clock stop mode to the normal operation mode.
(3) The interrupt control unit 240 notifies the clock control logic circuit 233 that the supply of the clock signal is stopped. The clock control logic circuit 233 wakes up the information processing core 103 by restoring the supply of the clock signal.
(4) The information processing core 103 returns to the IF stage of the instruction being fetched, and resumes operation from the DEC stage which is the next stage.

  As described above, according to the present embodiment, at the time of instruction fetch, supply of the clock signal to the circuits in the information processing core 103 other than the instruction fetch unit 221 is stopped. Further, the supply of the clock signal is resumed at the data read completion time predicted by the data read completion time prediction unit 110a. Thereby, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs at the time of instruction fetch.

(Embodiment 11)
Hereinafter, an eleventh embodiment of the present invention will be described. In the low power consumption type information processing apparatus according to the present embodiment, the method for determining the stop release timing of the clock signal supply is different from that of the fifth embodiment. That is, in this embodiment, the supply stop of the clock signal is released when the load data is written in the data cache 107.

  The configuration of the low power consumption type information processing apparatus according to the present embodiment has the same configuration as that of the third embodiment shown in FIG.

  FIG. 19 is a diagram showing a configuration of the information processing core according to the present embodiment. The information processing core 103 shown in this figure is different in the configuration of the clock control logic circuit 233 in the configuration of the information processing core 103 according to the third embodiment shown in FIG. The configuration of the tag unit 236 of the data cache 107 is also different. That is, the tag unit 236 outputs a write signal when load data is written in the data unit 235. In response to the write signal output from the tag unit 236, the clock control logic circuit 233 releases the supply stop of the clock signal.

  When releasing the supply stop of the clock signal when executing the load instruction, the following procedure is performed. Note that the processing until the supply of the clock signal is stopped is the same as that in the third embodiment. It is assumed that the clock signal supplied to the data cache 107 is not stopped while waiting for load data to be written to the data cache 107.

(1) Load data is written to the data cache 107.
(2) The tag unit 236 of the data cache 107 detects that the load data has arrived, and notifies the clock control logic circuit 233 of a write signal.
(3) In response to the write signal notified from the tag unit 236 of the data cache 107, the clock control logic circuit 233 cancels the supply stop of the clock signal and restores the clock signal supply.

  In the above (2), the timing for outputting the write signal is the timing at which the data of the address requested by the load store unit 227 is stored on the line of the data portion 235 of the data cache 107.

  As described above, according to the present embodiment, when a cache miss occurs in the MEM stage at the time of executing the load instruction, the circuit in the information processing core 103 other than the load buffer 229 in the load store unit 227 is transferred to the circuit. The clock signal supply is stopped. As a result, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs.

  In the fifth embodiment, the data read completion time prediction unit 110a predicts the load data read completion time. However, in this embodiment, the clock signal can be generated without providing such a special circuit. The supply stop can be released.

(Embodiment 12)
The following describes Embodiment 12 of the present invention. The low power consumption type information processing apparatus according to the present embodiment is different from the sixth embodiment in the method for determining the stop release timing of the clock signal supply. That is, in the present embodiment, the supply stop of the clock signal is released when the next instruction is written in the instruction cache 105.

  The configuration of the low power consumption information processing apparatus according to the present embodiment is the same as that of the low power consumption information processing apparatus 101 according to Embodiment 3 shown in FIG.

  FIG. 20 is a diagram showing a configuration of the information processing core according to the present embodiment. The information processing core 103 shown in this figure is different in the configuration of the clock control logic circuit 233 from the configuration of the information processing core 103 according to the fourth embodiment shown in FIG. The configuration of the tag unit 238 in the instruction cache 105 is also different. That is, the tag unit 238 outputs a write signal when the next instruction is written in the data unit 237. In response to the write signal output from the tag unit 238, the clock control logic circuit 233 releases the supply stop of the clock signal.

  When releasing the supply of the clock signal at the time of instruction fetch, the following procedure is performed. Note that the processing until the supply of the clock signal is stopped is the same as that in the fourth embodiment. It is assumed that the clock signal supplied to the instruction cache 105 is not stopped while waiting for the next instruction to be written in the instruction cache 105.

(1) The next instruction is written into the instruction cache 105.
(2) The tag unit 238 of the instruction cache 105 detects that the next instruction has arrived, and notifies the clock control logic circuit 233 of a write signal.
(3) In response to the write signal notified from the tag unit 238 of the instruction cache 105, the clock control logic circuit 233 cancels the supply stop of the clock signal and restores the clock signal supply.

  In the above (2), the timing for outputting the write signal is the timing at which the data at the address requested by the instruction fetch unit 221 is stored on the line of the data portion 237 of the instruction cache 105.

  As described above, according to the present embodiment, when a cache miss occurs during instruction fetch, the clock signal supply to the circuits in the information processing core 103 other than the instruction fetch unit 221 is stopped. ing. As a result, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs.

  In the sixth embodiment, the data read completion time prediction unit 110a predicts the load data read completion time. However, in this embodiment, the clock signal can be generated without providing such a special circuit. The supply stop can be released.

(Embodiment 13)
Next, an embodiment 13 of the invention will be described. In this embodiment, when there is no more data to be read by the information processing core, the supply of a clock signal to a predetermined circuit is stopped.

  FIG. 21 is a diagram showing a configuration of the low power consumption information processing apparatus 101 according to the present embodiment.

  Unlike the low power consumption information processing apparatus 101 according to the first embodiment shown in FIG. 3, the low power consumption information processing apparatus 101 is an apparatus that performs burst transfer of data from the DRAM 102 to the data SRAM 106 by DMA transfer. , An information processing core 103, a data SRAM 106, a bus control unit 108, a memory control unit 110, a PLL 111, and a DMA (Direct Memory Access) control unit 241. Constituent elements similar to those of the above-described embodiment are denoted by the same reference numerals. Since the name and function are also the same, the description will not be repeated. The bus control unit 108 includes a data queue 242 for inputting / outputting data using the FIFO method.

  The DMA control unit 241 controls burst transfer from the DRAM 102 to the data SRAM 106 by controlling the data queue 242 and the data SRAM 106.

  The data queue 242 outputs a data queue status signal indicating whether or not the data queue is empty.

  For example, in the low power consumption type information processing apparatus 101, the information processing core 103 decompresses bit stream image data compressed on the MPEG (Moving Picture Experts Group) standard or JPEG (Joint Photographic Experts Group) standard arranged on the DRAM 102. Then, it is assumed that the image data restored to the frame buffer on the DRAM 102 is written back again.

  FIG. 22 is a diagram showing a configuration of the information processing core according to the present embodiment. The information processing core 103 shown in this figure is different from the information processing core 103 according to the first embodiment shown in FIG. 4 except for the load source address space identification logic circuit 232 in the configuration of the clock control logic circuit 233.

  When the clock control logic circuit 233 receives the data queue status signal output from the data queue 242 of the low power consumption information processing apparatus 101, the data queue status signal indicates that the data queue 242 is empty. The supply of the clock signal to the predetermined circuit is stopped, and when the data queue is not empty, the supply stop of the clock signal is released.

  Next, a DMA transfer procedure will be described.

(1) The DMA control unit 241 reads a data string from the continuous area of the transfer source address of the DRAM 102 through the memory control unit 110.
(2) Based on a command from the DMA control unit 241, the bus control unit 108 writes the data string read from the DRAM 102 into the FIFO data queue 242.
(3) The information processing core 103 reads the data string written in the data queue 242 in the order of writing. Where, in particular,
(3-1) When the data queue 242 becomes full, the DMA control unit 241 stops data transfer to the data queue 242 and waits for reading by the information processing core 103.
(3-2) When the data queue 242 becomes empty, a data queue state signal indicating a state where the data queue 242 is empty is transmitted to the clock control logic circuit 233. Since the information processing core 103 cannot read the data string any more, the clock control logic circuit 233 clocks the components belonging to the information processing core 103 after the MEM stage (components that execute processing in the MEM stage and the WB stage). These operations are stopped by stopping the signal supply. Then, when the data queue 242 is not empty, a data queue status signal indicating that the data queue 242 is not empty is transmitted to the clock control logic circuit 233. The clock control logic circuit 233 resumes the clock signal supply, and the information processing core 103 resumes the read operation from the data queue 242.

  Note that when the reading speed by the information processing core 103 is lower than the writing speed by the DMA control unit 241, the data queue 242 tends to be full, and in the opposite case, the data queue 242 tends to be empty.

  As described above, according to the present embodiment, in the DMA transfer, when there is no data to be processed by the information processing core 103, the supply of the clock signal to the components belonging to the MEM stage and thereafter is stopped. As a result, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when a load delay occurs.

(Embodiment 14)
Next, a fourteenth embodiment of the present invention will be described. In this embodiment, the clock supply to a predetermined circuit is stopped at the time of load delay when data is written back from the data cache to the memory.

  FIG. 23 is a diagram showing a configuration of the low power consumption information processing apparatus 101 according to the present embodiment.

  The low power consumption type information processing apparatus 101 is a low power consumption type information processing apparatus that includes a plurality of information processing cores and in which a data cache is provided for each information processing core. Information processing core 103b, third information processing core 103c, first data cache 107a, second data cache 107b, third data cache 107c, bus control unit 108, peripheral circuit 109, and memory control unit 110 And PLL 111.

  The first information processing core 103a, the second information processing core 103b, and the third information processing core 103c have the same configuration as the information processing core 103 according to Embodiment 3 shown in FIG. Note that a clock stop cancellation signal is input from the memory control unit 110 to the clock control logic circuit 233 of each information processing core at a timing described later. The clock control logic circuit 233 releases the supply stop of the clock signal in response to the clock stop release signal.

  The first data cache 107a, the second data cache 107b, and the third data cache 107c have the same configuration as the information processing core 103 according to the third embodiment shown in FIG. The first data cache 107a, the second data cache 107b, and the third data cache 107c are provided between the first information processing core 103a, the second information processing core 103b, the third information processing core 103c, and the DRAM 102, respectively. Yes.

  The bus control unit 108 is connected to the first information processing core 103a to the third information processing core 103c and the first data cache 107a to the third data cache 107c.

  It is assumed that the memory control unit 110 transmits a clock stop cancellation signal at a timing described later.

Other components are the same as those in the above-described embodiment.
In the following cases, the data written in the first data cache 107a to the third data cache 107c must be written back to the DRAM 102.

(A) When data is written from the information processing core to the write-through data cache (b) When data cache consistency is maintained by snoop (c) Line data of the data cache is refilled due to refill due to insufficient line When replacement occurs (d) When line data is purged even in a write-back data cache

  When the data stored in the first data cache 107a is stored in the DRAM 102 in the above situation, a long store completion waiting time is generated as in the execution of the load instruction.

  For example, a case where refill occurs due to execution of a store instruction will be described below. The same applies to the cases (a) to (d) described above. Note that the same applies to storing data stored in the second data cache 107 b in the DRAM 102 and storing data stored in the third data cache 107 c in the DRAM 102.

(1) In the DEC stage, store data is read from the register file 226 as a source operand.
(2) In the EX stage, store data is written to the store buffer 230.
(3) In the MEM stage, store data should be written to the first data cache 107a, but there is no space in the data cache 107 line, and a cache miss occurs. In this case, based on an LRU (Least Recently Used) algorithm or the like, the data cache 107 discharges the old entry in the data cache 107 to the DRAM 102 and writes the store data as a new entry instead.
(4) The load / store unit 227 requests the memory control unit 110 for write access to the entry discharged to the DRAM 102 through the bus control unit 108.
(5) At the same time, the tag unit 236 asserts the cache hit / miss determination logic signal, and the clock control logic circuit 233 stops supplying the clock signal to the circuits in the first information processing core 103a other than the load store unit 227. To do.
(6) The memory control unit 110 writes the source operand to the store destination address of the DRAM 102.
(7) Upon completion of writing to the DRAM 102, the memory control unit 110 sends a clock stop cancellation signal to the first information processing core 103a.
(8) The clock control logic circuit 233 releases the stop of the clock signal supply in response to the clock stop release signal.
(9) The information processing core 103 completes the MEM stage and resumes operation from the WB stage.

  As described above, according to the present embodiment, the supply of the clock signal to the information processing core circuit other than the load / store unit 227 can be stopped when data is written back from the data cache to the DRAM. For this reason, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when waiting for the completion of the store (write back) occurs.

  In this embodiment, the low power consumption type information processing apparatus including a plurality of information processing cores has been described as an example. However, the above (a), (c), and (d) are described in the third embodiment. The method of this embodiment can be applied to a low power consumption type information processing apparatus having one information processing core as shown in FIG.

(Embodiment 15)
Next, an embodiment 15 of the invention will be described. In the fourteenth embodiment, the load delay when data is written back from the data cache to the memory has been described. However, when the information processing core is a low power consumption type information processing apparatus having a store buffer, the store buffer overflows. There is a case. In this case, the oldest data in the store buffer must be written to the memory, causing a load delay. In this embodiment, the supply of a clock signal to a predetermined circuit is stopped at the time of a load delay when data is written back from the store buffer to the memory.

  The configuration of the low power consumption type information processing apparatus and the information processing core according to the present embodiment is the same as the configuration of the low power consumption type information processing apparatus 101 and the information processing core 103 according to the third embodiment shown in FIGS. And the same for each.

  Hereinafter, a data storing operation to the DRAM 102 when the store buffer 230 of the information processing core 103 overflows will be described.

(1) In the DEC stage, store data is read from the register file 226 as a source operand.
(2) In the EX stage, the store buffer 230 overflows as the store data is about to be written into the store buffer 230.
(3) The oldest data in the store buffer 230 is discharged, and the store data is written to a new entry.
(4) The load / store unit 227 requests the memory control unit 110 for write access of the discharged entry to the DRAM 102 via the bus control unit 108.
(5) At the same time, the cache hit / miss determination logic signal is asserted, and the clock control logic circuit 233 stops supplying the clock signal to the circuits in the information processing core 103 other than the load store unit 227.
(6) The memory control unit 110 writes the source operand to the store destination address of the DRAM 102.
(7) Upon completion of writing to the DRAM 102, the memory control unit 110 sends a clock stop cancellation signal 112 to the information processing core 103.
(8) The information processing core 103 completes the MEM stage and resumes operation from the WB stage.

  As described above, according to the present embodiment, the clock signal supply to the circuits in the information processing core 103 other than the load / store unit 227 is stopped at the time of load delay when data is stored from the store buffer 230 to the DRAM 102. be able to. For this reason, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed when waiting for the completion of the store (write back) occurs.

(Embodiment 16)
Next, an embodiment 16 of the invention will be described. In this embodiment, in the pipeline stage, the supply of the clock signal to the circuit operating at the stage where the function stops is stopped.

This embodiment is applicable to all the embodiments described above.
In this embodiment, the supply stop of the clock signal in the pipeline stage is propagated to the subsequent stages. For example, in the cycle following the cycle in which the clock is stopped by the MEM stage, the WB stage stops its function, so that the clocks of the components belonging to the WB stage can also be stopped.

  For each instruction, a clock stop state flag indicating whether or not the supply of the clock signal is stopped is provided, and the clock stop state flag is propagated between successive stages so that the clock signal is not supplied to the useless stage. In addition, pipeline control can be realized. For example, the pipeline control can be realized in the following cases.

(Case 1) When a nop instruction flows into the pipeline, after it flows from IF to DEC stage, if it is determined to be a nop instruction in the DEC stage, the clock stops to the subsequent EX stage, MEM stage, and WB stage. And the supply of the clock signal to the components belonging to the stage is stopped.
(Case 2) A stage that does not operate may appear depending on the type of instruction. In a stage where processing is not performed, supply of the clock signal to the components belonging to the stage is stopped. For example, since no processing is performed in the MEM stage in the operation instruction, the supply of the clock signal to the components belonging to the MEM stage is stopped. Similarly, the supply of clock signals belonging to the store instruction is stopped in the WB stage, and the branch instruction is stopped in the MEM stage and the WB stage.

  As described above, according to the present embodiment, the clock signal to the components belonging to the stage where no processing is executed is stopped. For this reason, the power consumption of the circuit in which the supply of the clock signal is stopped is reduced, and the power consumption can be suppressed.

(Embodiment 17)
Next, an embodiment 17 of the invention will be described.

  Up to now, various embodiments have been described in the first to sixteenth embodiments regarding the clock supply stop. However, it is possible to cut off the power supply to some circuits of the information processing core 103 using the same concept. . When the power supply is shut off, unlike the clock signal supply stop, the volatile memory element (sequential circuit) can store the state in the normal operation state before the stop, that is, can return to the state before the stop. Disappear. Therefore, the range in which the power cut-off can be applied is usually narrower than the supply stop of the clock signal, and is limited to a nonvolatile storage device such as a flash memory and its peripheral circuit (combination circuit).

(Embodiment 18)
Next, an embodiment 18 of the present invention will be described.

  When implemented as a semiconductor product, a low power consumption information processing apparatus that implements the functions described in the various embodiments is referred to as SoC or system LSI. These SoCs are mounted on various portable information devices and realize long-time operation of these devices using batteries. Examples of the portable information device include a mobile phone, a portable game machine, a video camera, a still image camera, a PDA (Personal Digital Assistant), a portable PC (Personal Computer), and an electronic dictionary. Information equipment with a strong demand for low power consumption includes in-car products such as car navigation.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The low power consumption type information processing apparatus according to the present invention is incorporated in a digital information device, a portable communication apparatus, etc., and is useful as a control microprocessor or microcontroller driven by a battery. It can also be applied to uses such as an embedded DMA control LSI and DSP.

It is a figure for demonstrating each process step in a pipeline process. It is a figure which shows the notation method of a bus signal line. It is a figure which shows the structure of the system containing the low power consumption type information processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of the information processing core which concerns on 1 of this invention. It is a figure for demonstrating clock gating. It is a figure which shows the structure of the information processing core which concerns on 2 of this invention. It is a figure which shows the structure of the system containing the low power consumption type information processing apparatus which concerns on 3 of this invention. It is a figure which shows the structure of the information processing core which concerns on 3 of this invention. It is a figure which shows the structure of the information processing core which concerns on 4 of this invention. It is a structure of the system containing the low power consumption type information processing apparatus concerning 5 of this invention. It is a figure which shows the structure of the information processing core which concerns on 5 of this invention. It is a figure which shows the structure of the information processing core which concerns on 6 of this invention. It is a figure which shows the structure of the information processing core which concerns on 7 of this invention. It is a figure which shows the structure of the information processing core which concerns on 8 of this invention. It is a figure which shows the structure of an instruction fetch unit. It is a figure which shows the structure of the information processing core which concerns on 9 of this invention. FIG. 6 is a state transition diagram between a normal operation mode and a clock stop mode. It is a figure which shows the structure of the information processing core which concerns on 10 of this invention. It is a figure which shows the structure of the information processing core which concerns on 11 of this invention. It is a figure which shows the structure of the information processing core which concerns on 12 of this invention. It is a figure which shows the structure of the low power consumption type | mold information processing apparatus which concerns on 13 of this invention. It is a figure which shows the structure of the information processing core which concerns on 13 of this invention. It is a figure which shows the structure of the low power consumption type information processing apparatus which concerns on Embodiment 14 of this invention.

Explanation of symbols

101 Low power consumption information processing apparatus 102 DRAM
103 Information processing core 103a First information processing core 103b Second information processing core 103c Third information processing core 104 Instruction ROM
105 Instruction cache 106 Data SRAM
107 data cache 107a first data cache 107b second data cache 107c third data cache 108 bus control unit 109 peripheral circuit 110 memory control unit 110a completion time prediction unit 111 PLL
112 Clock stop release signal 221 Instruction fetch unit 222 Instruction decode unit 223 Operand address calculation unit 224 Instruction address calculation unit 225 Instruction execution unit 226 Register file 227 Load store unit 228 Path selector 229 Load buffer 230 Store buffer 231 Program counter 232 Load source Address space identification logic circuit 233 Clock control logic circuit 235, 237 Data section 236, 238 Tag section 239 Instruction buffer 239a Instruction register 239c Program counter 239b Incrementer 240 Interrupt control section 241 DMA control section 242 Data queue 252 Fetch address space identification logic circuit 261 Cash controller 301 D-FF
303 Buffer 305 AND gate

Claims (26)

Data loading means for loading data from main memory;
Information processing means for executing predetermined processing with reference to data loaded by the data loading means;
A clock generating means for generating a clock signal having a frequency at which the data loading means and the information processing means can operate, and supplying the clock signal to the data loading means and the information processing means;
Clock control means for controlling supply and stop of the clock signal from the clock generating means to the information processing means,
The clock control unit is configured to transfer the data from the clock generation unit to the information processing unit over a part or all of the period from when the data loading unit starts the data loading operation until the data is acquired. An information processing apparatus characterized by stopping supply of a clock signal. The main memory requires a predetermined time or more to load data,
The information processing apparatus further includes:
A sub memory capable of loading data within the predetermined time; and
Load source address space identification logic means for determining which address space of the main memory and the sub memory belongs to the address where the data loaded by the data load means is stored,
The clock control means, when it is determined that the address belongs to the address space of the main memory, part or all of the period from the start of the data load operation to the acquisition of data The information processing apparatus according to claim 1, wherein the supply of the clock signal from the clock generation unit to the information processing unit is stopped over a period of time. The information processing apparatus further includes:
Main memory control means for controlling reading of data from the main memory in response to a data load request from the data load means for the main memory;
A data cache that is accessible at a higher speed than the main memory and temporarily holds a copy of the data read from the main memory;
When loading data from the main memory, if the data to be loaded is held in the data cache, the data loading means loads the data from the data cache,
When the data load means tries to load data from the main memory, if the data load means makes a miss-hit in the read access of the data from the data cache, the main memory control means loads the data from the main memory. The information processing apparatus according to claim 1, wherein the clock control unit stops supply of a clock signal to the information processing unit. When the data load means stores data read from the main memory in the data cache when the data load means tries to load data from the data cache and makes a miss hit, the information processing The information processing apparatus according to claim 3, wherein the supply of the clock signal to the means is resumed. The clock control means stops supply of a clock signal to a part or all of the constituent circuits of the information processing means when data is written back from the data cache to the main memory. The information processing apparatus described in 1. The information processing apparatus further includes:
In response to a data load request from the data load means to the main memory, the main memory control means for controlling reading of data from the main memory,
Further, the main memory control means is specific to the main memory after the main memory control means makes a data read request to the main memory when the data load means loads data from the main memory. Predict the time when the access time elapses, and output a clock stop release signal a predetermined time before the predicted time,
The said clock control means restarts supply of the said clock signal to the said information processing means in response to the said clock stop cancellation | release signal output from the said main memory control means. Information processing device. The information processing apparatus further includes:
In response to a data load request from the data load means to the main memory, the main memory control means for controlling reading of data from the main memory,
The main memory control means further outputs an output from the main memory after the main memory control means makes a data read request to the main memory when the data load means loads data from the main memory. Based on the output timing of the response signal to be predicted data read completion time from the main memory, output a clock stop release signal a predetermined time before the predicted data read completion time,
The said clock control means restarts supply of the said clock signal to the said information processing means in response to the said clock stop cancellation | release signal output from the said main memory control means. Information processing device. The information processing apparatus further includes:
Load buffer means for temporarily holding data read from the main memory;
The clock control means, when the data load means tries to load data from the main memory, a period from the start of the load operation until the data read from the main memory is stored in the load buffer means The information processing apparatus according to claim 1, wherein the supply of the clock signal is stopped over part or all of the information processing apparatus. The information processing apparatus further includes:
DMA (Direct Memory Access) control means for controlling data transfer from the main memory to the load buffer means,
The load buffer means functions as an intermediate temporary buffer for holding data in a first-in first-out manner for data transfer from the main memory to the information processing means,
The clock control unit stops supply of a clock signal to a part or all of the constituent circuits of the information processing unit over a part or all of a period in which no data is stored in the load buffer unit. The information processing apparatus according to claim 8. The information processing apparatus further includes:
Main memory control means for controlling reading of data from the main memory in response to a data load request from the data load means for the main memory;
Interrupt control means for controlling the operation of the clock control means in response to an interrupt signal,
Further, the main memory control means is specific to the main memory after the main memory control means makes a data read request to the main memory when the data load means loads data from the main memory. Predict the time when the access time elapses, and output a clock stop release signal a predetermined time before the predicted time,
The interrupt control means accepts the clock stop release signal as an interrupt signal, notifies the clock control means,
The information processing apparatus according to claim 1, wherein the clock control unit restarts supply of the clock signal to the information processing unit in response to the notification. The information processing apparatus further includes:
Store buffer means for temporarily holding data to be stored in the main memory;
Store means for storing the data held by the store buffer means in the main memory,
When the store means tries to store the data held by the store buffer means in the main memory, the clock control means is a part of a period from the start of the store operation until the data is written to the main memory. The information processing apparatus according to claim 1, wherein the supply of the clock signal is stopped over the whole. The information processing means has a processing structure based on a pipeline type processing method,
The clock control means, for the pipeline stage to which the process for which the clock supply is stopped belongs, in the cycle next to the cycle in which the clock supply is stopped, the information processing constituting the stage of the next stage of the pipeline stage The information processing apparatus according to claim 1, wherein the clock supply to the circuit of the means is stopped. An instruction fetching means for fetching an instruction from the main memory;
Information processing means for executing the instruction fetched by the instruction fetch means;
A clock generating means for generating a clock signal of a frequency at which the instruction fetch means and the information processing means can operate, and supplying the clock signal to the instruction fetch means and the information processing means;
Clock control means for controlling supply and stop of the clock signal from the clock generating means to the information processing means,
The clock control unit is configured to transfer the clock from the clock generation unit to the information processing unit over a part or all of a period from when the instruction fetch unit starts an instruction fetch operation until the instruction is acquired. An information processing apparatus characterized by stopping supply of a clock signal. The main memory requires a predetermined time or more to fetch an instruction,
The information processing apparatus further includes:
A sub memory capable of loading data within the predetermined time; and
Fetch address space identification logic means for determining which address space of the main memory and the sub memory belongs to an address in which an instruction fetched by the instruction fetch means is stored;
When the clock control unit determines that the address belongs to the address space of the main memory, a part or all of the period from when the instruction fetch unit starts the instruction fetch operation until the instruction is acquired The information processing apparatus according to claim 13, wherein supply of the clock signal from the clock generation unit to the information processing unit is stopped over a period of time. The information processing apparatus further includes:
Main memory control means for controlling reading of an instruction from the main memory in response to an instruction fetch request from the instruction fetch means for the main memory;
An instruction cache that is accessible at a higher speed than the main memory and temporarily holds a copy of the instruction read from the main memory;
When the instruction fetch unit attempts to fetch an instruction from the main memory, if there is a miss hit in the read access of the instruction from the instruction cache, the main memory control unit fetches the instruction from the main memory. The information processing apparatus according to claim 13, wherein the clock control unit stops the clock supply to the information processing unit. When the instruction fetch unit tries to fetch an instruction from the instruction cache and makes a miss hit, the clock control unit stores the instruction read from the main memory in the instruction cache. The information processing apparatus according to claim 15, wherein supply of a clock signal to the computer is resumed. The information processing apparatus further includes:
In response to an instruction fetch request from the instruction fetch means for the main memory, the main memory control means for controlling reading of instructions from the main memory,
The main memory further includes an access unique to the main memory after the main memory control unit makes a request to read the instruction to the main memory when the instruction fetch unit fetches an instruction from the main memory. Predict the time when the time elapses, output a clock stop release signal a predetermined time before the predicted time,
The clock control means restarts the supply of the clock signal to the information processing means in response to the clock stop cancellation signal output from the main memory control means. Information processing device. The information processing apparatus further includes:
In response to an instruction fetch request from the instruction fetch means for the main memory, the main memory control means for controlling reading of instructions from the main memory,
The main memory control means further outputs an output from the main memory after the main memory control means makes a read request to the main memory when the instruction fetch means fetches an instruction from the main memory. Based on the output timing of the response signal to be predicted the instruction read completion time from the main memory, output a clock stop release signal a predetermined time before the predicted instruction read completion time,
The clock control means restarts the supply of the clock signal to the information processing means in response to the clock stop cancellation signal output from the main memory control means. Information processing device. The information processing apparatus further includes:
An instruction buffer means for temporarily holding an instruction read from the main memory;
When the instruction fetch attempts to fetch an instruction from the main memory, the clock control means has a period from the start of the fetch operation until the instruction read from the main memory is stored in the instruction buffer means. The information processing apparatus according to claim 13, wherein the supply of the clock signal is stopped partly or entirely. The information processing apparatus further includes:
Main memory control means for controlling reading of an instruction from the main memory in response to an instruction fetch request from the instruction fetch means for the main memory;
Interrupt control means for controlling the operation of the clock control means in response to an interrupt signal,
Further, the main memory control means is specific to the main memory after the main memory control means makes a read request of the instruction to the main memory when the instruction fetch means fetches an instruction from the main memory. Predict the time when the access time elapses, and output a clock stop release signal a predetermined time before the predicted time,
The interrupt control means accepts the clock stop release signal as an interrupt signal, notifies the clock control means,
The information processing apparatus according to claim 13, wherein the clock control unit restarts the supply of the clock signal to the information processing unit in response to the notification. Data loading means for loading data from main memory;
Information processing means for executing predetermined processing with reference to data loaded by the data loading means;
A clock generating means for generating a clock signal having a frequency at which the data loading means and the information processing means can operate, and supplying the clock signal to the data loading means and the information processing means;
Clock control means for controlling supply and stop of the clock signal from the clock generating means to the information processing means;
A data cache that is accessible at a higher speed than the main memory and temporarily holds a copy of the data read from the main memory;
The clock control means stops the supply of a clock signal to a part or all of the constituent circuits of the information processing means when data is written back from the data cache to the main memory. . Data loading means for loading data from main memory;
Information processing means for executing predetermined processing with reference to data loaded by the data loading means;
A clock generating means for generating a clock signal having a frequency at which the data loading means and the information processing means can operate, and supplying the clock signal to the data loading means and the information processing means;
Clock control means for controlling supply and stop of the clock signal from the clock generating means to the information processing means;
Load buffer means for temporarily holding data read from the main memory;
DMA control means for controlling data transfer from the main memory to the load buffer means,
The load buffer means functions as an intermediate temporary buffer for holding data in a first-in first-out manner for data transfer from the main memory to the information processing means,
The clock control unit stops supply of a clock signal to a part or all of the constituent circuits of the information processing unit over a part or all of a period in which no data is stored in the load buffer unit. An information processing apparatus characterized by that. Data loading means for loading data from main memory;
Information processing means for executing predetermined processing with reference to data loaded by the data loading means;
A clock generating means for generating a clock signal having a frequency at which the data loading means and the information processing means can operate, and supplying the clock signal to the data loading means and the information processing means;
Clock control means for controlling supply and stop of the clock signal from the clock generating means to the information processing means;
Store buffer means for temporarily holding data to be stored in the main memory;
Store means for storing the data held by the store buffer means in the main storage device,
When the store means tries to store the data held by the store buffer means in the main memory, the clock control means is a part of a period from the start of the store operation until the data is written to the main memory. Alternatively, the information processing apparatus is characterized in that the supply of the clock signal is stopped throughout. Data loading means for loading data from main memory;
Information processing means having a processing structure based on a pipeline type processing method for executing predetermined processing with reference to data loaded by the data loading means;
A clock generating means for generating a clock signal having a frequency at which the data loading means and the information processing means can operate, and supplying the clock signal to the data loading means and the information processing means;
Clock control means for controlling supply and stop of the clock signal from the clock generating means to the information processing means,
The clock control means, for the pipeline stage to which the process for which the clock supply is stopped belongs, in the cycle next to the cycle in which the clock supply is stopped, the information processing constituting the stage of the next stage of the pipeline stage An information processing apparatus characterized by stopping clock supply to the circuit of the means. The information processing apparatus includes power supply cutoff means for cutting off power supply to the information processing apparatus instead of the clock control means,
25. The power supply cut-off means cuts off power supply to the information processing apparatus during a period in which the clock control means stops the supply of a clock signal to the information processing means. The information processing apparatus according to claim 1. An information device comprising the information processing apparatus according to any one of claims 1 to 25.

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