JP2006309734A - Arithmetic processing unit and electronic device using arithmetic processing unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CPU which raises processing speed, and also realizes low power consumption simultaneously in a CPU mounted with a cache memory. <P>SOLUTION: In a CPU mounted with multiple sets of associative cache memory, the CPU is provided which has a means to monitor a cache memory area which does not contribute to improvement of processing performance of the CPU and can dynamically change it into an idle state according to the operating status. The CPU of high performance and low power consumption can be provided with such a configuration. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an arithmetic processing apparatus equipped with an associative cache memory composed of a plurality of sets. In particular, the present invention relates to an arithmetic processing device capable of changing a predetermined set during operation according to an operation state.

  Almost all arithmetic processing devices represented by the current CPU (Central Processing Unit) have an architecture called a stored program system. In this stored program method, instructions processed by the CPU and data necessary for the processing are stored in the memory, and the processing of the CPU proceeds by sequentially reading the data in the memory. Therefore, in a system equipped with a CPU, the memory access speed is very important for determining the performance of the entire system. For this reason, a cache memory is installed in many CPUs.

  The cache memory is a high-speed memory that copies and stores a part of the contents of the main memory (external memory) where data writing and reading are slow. A case where data required by the CPU exists in the cache memory is called a cache hit. On the contrary, the case where the data required by the CPU does not exist in the cache memory is called a cache miss. For such cache performance, Non-Patent Document 1 can be referred to.

When a cache miss occurs, access to the low-speed main memory occurs. Therefore, the higher the cache hit probability (cache hit rate), that is, the lower the cache miss probability (cache miss rate), the faster the CPU can perform processing. That is, in a system equipped with a CPU, the performance of the entire system can be improved.
J. et al. Hennessy, D.C. Co-authored by Patterson, Computer Architecture, Nikkei Business Publications, 418, 419 pages

  Generally, a cache memory with a larger capacity has fewer cache misses. Therefore, the CPU processing speed can be improved by increasing the cache memory capacity. However, in the CPU, the cache memory is also one of the blocks with the highest power consumption. Therefore, there is a need for a cache memory that increases the capacity to improve the processing speed of the CPU and at the same time realizes low power consumption.

  The cache memory of the CPU is composed of a tag memory for storing a copy source address or a part of the content copied from the main memory, and a data memory for copying the content stored at the address. During the read operation of the cache memory, the address is compared with the data (tag data) stored in the tag memory and the copied data (copy data) is read simultaneously. Here, the case where the address and the tag data match is a cache hit, and the read copy data is used for the processing of the CPU. On the other hand, when the address and the tag data do not match, a cache miss occurs, and the read copy data becomes invalid, and the main memory is accessed again to acquire data necessary for the CPU processing.

  Typical configurations of the cache memory include a full set associative method, a direct map method, and an n-way set associative method. Each method will be briefly described below.

  In the full set associative method, all bits of the copy source address are stored in the tag memory. During the read operation of the cache memory, the tag data of all the rows (entries) of the tag memory are read, and the respective tag data and addresses are compared. If they match, the copy data of the corresponding entry is validated. Although data can be copied from any address in the main memory, the comparison circuit becomes complicated depending on the capacity of the cache memory, so this is an effective system for a small number of entries, that is, a small capacity cache memory.

  In the direct map method, some bits of the address in the main memory are stored in the tag memory. Normally, the upper bits of the address are stored. The tag memory entry that can be stored is specified by the lower bits of the address. When the cache memory is read, the tag data read only from the tag memory entry specified by the lower bit of the address is compared with the upper bit of the address, and if they match, the copy data of the corresponding entry is validated. To do. Although the comparison circuit can be simplified, the cache hit rate decreases when accesses to addresses having the same lower order bits are frequently performed. That is, it is effective when the data required by the CPU has locality, and the performance decreases when a large-scale program is executed.

  The n-way set associative system is composed of a set of n (normally 2, 4, and 8) sets each including a tag memory and a data memory. Some bits of the address in the main memory are stored in either set of tag memories. Normally, the upper bits of the address are stored. The tag memory entry that can be stored is specified by the lower bits of the address. In the cache memory read operation, the tag data read only from the tag memory entry specified by the lower bit of the address is compared with the upper bits of the address in all sets of tag memories. Validate the copy data of the entry in the corresponding set. Although the comparison circuit is slightly complicated, the cache hit rate does not decrease even when accesses to addresses having the same low-order bits are frequently performed.

  Here, details of an n-way set associative cache memory that is generally used as a cache memory of a high-performance CPU will be described. For the sake of simplicity, an outline of two sets of associative cache memories is shown.

  The configuration of the cache memory is shown in FIG. Here, the cache memory 101 includes a first set 102, a second set 103, a tag comparison circuit 104, and a data selection circuit 105. The first set 102 includes a first tag memory 106 and a first data memory 107. The second set 103 includes a second tag memory 108 and a second data memory 109. The tag comparison circuit 104 includes a first comparison circuit 110 and a second comparison circuit 111.

  Here, it is assumed that a partial copy of the contents in the main memory is stored in the cache memory. That is, the upper bits of the address are stored in the entry of either the first tag memory 106 or the second tag memory 108 specified by the lower bits of the address for the contents at a specific address in the main memory. Yes.

  Further, when the upper bit of the address is stored in the first tag memory 106, it is stored in the entry specified by the lower bit of the address in the first data memory 107 or in the second tag memory 108. In this case, it is assumed that the content (copy data) of the address in the main memory is stored in the entry specified by the lower bit of the address in the second data memory 109.

  The operation of the cache memory will be described. First, the cache memory receives the address 112 of the main memory where the next data required by the CPU is stored.

  Secondly, the upper bit (address upper bit) 113 of the address 112 is sent to the tag comparison circuit 104, and the lower bit (address lower bit) 114 of the address 112 is sent to the first set 102 and the second set 103. In the first set 102, the lower address bits 114 are decoded, and the first tag data 115 and the first copy data 116 stored in the corresponding entries of the first tag memory 106 and the first data memory 107, respectively. Is output. Similarly, the second tag data 117 and the second copy data 118 are output from the second set 103.

  Third, the first comparison circuit 110 compares the address upper bits 113 with the first tag data 115 and outputs a first tag hit signal 119. Here, the first tag hit signal 119 is “1” in the case of coincidence and “0” in the case of non-coincidence. Similarly, the second comparison circuit 111 compares the address upper bits 113 with the second tag data 117 and outputs a second tag hit signal 120.

  Finally, in the data selection circuit 105, when the first tag hit signal 119 is “1”, the first copy data 116 is obtained. When the second tag hit signal 120 is “1”, the second copy data is obtained. 118 is output as the cache data 121. Further, a cache hit signal 122 that is “1” when either the first tag hit signal 119 or the second tag hit signal 120 is “1” is output.

  When the cache hit signal 122 is “1”, the CPU can use the cache data 121 as the same valid data as the contents stored at the address 112 of the main memory. On the other hand, when the cache hit signal 122 is “0”, it is necessary to access the main memory and acquire necessary data because of a cache miss.

  In the case of such a two-way set associative cache memory, at least one of the first copy data 116 and the second copy data 118 is not always used. That is, the current required for reading is always wasted as wasted power consumption. In an n-way set associative cache memory, as the number of sets increases, the consumed power increases in exchange for improved processing performance.

  The present invention has been made in view of the above-described problems. In an arithmetic processing unit equipped with an n-way set associative cache memory, the operating set is dynamically changed in accordance with the operating state, thereby achieving high performance. An arithmetic processing unit with low power consumption is provided. In the present invention, the arithmetic processing device includes a CPU and a DSP (Digital Signal Processor).

  The configuration of the present invention disclosed in the present specification is an arithmetic processing device equipped with an associative cache memory, and the cache memory is composed of at least one set, and each set includes a data memory, a tag memory, , Each having a means for transitioning between two states of an operation state and a stop state, and the arithmetic processing unit includes: the number of accesses to the cache memory; the number of cache hits; the number of tag hits in each set; And a means for counting the cache hit rate obtained by dividing the number of cache hits by the number of accesses for an arbitrary period.

  In the above configuration, the arithmetic processing unit shifts one of the data memory and the tag memory in the operating state to the stopped state according to the result of comparing the cache hit rate and the reference value of the arbitrarily set hit rate. Means may be included. Note that in this specification, transition includes a reversible change. Specifically, the transition includes not only the change from the operating state to the stopped state but also the change from the stopped state to the operating state.

  In the above configuration, the arithmetic processing unit sets one of the stopped data memory and the tag memory to the operating state according to the result of comparing the cache hit rate with the arbitrarily set hit rate reference value. Means for transition may be included.

  In the above configuration, the arithmetic processing unit may include means for causing at least one of the sets in the operating state to transition to the stopped state for each time specified by an arbitrarily set time reference value. .

  In the above configuration, the arithmetic processing unit has means for causing the set with the smallest number of tag hits among the sets in the operating state to transition to the stopped state for each time specified by the arbitrarily set time reference value. You may do it.

  Further, in the above configuration, the arithmetic processing unit may include means for causing at least one of the sets in the stopped state to transition to the operating state for each time defined by an arbitrarily set time reference value. good.

  In the above configuration, the arithmetic processing unit sets the smallest number of tag hits among the sets in the operating state according to the result of comparing the cache hit rate and the arbitrarily set hit rate reference value. There may be provided means for transitioning to a stop state.

  In the above configuration, the arithmetic processing unit causes at least one of the sets in the operating state to transition to the stopped state in accordance with the result of comparing the cache hit rate and the reference value of the arbitrarily set hit rate. Means may be included.

  In the above configuration, the arithmetic processing unit sets at least one of the sets in the stopped state to the operating state according to the result of comparing the cache hit rate and the arbitrarily set hit rate reference value. Means for transition may be included.

  Further, in the above configuration, the arithmetic processing unit performs an operation according to a result of comparing the cache hit rate with an arbitrarily set reference value of the hit rate after the operation of changing the set in the operating state to the stopped state. It is desirable to have means for transitioning the set that has been transitioned to the stop state in (1) to the operational state again.

  Further, in the above configuration, the arithmetic processing unit performs an operation according to a result of comparing the cache hit rate with an arbitrarily set reference value of the hit rate after the operation of changing the set in the stopped state to the operating state. It is desirable to have a means for transitioning the set that has been transitioned to the operating state in step 1 again to the stopped state.

  Further, in the above configuration, the arithmetic processing unit controls an operation for transitioning the set in the operating state to the stopped state, or an operation for transitioning the set in the stopped state to the operating state by an instruction executed by the arithmetic processing device. It is desirable to have

  Further, in the above configuration, the arithmetic processing device performs an operation for transitioning the set in the operating state to the stopped state, or an operation for transitioning the set in the stopped state to the operating state, and a control circuit mounted on the arithmetic processing device; It is desirable to have a means for controlling by an instruction executed by the arithmetic processing unit.

  In the above configuration, it is desirable that the arithmetic processing device has means for changing the time reference value and the hit rate reference value during operation of the arithmetic processing device.

  In the above configuration, the arithmetic processing unit has means for determining a reference value for a time suitable for each program to be executed and a reference value for the hit rate. It is desirable to use a value suitable for each program.

An example of a more detailed configuration of the present invention includes a cache memory having at least one set including a data memory and a tag memory, a counting circuit, and a register. The number of accesses to the cache, the number of cache hits in the cache memory, the number of tag hits in the tag memory, and the cache hit rate obtained by dividing the number of cache hits by the number of accesses are counted. Is shifted to an operating state or a stopped state.
That is, one of the data memory and the tag memory is changed from the operating state to the stopped state according to the comparison result between the cache hit rate and the reference value of the first hit rate.
A configuration may be adopted in which one of the data memory and the tag memory is changed from the operating state to the stopped state for each first time reference value by the register.

Another example of a more detailed configuration of the present invention includes a cache memory having a plurality of sets each including a data memory and a tag memory, a counting circuit, and a register. Counts the number of accesses to the cache memory, the number of cache hits in the cache memory, the number of tag hits in the tag memory of at least one set of a plurality of sets, and the cache hit rate obtained by dividing the number of cache hits by the number of accesses The at least one set is transited to an operating state or a stopped state by a register.
That is, at least one set is changed from the operating state to the stopped state according to the comparison result between the cache hit rate and the reference value of the first hit rate.
A configuration may be adopted in which at least one set is changed from the operating state to the stopped state for each reference value of the first time by the register. Further, for each reference value for the first time, a set with the smallest number of tag hits out of at least one set may be changed from the operating state to the stopped state.

  Note that examples of means for transitioning between the two states of the operation state and the stop state include a set control circuit having a counting circuit, a condition determination circuit, a register, and the like. More specifically, the operation state and the stop state can be changed by a set control signal from the set control circuit. Further, the time reference value and the hit rate reference value are changed by rewriting the register value by the arithmetic processing unit. It is preferable to use a reference value suitable for each program to be executed.

  In the above configuration, the stopped state may be a state in which the precharge operation that is performed when data stored in the data memory and the tag memory is read is not performed. In the above configuration, the stopped state may be a state in which the power supply voltage is not supplied to the data memory and the tag memory.

  In the above structure, the arithmetic processing unit includes a thin film transistor. The thin film transistor uses a semiconductor thin film formed over a substrate having an insulating surface as an active layer. The substrate having an insulating surface is a glass substrate. Further, any of a quartz substrate, a plastic substrate, and an SOI substrate may be used.

  It is also effective to incorporate the CPU having the above configuration into an electronic device.

  According to the present invention, in an associative cache memory, it is possible to monitor a cache memory area that does not contribute to an improvement in processing performance of an arithmetic processing device and dynamically make it stop appropriately according to a program executed by the arithmetic processing device. . That is, it is possible to reduce wasteful power consumption due to data reading from the cache memory while maintaining the processing performance of the arithmetic processing unit. By mounting such an associative cache memory, a high performance and low power consumption CPU can be provided.

  Hereinafter, embodiments and examples of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of the embodiments and examples.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

  Note that the same portions or portions having similar functions are denoted by the same reference symbols throughout the drawings for describing the embodiments and examples, and the repetitive description thereof is omitted.

  In FIG. 2, the CPU 201 includes a cache memory 202, a control unit 203, and a calculation unit 204. The control unit 203 includes a set control circuit 205. The set control circuit 205 includes a counting circuit 206, a condition determination circuit 207, a register 208, and the like. The cache memory 202 outputs the cache data 121 to the address 112 issued from the control unit 203. At the same time, a hit signal 209 is output. The cache memory 202 is controlled by a set control signal 210 that is an output signal from the control unit 203.

  For example, the cache memory 202 can be configured as shown in FIG. However, a set control signal 210 from the set control circuit 205 can make a transition to an operating state or a stopped state for each set. That is, FIG. 3 shows a configuration in which means for changing to an operating state or a stopped state for each set is added to the configuration of FIG.

  In FIG. 3, the operation of the tag memory and the data memory in the set (stop set) transitioning to the stop state is stopped by the set control signal 210. Specifically, the write signal and the read signal to the tag memory and the data memory are deactivated. Usually, the data signal line needs to be precharged for reading from the memory. Most of the power consumption of the memory is due to this precharge. Therefore, by disabling the read signal, the power consumption in each set is greatly reduced. Further, power consumption can be further reduced by cutting off the power supply voltage supplied to each set.

  It is also effective to deactivate the tag comparison circuit 104 for the stop set by the set control signal 210. Specifically, for example, the tag hit signal is always set to “0”. As a result, the data selection circuit 105 does not have to worry about erroneously selecting stop set data. Note that the first tag hit signal 119, the second tag hit signal 120, and the cache hit signal 122 correspond to the hit signal 209.

  The set control circuit 205 in FIG. 2 includes a counting circuit 206 that counts a cache hit rate and the like, a condition determination circuit 207, and a register 208.

  The counting circuit 206 can count the number of accesses to the cache memory, the number of cache hits, the number of tag hits for each set, and the like. By dividing the number of cache hits by the number of accesses, the cache hit rate can be counted. Further, the tag hit rate for each set can be counted by dividing the number of tag hits for each set by the number of accesses.

  The condition determination circuit 207 determines a set to be changed to the stop state or the operation state by a predetermined algorithm according to the cache hit rate or the like. The algorithm for determining the state for each set from the cache hit rate is a very important item for determining the performance of the CPU equipped with the cache memory in the present invention. Various methods can be considered according to the specific application of the CPU in the present invention.

  The register 208 is used for setting the counting condition in the counting circuit 206 and the parameter setting in the condition determining circuit 207.

  With the above configuration, it is possible to provide a high-performance and low-power-consumption CPU equipped with a cache memory that can select optimal performance and power consumption in accordance with the operation state.

  In addition, the CPU in this embodiment includes a thin film transistor that uses a semiconductor thin film formed over a substrate having an insulating surface such as a glass substrate, a quartz substrate, or a plastic substrate as an active layer, so that high performance and low consumption can be obtained. A power CPU can be provided at a lower weight and at a lower cost.

  Furthermore, by configuring the electronic device using the CPU in this embodiment, a high-performance and low-power consumption electronic device can be provided at a lower weight and at a lower cost.

  In this embodiment, an algorithm for determining a state for each set from a cache hit rate, which is not described in detail in the embodiment, for a CPU equipped with a cache memory according to the present invention will be described.

  However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment.

  The algorithm in the present embodiment will be described with reference to the flowchart shown in FIG. The cache hit rate in a access is counted as an arbitrary number (cache hit rate count 501). This cache hit rate is compared with b% which is a preset condition (condition determination 502), and an arbitrary set is changed from the operating state to the stopped state (set stop processing 503) according to the result. Thereafter, the cache hit rate in an arbitrary period is counted (cache hit rate count 504), and this is defined as c%. c% is compared with b% which is a preset condition (condition determination 505), and it is determined whether or not to return to the state before transition according to the result (set restoration processing 506). This algorithm corresponds to determining the number of sets while verifying whether the cache hit rate can be maintained even with a smaller number of sets. By reducing the number of sets, power consumption in the semiconductor device can be reduced. The algorithm described here can be executed by software (program) or hardware.

  The case where this operation is performed by hardware is shown below. The count circuit counts the cache hit rate in a accesses and stores it in a register. The cache hit rate and b% which is a preset condition are compared by a condition discriminating circuit, and a set control signal is changed according to the result, thereby changing an arbitrary set from an operating state to a stopped state. Let Thereafter, the cache hit rate in an arbitrary period is counted by a counting circuit, and this is set as c%. The condition discriminating circuit compares c% with b% which is a preset condition, and determines whether or not to return to the state before the transition according to the result. In this way, power consumption in the semiconductor device can be reduced.

  Here, as a condition for transitioning an arbitrary set to the stopped state, it is effective that the cache hit rate is b% or more. This is effective when the cache memory is functioning very effectively, and corresponds to the case where the program size is very small and almost all programs can be copied from the main memory to the cache memory.

  It is also effective to set the cache hit rate to b% or less as a condition for transitioning an arbitrary set to the stopped state. This is effective when the cache memory is hardly functioning, and corresponds to a case where data to be processed is scattered on the main memory although the program size is small. In this case, if the program is copied to the cache memory, it is considered that the CPU processing speed hardly changes.

  It is also effective to combine the above two types of conditions. In this case, since it can be determined whether or not to make a transition to the stop state more precisely, it is effective in reducing power consumption.

  In the algorithm in this embodiment, the parameters a, b, and c can be set as fixed values, but it is desirable to update them appropriately while observing the cache hit rate. This is because the optimum reference value depends on the program that is actually executed by the CPU. These values are updated by the CPU rewriting the register values.

  Furthermore, it is also effective to save optimal a, b, and c for a program that has been executed once, and set it to the value at the next execution. This is particularly effective when the CPU is used in a system that can execute various programs such as a personal computer. Note that the register 208 in FIG. 2 is effective in storing these parameters, a, b, and c.

  Further, by counting the tag hit rate for each set in a 'accesses as an arbitrary number of times (tag hit rate count 507) and determining a set to be shifted to the stopped state, more optimal control can be performed. . By stopping a set with a low tag hit rate, it is considered that the decrease in the cache hit rate is slight before and after the set stop, and the stop set can be controlled effectively. Therefore, power consumption can be more precisely reduced.

  With the above-described configuration, it is possible to provide a high-performance and low-power-consumption CPU equipped with a cache memory that can select optimal performance and power consumption according to the operation state.

  Note that the CPU in this embodiment is composed of a thin film transistor using a semiconductor thin film formed on a substrate having an insulating surface such as a glass substrate, a quartz substrate, or a plastic substrate as an active layer, thereby achieving high performance and low power consumption. CPU can be provided at a lower weight and at a lower cost.

  Furthermore, by configuring an electronic device using the CPU in this embodiment, a high-performance and low power consumption electronic device can be provided at a lower weight and at a lower cost.

  This embodiment can be implemented in combination with the best mode for carrying out the invention.

  In the present embodiment, an algorithm different from the algorithm for determining a stop set from the cache hit rate described in the first embodiment will be described for a CPU equipped with a cache memory according to the present invention.

  However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment.

  The algorithm in the present embodiment will be described with reference to a flowchart shown in FIG. An appropriate time interval d seconds is counted (time count 601), an arbitrary set is changed from the operating state to the stopped state (set stop processing 602), and then the cache hit rate is counted (cache hit rate count 603). This cache hit rate is compared with e%, which is a preset condition (condition determination 604), and it is determined whether or not to return to the state before transition according to the result (set restoration process 605). This algorithm corresponds to periodically checking the cache memory size and its effectiveness and verifying whether the cache hit rate can be maintained even with a smaller number of sets. By reducing the number of sets, power consumption in the semiconductor device can be reduced. The algorithm described here can be executed by software (program) or hardware.

  The case where this operation is performed by hardware is shown below. The counting circuit counts the time of d seconds, and changes the set control signal to change any set from the operating state to the stopped state. Thereafter, the cache hit rate is counted by a counting circuit and stored in a register. Thereafter, the cache hit rate and e% which is a preset condition are compared by the condition determination circuit, and it is determined whether or not to return to the state before the transition according to the result.

  Even in the algorithm in the present embodiment, the parameters d and e can be set as fixed values, but it is desirable to update appropriately while observing the cache hit rate. This is because the optimum reference value depends on the program that is actually executed by the CPU. These values are updated by the CPU rewriting the register values.

  Furthermore, it is also effective to store the optimum d and e for a program that has been executed once, and set it to the value at the next execution. This is particularly effective when the CPU is used in a system that can execute various programs such as a personal computer. In order to store these parameters, d and e, the register 208 in FIG. 2 is effective.

  Further, by counting the tag hit rate for each set in the d-second access as an arbitrary time (tag hit rate count 606), and determining the set to be shifted to the stop state, more optimal control is possible. By stopping a set with a low tag hit rate, it is considered that the decrease in the cache hit rate is slight before and after the set stop, and the stop set can be controlled effectively. Therefore, power consumption can be more precisely reduced.

  With the above-described configuration, it is possible to provide a high-performance and low-power-consumption CPU equipped with a cache memory that can select optimal performance and power consumption according to the operation state.

  Note that the CPU in this embodiment is composed of a thin film transistor using a semiconductor thin film formed on a substrate having an insulating surface such as a glass substrate, a quartz substrate, or a plastic substrate as an active layer, thereby achieving high performance and low power consumption. CPU can be provided at a lower weight and at a lower cost.

  Furthermore, by configuring an electronic device using the CPU in this embodiment, a high-performance and low power consumption electronic device can be provided at a lower weight and at a lower cost.

  This embodiment can be carried out in any combination with the best mode for carrying out the invention and Embodiment 1.

  In this embodiment, a personal computer will be described as a system using a CPU in the present invention.

  FIG. 7 shows a configuration diagram of the personal computer. In FIG. 7, a CPU 702, a north bridge (NB) 703, a south bridge (SB) 704, an SDRAM 705, and an image processing circuit 706 are mounted on a motherboard 701. The SB 704 includes a hard disk controller 707, a flexible disk cartridge controller 708, a mouse controller 709, and a keyboard controller 710. An image processing circuit 706, a hard disk controller 707, a flexible disk cartridge controller 708, a mouse controller 709, and a keyboard controller 710 control the display 711, hard disk 712, flexible disk cartridge 713, mouse 714, and keyboard 715, respectively.

  Here, the NB 703 is a semiconductor device in which a controller circuit of a semiconductor device that needs to perform high-speed data access with the CPU, such as an SDRAM 705 and an image processing circuit 706, is integrated. The SB 704 is a semiconductor device in which a controller circuit of a semiconductor device that performs low-speed data access with the CPU 702 is integrated.

By using the present invention for the CPU 702, a high performance and low power consumption system can be provided. Further, by using the present invention for the processor in the image processing circuit 706, a system with higher performance and lower power consumption can be provided.

  This embodiment can be carried out in any combination with the best mode for carrying out the invention, Embodiment 1 and Embodiment 2.

  In this embodiment, an example of an electronic device manufactured using the CPU in the present invention will be described with reference to FIGS.

  As an electronic device manufactured using the present invention, a camera such as a video camera or a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a personal computer, a game device, Play back a recording medium such as a portable information terminal (mobile computer, mobile phone, portable game machine or electronic book), an image playback device (specifically, Digital Versatile Disc (DVD)) provided with a recording medium, A device having a display capable of displaying). Specific examples of these electronic devices are shown in FIGS.

  FIG. 4A illustrates a display device, which includes a housing 1401, a support base 1402, and a display portion 1403. The present invention can be applied to the controller of the display unit 1403. By using the present invention, low power consumption of the display device can be realized.

  FIG. 4B illustrates a video camera, which includes a main body 1411, a display portion 1412, an audio input portion 1413, an operation switch 1414, a battery 1415, an image receiving portion 1416, and the like. The present invention can be applied to the CPU inside the main body 1411 and the controller of the display unit 1412. By using the present invention, the video camera can be reduced in size and weight.

  FIG. 4C illustrates a personal computer, which includes a main body 1421, a housing 1422, a display portion 1423, a keyboard 1424, and the like. The present invention can be applied to the controller of the display portion 1423. Further, the present invention can be applied to the CPU inside the main body 1421. By using the present invention, low power consumption of a personal computer can be realized.

  FIG. 4D illustrates a portable information terminal which includes a main body 1431, a stylus 1432, a display portion 1433, operation buttons 1434, an external interface 1435, and the like. The present invention can be applied to the controller of the display portion 1433. Further, the present invention can be applied to the CPU inside the main body 1431. By using the present invention, low power consumption of the portable information terminal can be realized.

  FIG. 4E illustrates a sound reproducing device, specifically an in-vehicle audio device, which includes a main body 1441, a display portion 1442, an operation switch 1443, an operation switch 1444, and the like. The present invention can be applied to the controller of the display unit 1442. Further, the present invention can be applied to the CPU inside the main body 1441. In this example, the on-vehicle audio device is taken as an example, but it may be used for a portable or home audio device. By using the present invention, low power consumption of the sound reproducing device can be realized.

  FIG. 4F illustrates a digital camera, which includes a main body 1451, a display portion (A) 1452, an eyepiece portion 1453, operation switches 1454, a display portion (B) 1455, a battery 1456, and the like. The present invention can be applied to the controllers of the display portion (A) 1452 and the display portion (B) 1455. Further, the present invention can be applied to the CPU inside the main body 1451. By using the present invention, low power consumption of a digital camera can be realized.

  FIG. 4G illustrates a cellular phone, which includes a main body 1461, an audio output portion 1462, an audio input portion 1463, a display portion 1464, operation switches 1465, an antenna 1466, and the like. The present invention can be applied to the controller of the display unit 1464. Further, the present invention can be applied to the CPU inside the main body 1461. By using the present invention, low power consumption of a mobile phone can be realized.

  A semiconductor device and a display device used in these electronic devices can use not only a glass substrate but also a heat-resistant plastic substrate. Thereby, weight reduction can be achieved.

  The present invention is not limited to the above electronic devices, and can be various electronic devices using the best mode for carrying out the invention and the arithmetic processing units shown in the first to third embodiments. .

1 is a schematic diagram of a general associative cache memory. The schematic diagram of the arithmetic processing unit in this invention. 1 is a schematic diagram of an associative cache memory installed in an arithmetic processing unit according to the present invention. The electronic device which applied the arithmetic processing unit in this invention. The flowchart 1 of the algorithm in the control circuit mounted in the arithmetic processing unit in this invention. The flowchart 2 of the algorithm in the control circuit mounted in the arithmetic processing unit in this invention. The system using the arithmetic processing unit in this invention.

Explanation of symbols

101 cache memory 102 first set 103 second set 104 tag comparison circuit 105 data selection circuit 106 first tag memory 107 first data memory 108 second tag memory 109 second data memory 110 first comparison Circuit 111 Second comparison circuit 112 Address 113 Address upper bit 114 Address lower bit 115 First tag data 116 First copy data 117 Second tag data 118 Second copy data 119 First tag hit signal 120 2 tag hit signal 121 Cache data 122 Cache hit signal

Claims (41)

An arithmetic processing unit having a cache memory,
At least one set having a data memory and a tag memory;
Means for transitioning between an operating state and a stopped state of one of the data memory or the tag memory;
Counting the number of accesses to the cache memory, the number of cache hits in the cache memory, the number of tag hits in the tag memory, and the cache hit rate obtained by dividing the number of cache hits by the number of accesses for an arbitrary period Means to
An arithmetic processing apparatus comprising: An arithmetic processing unit having a cache memory,
At least one set having a data memory and a tag memory;
Means for transitioning between an operating state and a stopped state of one of the data memory or the tag memory;
Counting the number of accesses to the cache memory, the number of cache hits in the cache memory, the number of tag hits in the tag memory, and the cache hit rate obtained by dividing the number of cache hits by the number of accesses for any period And means for
According to a result of comparing the cache hit rate and a value arbitrarily set as a reference value of the first hit rate by the means for making a transition, one of the data memory or the tag memory in an operating state is selected. An arithmetic processing apparatus characterized by causing a transition to a stopped state. In claim 2,
An arithmetic processing apparatus comprising: means for changing a reference value of the first hit rate to another value during the operation of the arithmetic processing apparatus. In claim 3,
The arithmetic processing device, wherein the reference value of the first hit rate is changed for each program executed by the arithmetic processing device. In any one of Claims 1 thru | or 4,
According to a result of comparing the cache hit rate and a value arbitrarily set as a reference value of the second hit rate by the means for making a transition, one of the data memory or the tag memory in a stopped state is An arithmetic processing device characterized by causing transition to an operating state. In claim 5,
Means for changing the reference value of the second hit rate to another value during the operation of the arithmetic processing unit. In claim 6,
The arithmetic processing device, wherein the second hit rate reference value is changed for each program executed by the arithmetic processing device. An arithmetic processing unit having a cache memory,
At least one set having a data memory and a tag memory;
Means for transitioning between an operating state and a stopped state of one of the data memory or the tag memory;
Counting the number of accesses to the cache memory, the number of cache hits in the cache memory, the number of tag hits in the tag memory, and the cache hit rate obtained by dividing the number of cache hits by the number of accesses for any period And means for
An arithmetic processing unit characterized in that the transition means causes one of the data memory or the tag memory in an operating state to transition to a stopped state for each value arbitrarily set as a reference value for the first time. In claim 8,
An arithmetic processing apparatus comprising: means for changing the reference value of the first time to another value during the operation of the arithmetic processing apparatus. In claim 9,
The arithmetic processing apparatus, wherein the first time reference value is changed for each program executed by the arithmetic processing apparatus. In claims 8 to 10,
An arithmetic processing unit characterized in that, by means of the transition, one of the data memory or the tag memory in a stopped state is shifted to an operating state for each value arbitrarily set as a reference value for a second time. In claim 11,
An arithmetic processing apparatus comprising: means for changing the second time reference value to another value during operation of the arithmetic processing apparatus. In claim 12,
The arithmetic processing apparatus, wherein the second time reference value is changed for each program executed by the arithmetic processing apparatus. In any one of Claims 1 thru | or 13,
The arithmetic processing unit performs an operation of transitioning one of the data memory or the tag memory in an operating state to a stopped state, or an operation of transitioning one of the data memory or the tag memory in a stopped state to an operating state, An arithmetic processing unit comprising means for controlling in accordance with an instruction from the arithmetic processing unit. In any one of Claims 1 thru | or 13,
The arithmetic processing unit performs an operation of transitioning one of the data memory or the tag memory in an operating state to a stopped state, or an operation of transitioning one of the data memory or the tag memory in a stopped state to an operating state, An arithmetic processing apparatus comprising: a control circuit mounted on the arithmetic processing apparatus; and a means for controlling the control circuit according to a command from the arithmetic processing apparatus. An arithmetic processing unit having a cache memory,
A plurality of sets each having a data memory and a tag memory;
Means for transitioning between an operating state and a stopped state of the plurality of sets;
Any number of accesses to the cache memory, the number of cache hits of the cache memory, the number of tag hits in any of the plurality of sets, and the cache hit rate obtained by dividing the number of cache hits by the number of accesses Means for counting the period of
An arithmetic processing apparatus comprising: An arithmetic processing unit having a cache memory,
A plurality of sets each having a data memory and a tag memory;
Means for transitioning between an operating state and a stopped state of the plurality of sets;
Any number of accesses to the cache memory, cache hits of the cache memory, tag hits in any of the plurality of sets, and a cache hit rate obtained by dividing the cache hits by the number of accesses Means for counting for a period of
Depending on a result of comparing the cache hit rate and a value arbitrarily set as a reference value of the third hit rate by the means for making a transition, any one of the plurality of sets in the operating state is stopped. An arithmetic processing device characterized by making a transition to. In claim 17,
Means for changing the reference value of the third hit rate to another value during operation of the arithmetic processing unit. In claim 18,
The arithmetic processing device, wherein the third hit rate reference value is changed for each program executed by the arithmetic processing device. In any one of Claims 17-19,
According to a result of comparing the cache hit rate and a value arbitrarily set as a reference value of the fourth hit rate by the means for making a transition, any one of the plurality of sets in the stopped state is in an operating state. An arithmetic processing device characterized by making a transition to. In claim 20,
An arithmetic processing apparatus comprising: means for changing the reference value of the fourth hit rate to another value during operation of the arithmetic processing apparatus. In claim 21,
The arithmetic processing apparatus, wherein the fourth hit rate reference value is changed for each program executed by the arithmetic processing apparatus. An arithmetic processing unit having a cache memory,
A plurality of sets each having a data memory and a tag memory;
Means for transitioning between an operating state and a stopped state of the plurality of sets;
Count the number of accesses to the cache memory, the number of cache hits in the cache memory, the number of tag hits in the set, and the cache hit rate obtained by dividing the number of cache hits by the number of accesses for any period. Means,
An arithmetic processing apparatus characterized in that, by means of the transition, any one of the plurality of sets in the operating state is transitioned to a stopped state for each value arbitrarily set as a third time reference value. An arithmetic processing unit having a cache memory,
A plurality of sets each having a data memory and a tag memory;
Means for transitioning between an operating state and a stopped state of the plurality of sets;
Any number of accesses to the cache memory, cache hits of the cache memory, tag hits in any of the plurality of sets, and a cache hit rate obtained by dividing the cache hits by the number of accesses Means for counting for a period of
For each value arbitrarily set as the reference value for the third time by the means for transition, the set having the smallest number of tag hits among the plurality of sets in the operating state is transitioned to the stopped state. Arithmetic processing unit to perform. In claim 23 or claim 24,
An arithmetic processing apparatus comprising: means for changing the reference value of the third time to another value during operation of the arithmetic processing apparatus. In claim 25,
The arithmetic processing apparatus, wherein the third time reference value is changed for each program executed by the arithmetic processing apparatus. In any one of claims 23 to 26,
The arithmetic processing apparatus, wherein the transition means causes at least one of the sets in the stopped state to transition to an operating state for each value arbitrarily set as a fourth time reference value. In claim 27,
An arithmetic processing apparatus comprising: means for changing the fourth time reference value to another value during the operation of the arithmetic processing apparatus. In claim 28,
The arithmetic processing unit, wherein the fourth time reference value is changed for each program executed by the arithmetic processing unit. In any one of claims 23 to 29,
After the operation for transitioning to the stopped state, the set that has been transitioned to the stopped state in the operation according to a result of comparing the cache hit rate and a value arbitrarily set as a reference value for the fifth hit rate An arithmetic processing unit characterized by having means for making a transition to the operating state again. In claim 30,
An arithmetic processing apparatus comprising: means for changing the reference value of the fifth hit rate to another value during the operation of the arithmetic processing apparatus. In claim 31,
The arithmetic processing device, wherein the reference value of the fifth hit rate is changed for each program executed by the arithmetic processing device. In any one of claims 30 to 32,
The set that is changed to the operation state in the operation according to the result of comparing the cache hit rate and the value arbitrarily set as the reference value of the sixth hit rate after the operation to change to the operation state An arithmetic processing unit characterized by having means for making a transition to a stopped state again. In claim 33,
An arithmetic processing apparatus comprising: means for changing the reference value of the sixth hit rate to another value during the operation of the arithmetic processing apparatus. In claim 34,
The arithmetic processing apparatus, wherein the sixth hit rate reference value is changed for each program executed by the arithmetic processing apparatus. In any one of claims 16 to 35,
The arithmetic processing unit has means for controlling an operation for transitioning the set in an operating state to a stopped state, or an operation for transitioning the set in a stopped state to an operating state by an instruction of the arithmetic processing unit. An arithmetic processing device characterized by the above. In any one of claims 16 to 35,
The arithmetic processing device performs an operation for transitioning the set in an operating state to a stopped state, or an operation for transitioning the set in a stopped state to an operating state, and a control circuit mounted on the arithmetic processing device; An arithmetic processing apparatus comprising: means for controlling according to an instruction of the processing apparatus. In any one of claims 1 to 37,
The arithmetic processing apparatus according to claim 1, wherein the stopped state is a state in which a precharge operation that is performed when reading data stored in the data memory and the tag memory is not performed. In any one of claims 1 to 37,
The arithmetic processing apparatus according to claim 1, wherein the stopped state is a state in which a power supply voltage is not supplied to the data memory and the tag memory. 40. In any one of claims 1 to 39,
The arithmetic processing unit has a thin film transistor,
The thin film transistor is a semiconductor thin film formed on a substrate having an insulating surface,
The arithmetic processing apparatus, wherein the substrate having an insulating surface is any one of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate.   The electronic device using the arithmetic processing apparatus as described in any one of Claims 1 thru | or 40.

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