JP4512303B2 - 最適なアクセスのためのレジスタ構成 - Google Patents

最適なアクセスのためのレジスタ構成 Download PDF

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Publication number
JP4512303B2
JP4512303B2 JP2001544138A JP2001544138A JP4512303B2 JP 4512303 B2 JP4512303 B2 JP 4512303B2 JP 2001544138 A JP2001544138 A JP 2001544138A JP 2001544138 A JP2001544138 A JP 2001544138A JP 4512303 B2 JP4512303 B2 JP 4512303B2
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JP
Japan
Prior art keywords
register
registers
group
access
host processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2001544138A
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English (en)
Japanese (ja)
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JP2003524834A (ja
JP2003524834A5 (enExample
Inventor
ドゥウォーク，ジェフリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2003524834A publication Critical patent/JP2003524834A/ja
Publication of JP2003524834A5 publication Critical patent/JP2003524834A5/ja
Application granted granted Critical
Publication of JP4512303B2 publication Critical patent/JP4512303B2/ja
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Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Information Transfer Systems (AREA)
JP2001544138A 1999-12-07 2000-06-07 最適なアクセスのためのレジスタ構成 Expired - Lifetime JP4512303B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US16927299P 1999-12-07 1999-12-07
US60/169,272 1999-12-07
US09/488,783 2000-01-21
US09/488,783 US6915356B1 (en) 1999-12-07 2000-01-21 Register addresses optimum access
PCT/US2000/015585 WO2001042913A1 (en) 1999-12-07 2000-06-07 Register arrangement for optimum access

Publications (3)

Publication Number Publication Date
JP2003524834A JP2003524834A (ja) 2003-08-19
JP2003524834A5 JP2003524834A5 (enExample) 2007-05-31
JP4512303B2 true JP4512303B2 (ja) 2010-07-28

Family

ID=26864915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001544138A Expired - Lifetime JP4512303B2 (ja) 1999-12-07 2000-06-07 最適なアクセスのためのレジスタ構成

Country Status (5)

Country Link
US (1) US6915356B1 (enExample)
EP (1) EP1236091B1 (enExample)
JP (1) JP4512303B2 (enExample)
DE (1) DE60007553T2 (enExample)
WO (1) WO2001042913A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8593465B2 (en) * 2007-06-13 2013-11-26 Advanced Micro Devices, Inc. Handling of extra contexts for shader constants
US10007590B2 (en) 2016-04-14 2018-06-26 International Business Machines Corporation Identifying and tracking frequently accessed registers in a processor
US10949202B2 (en) 2016-04-14 2021-03-16 International Business Machines Corporation Identifying and tracking frequently accessed registers in a processor
US20190095143A1 (en) * 2017-09-25 2019-03-28 Kabushiki Kaisha Toshiba Integrated circuit, image forming apparatus, and address assignment method
CN115081366B (zh) * 2022-06-13 2024-04-05 云合智网(上海)技术有限公司 寄存器突发访问的建模方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4177462A (en) * 1976-12-30 1979-12-04 Umtech, Inc. Computer control of television receiver display
US4916301A (en) * 1987-02-12 1990-04-10 International Business Machines Corporation Graphics function controller for a high performance video display system
US5440714A (en) 1992-12-14 1995-08-08 Industrial Technology Research Institute Method and system configuration for simplifying the decoding system for access to an register file with overlapping windows
US5752073A (en) * 1993-01-06 1998-05-12 Cagent Technologies, Inc. Digital signal processor architecture
JPH06231072A (ja) * 1993-02-04 1994-08-19 Mitsubishi Electric Corp マイクロコンピュータ
JP3676411B2 (ja) 1994-01-21 2005-07-27 サン・マイクロシステムズ・インコーポレイテッド レジスタファイル装置及びレジスタファイルアクセス方法
US5805842A (en) 1995-09-26 1998-09-08 Intel Corporation Apparatus, system and method for supporting DMA transfers on a multiplexed bus
US6189082B1 (en) * 1999-01-29 2001-02-13 Neomagic Corp. Burst access of registers at non-consecutive addresses using a mapping control word

Also Published As

Publication number Publication date
US6915356B1 (en) 2005-07-05
JP2003524834A (ja) 2003-08-19
DE60007553D1 (de) 2004-02-05
EP1236091A1 (en) 2002-09-04
DE60007553T2 (de) 2004-11-18
WO2001042913A1 (en) 2001-06-14
EP1236091B1 (en) 2004-01-02

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