JP4506666B2 - Manufacturing method of double-sided wiring tape carrier - Google Patents

Manufacturing method of double-sided wiring tape carrier Download PDF

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JP4506666B2
JP4506666B2 JP2005366535A JP2005366535A JP4506666B2 JP 4506666 B2 JP4506666 B2 JP 4506666B2 JP 2005366535 A JP2005366535 A JP 2005366535A JP 2005366535 A JP2005366535 A JP 2005366535A JP 4506666 B2 JP4506666 B2 JP 4506666B2
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foil layer
double
tape
tape carrier
film
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JP2007173377A (en
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裕章 平塚
宏之 岡部
智幸 浅川
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

本発明は、ＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）テープまたはＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）用の両面配線テープキャリア及びその製造方法に係り、特に両面配線テープキャリアを矯正するためにテープ反り量の低減を図った両面配線テープキャリアの製造方法に関する。
The present invention relates to a double-sided wiring tape carrier for TAB (Tape Automated Bonding) tape or BGA (Ball Grid Array) and a method for manufacturing the double-sided wiring tape carrier. a method for manufacturing a wiring tape career.

図６に示すように、両面配線テープキャリア６１は、両面にＣｕ箔層６２を有する絶縁性フィルム６３の一面または両面のＣｕ箔層６２をフォトエッチング、また絶縁性フィルム６３に対しレーザー加工を施すことによって導通用のビアホール６４を形成し、ビアホール６４内に酸性電解Ｃｕメッキを直接施すことによって両面のＣｕ箔層６２を導通化するためのメッキ層６５を形成し、絶縁性フィルム６３の両面のＣｕ箔層６２を同時または逐次フォトエッチングすることにより形成されたワイヤボンディングパッド６６、ボールパッド（ハンダボールランド）６７等からなる電気配線を具備する。   As shown in FIG. 6, the double-sided wiring tape carrier 61 performs photoetching on one side or both sides of the Cu foil layer 62 having the Cu foil layer 62 on both sides, and laser processing the insulating film 63. Thus, a via hole 64 for conduction is formed, and a plated layer 65 for conducting the Cu foil layer 62 on both sides is formed by directly applying acidic electrolytic Cu plating in the via hole 64, and both sides of the insulating film 63 are formed. An electrical wiring composed of a wire bonding pad 66, a ball pad (solder ball land) 67, and the like formed by photo-etching the Cu foil layer 62 simultaneously or sequentially is provided.

このボールパッド６７にはハンダボールが接着され、このハンダボールによって、両面配線テープキャリア６１は半導体装置として電気配線板上に実装される。両面配線テープキャリア６１上には、半導体チップ６８がＡｇペーストまたは接着材テープにより搭載される。半導体チップ６８は、Ａｕワイヤ６９により、両面配線テープキャリア６１上のＣｕ箔等からなるワイヤボンディングパッド６６に電気的に接続される。ワイヤボンディングパッド６６は電気配線により、図示しないハンダボールを接着するボールパッド６７と電気的に接続される。ワイヤボンディングパッド６６は、Ａｕワイヤ６９を接続されるため、ＡｕとＮｉによりメッキされる。   A solder ball is bonded to the ball pad 67, and the double-sided wiring tape carrier 61 is mounted on the electric wiring board as a semiconductor device by the solder ball. On the double-sided wiring tape carrier 61, the semiconductor chip 68 is mounted by Ag paste or adhesive tape. The semiconductor chip 68 is electrically connected to a wire bonding pad 66 made of Cu foil or the like on the double-sided wiring tape carrier 61 by an Au wire 69. The wire bonding pad 66 is electrically connected to a ball pad 67 for bonding a solder ball (not shown) by electric wiring. The wire bonding pad 66 is plated with Au and Ni in order to connect the Au wire 69.

ここに一般的な両面配線テープキャリア６１の平面図を図７（ａ）にその正面図を図７（ｂ）に示す。図７（ａ）および図７（ｂ）に示すように、両面配線テープ６１は、折り曲げ立体加工が可能というその特徴から分かるように、柔軟な材料であるポリイミド材を基材として用いている。また、両面配線テープキャリア６１は、絶縁性フィルム６３としてのポリイミドフィルムの両面にＣｕ箔層６２を有する基材をベース材とし、それを細長で長尺のテープ状としておき、それにテープ製造工程搬送用に使用するスプロケットホール７１を規格に基づいてパンチングした後、それにドライフィルムラミネート加工やエッチング技術により所望の回路パターンを形成する。   Here, a plan view of a general double-sided wiring tape carrier 61 is shown in FIG. 7 (a), and a front view thereof is shown in FIG. 7 (b). As shown in FIGS. 7A and 7B, the double-sided wiring tape 61 uses a polyimide material, which is a flexible material, as a base material, as can be seen from the characteristic that bending solid processing is possible. Further, the double-sided wiring tape carrier 61 uses a base material having a Cu foil layer 62 on both sides of a polyimide film as an insulating film 63 as a base material, which is formed into a long and slender tape shape, and transports it to the tape manufacturing process. After punching the sprocket hole 71 to be used according to the standard, a desired circuit pattern is formed on the sprocket hole 71 by dry film laminating or etching technology.

しかし、テープ製造工程搬送用に使用するスプロケットホール部分のＣｕ箔層６２をエッチング加工により除去してしまい、ポリイミドフィルム層の単体にしてしまうと、そのテープ基材の特徴的な利点である「柔軟性」、「薄膜化」により、そのポリイミドフィルムが搬送中に破損してしまい、以後のテープ製造加工が不可能になるという問題があった。そのために、従来の両面配線テープキャリア６１では、テープ製造工程搬送用として使用するスプロケットホール部の両面のＣｕ箔層６２はエッチング加工を行わずに、そのまま残存させておくことによって、テープ製造加工を行っていた。   However, if the Cu foil layer 62 in the sprocket hole portion used for transporting the tape manufacturing process is removed by etching, and the polyimide film layer is formed as a single body, the characteristic advantage of the tape base material is “flexibility” ”And“ thinning ”cause the polyimide film to be damaged during transportation, making the subsequent tape manufacturing process impossible. Therefore, in the conventional double-sided wiring tape carrier 61, the Cu foil layers 62 on both sides of the sprocket hole portion used for transporting the tape manufacturing process are left without being etched, so that the tape manufacturing process is performed. I was going.

なお、この出願の発明に関連する先行技術文献情報としては、次のものがある。   The prior art document information related to the invention of this application includes the following.

特開２００１−５３１０８号公報JP 2001-53108 A 特開２００３−３４７３６６号公報JP 2003-347366 A

しかしながら、従来の両面配線テープキャリアでは、そうした場合、テープ幅方向中央部付近のＣｕ箔層６２を使用しての配線形成のためのエッチング加工時に、そのＣｕ箔層６２が除去されることによって、Ｃｕ箔層６２と絶縁性フィルム６３を貼り合わせるために行ったラミネーション作業時に内在した内部応力が、そのエッチング加工時に開放されるが、テープ幅方向での両端部にＣｕ箔層６２が残存していることから、その内部応力起因により、特にテープ幅方向両端部の形状が波打ちのように悪化していた。   However, in the conventional double-sided wiring tape carrier, in such a case, the Cu foil layer 62 is removed at the time of etching processing for wiring formation using the Cu foil layer 62 near the center in the tape width direction. The internal stress inherent in the lamination work performed to bond the Cu foil layer 62 and the insulating film 63 is released during the etching process, but the Cu foil layer 62 remains at both ends in the tape width direction. Therefore, due to the internal stress, the shape of both ends in the tape width direction was particularly deteriorated as a wave.

また、両面配線テープキャリア６１に反りが発生すると、半導体チップ６８の実装時に、ダイアタッチペーストが平坦に塗布できなくなる。またはダイアタッチペーストが塗布できたとしてもモールド後の加圧時にＩＣチップなどの半導体チップ６８にクラックが発生する等の不良発生の原因となる。   Further, when the double-sided wiring tape carrier 61 is warped, the die attach paste cannot be applied flatly when the semiconductor chip 68 is mounted. Alternatively, even if the die attach paste can be applied, it may cause defects such as cracks occurring in the semiconductor chip 68 such as an IC chip during pressurization after molding.

また、長尺の両面配線テープキャリア６１を使用して半導体チップ６８の実装を行う際には、その作業性のためにテープを短く切断し、さらにＣｕもしくはステンレスのフレームに貼り付けることで実装作業を行っている。ただし、上記のようなテープの端部に波打ちのような形状があると、そのフレーム貼付工程で清浄にフレームと両面配線テープキャリア６１の貼り合わせ作業が行えず、テープを貼り付けたフレームそのものを廃却するといったような実装歩留を低下させる要因になっている。   Also, when mounting the semiconductor chip 68 using the long double-sided wiring tape carrier 61, the mounting work is performed by cutting the tape short for the workability and further attaching it to a Cu or stainless steel frame. It is carried out. However, if there is a wavy shape at the end of the tape as described above, the frame and the double-sided wiring tape carrier 61 cannot be bonded together cleanly in the frame affixing process, and the frame itself with the tape affixed This is a factor that reduces the mounting yield, such as abandonment.

そこで、本発明の目的は、テープ幅方向両端に残存するＣｕ箔層を除去してテープ反り量の低減を図った両面配線テープキャリアの製造方法を提供することにある。
An object of the present invention is to provide a method of manufacturing a double-sided wiring tape career which aimed at reducing the tape warpage by removing the Cu foil layer remaining in the tape width direction at both ends.

本発明は上記目的を達成するために創案されたものであり、請求項１の発明は、複数の半導体チップ搭載部を有し、テープ幅方向両端部のスプロケットホールエリアの一方のＣｕ箔層のみを残存させる両面配線テープキャリアの製造方法において、両面にＣｕ箔層を有する長尺の絶縁性フィルムにその絶縁性フィルムを貫通するビアホールを形成し、そのビアホールの壁面に導電性薄膜を形成し、その導電性膜上に両面のＣｕ箔層を導通化するためのメッキ層を形成し、前記絶縁性フィルムの両面のＣｕ箔層を同時あるいは逐次フォトエッチングして一面にＣｕ配線パターンを形成する際に、テープ幅方向両端部のスプロケットホールエリアの一方のＣｕ箔層上に樹脂等の塗布により保護膜を形成した後、他方のＣｕ箔層のエッチングを行って保護膜に保護されたＣｕ箔層のみを残存させることを特徴とする両面配線テープキャリアの製造方法である。
The present invention has been devised to achieve the above object, and the invention of claim 1 has a plurality of semiconductor chip mounting portions, and only one Cu foil layer in the sprocket hole area at both ends in the tape width direction. In the manufacturing method of the double-sided wiring tape carrier that leaves the film, a via hole penetrating the insulating film is formed in a long insulating film having a Cu foil layer on both sides, and a conductive thin film is formed on the wall surface of the via hole. When forming a Cu wiring pattern on one side by forming a plated layer on both sides of the conductive film on the conductive film and then photoetching the Cu foil layers on both sides of the insulating film simultaneously or sequentially Next, after forming a protective film on one Cu foil layer in the sprocket hole area at both ends in the tape width direction by applying a resin or the like, the other Cu foil layer is etched. A method for producing a double-sided circuit tape carrier, characterized in that to leave only the Cu foil layer protected by a protective film.

請求項２の発明は、前記導電性膜は、Ｓｎ−Ｐｄまたはその化合物、あるいはグラファイト、導電性カーボン、あるいはポリピロールの如き導電性ポリマの内から選ばれたものからなる請求項１記載の両面配線テープキャリアの製造方法である。
The invention according to claim 2 is the double-sided wiring according to claim 1 , wherein the conductive film is selected from Sn-Pd or a compound thereof, or a conductive polymer such as graphite, conductive carbon, or polypyrrole. It is a manufacturing method of a tape carrier .

請求項３の発明は、前記メッキ層は、前記導電性薄膜上に酸性電解Ｃｕメッキを直接施すことによって形成される請求項１または２記載の両面配線テープキャリアの製造方法である。
The invention according to claim 3 is the method for producing a double-sided wiring tape carrier according to claim 1 or 2 , wherein the plating layer is formed by directly applying acidic electrolytic Cu plating on the conductive thin film .

本発明によれば、両面配線テープキャリアの反り量低減のためにテープ幅方向両端部のスプロケットホールエリアの一方のＣｕ箔層のみ残存させることにより、両面配線テープ構成・構造に起因するテープ反りを低減することができる。   According to the present invention, only one Cu foil layer in the sprocket hole area at both ends of the tape width direction is left to reduce the amount of warpage of the double-sided wiring tape carrier, thereby reducing the tape warpage caused by the double-sided wiring tape configuration / structure. Can be reduced.

以下、本発明の好適な実施形態を添付図面にしたがって説明する。   Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

図１は、本発明の好適な実施形態を示す両面配線テープキャリアの横断面図である。   FIG. 1 is a cross-sectional view of a double-sided wiring tape carrier showing a preferred embodiment of the present invention.

図１に示すように、本実施形態に係る両面配線テープキャリア１は、細長で長尺（あるいは短冊状の）のポリイミドフィルムなどの絶縁性フィルム２の両面（後述するスプロケットホールエリアの一方を除く）にＣｕ箔層３がそれぞれ形成される。絶縁性フィルム２の幅方向の両端には、長さ方向に沿ってテープキャリア１を連続搬送する際にスプロケットの歯が嵌るスプロケットホール４が複数個形成される。絶縁性フィルム２には、厚さ方向に貫通するビアホール５が形成される。   As shown in FIG. 1, a double-sided wiring tape carrier 1 according to the present embodiment has both sides of an insulating film 2 such as an elongated and long (or strip-shaped) polyimide film (excluding one of sprocket hole areas described later). ) Cu foil layer 3 is formed respectively. At both ends in the width direction of the insulating film 2, a plurality of sprocket holes 4 into which the teeth of the sprocket are fitted when the tape carrier 1 is continuously conveyed along the length direction are formed. The insulating film 2 is formed with a via hole 5 penetrating in the thickness direction.

図１でＣｕ箔層３を２層形成した理由は、Ｃｕ箔層とその上に形成したＣｕめっき層とを分けて示したためである。   The reason why the two Cu foil layers 3 are formed in FIG. 1 is that the Cu foil layer and the Cu plating layer formed thereon are shown separately.

ビアホール５には、図示しない導電性膜が形成され、その導電性膜の上に両面のＣｕ箔層３を導通化するためのメッキ層６が形成される。導電性膜は、Ｓｎ−Ｐｄまたはその化合物、あるいはグラファイト、導電性カーボン、あるいはポリピロールの如き導電性ポリマの内から選ばれたものからなる。メッキ層６は、導電性薄膜上に酸性電解Ｃｕメッキを直接施すことによって形成される。   A conductive film (not shown) is formed in the via hole 5, and a plated layer 6 for making the Cu foil layers 3 on both sides conductive is formed on the conductive film. The conductive film is made of Sn—Pd or a compound thereof, or a conductive polymer such as graphite, conductive carbon, or polypyrrole. The plating layer 6 is formed by directly applying acidic electrolytic Cu plating on the conductive thin film.

一方（図１では表面側）のＣｕ箔層３の一部には、Ａｕワイヤが接続されるワイヤボンディングパッド７が形成され、他方（図１では裏面側）のＣｕ箔層３の一部には、Ａｕ／Ｎｉメッキが施されたボールパッド（ハンダボールランド）８が形成される。絶縁性フィルム２とＣｕ箔層３上には、ワイヤボンディングパット７とボールパッド８を除いて絶縁層９が形成される。この絶縁層９の表面側の中央部分が半導体チップを搭載固定するための複数の半導体チップ搭載部９ｔである。   A wire bonding pad 7 to which an Au wire is connected is formed on a part of the Cu foil layer 3 on one side (front side in FIG. 1), and a part of the Cu foil layer 3 on the other side (back side in FIG. 1). The ball pad (solder ball land) 8 to which Au / Ni plating is applied is formed. An insulating layer 9 is formed on the insulating film 2 and the Cu foil layer 3 except for the wire bonding pad 7 and the ball pad 8. A central portion on the surface side of the insulating layer 9 is a plurality of semiconductor chip mounting portions 9t for mounting and fixing the semiconductor chips.

この両面配線テープキャリア１は、テープ反りを低減させるために、テープ幅方向両端部のスプロケットホールエリア（スプロケットホール部）の一方（図１では表面側）のＣｕ箔層３のみを残存させたものである。   This double-sided wiring tape carrier 1 is one in which only the Cu foil layer 3 on one side (surface side in FIG. 1) of the sprocket hole area (sprocket hole portion) at both ends in the tape width direction is left to reduce tape warpage. It is.

両面配線テープキャリアの半導体チップ搭載部９ｔに半導体チップを搭載固定し、半導体チップの電極とワイヤボンディングパット７とをＡｕワイヤでワイヤボンディング接続し、ボールパッド７にハンダボールを接続し、絶縁層９と半導体チップとをモールドレジンで樹脂封止すると、半導体装置（半導体パッケージ）が得られる。この半導体装置は、ハンダボールによるマザーボードと接続される。   The semiconductor chip is mounted and fixed on the semiconductor chip mounting portion 9t of the double-sided wiring tape carrier, the electrode of the semiconductor chip and the wire bonding pad 7 are wire-bonded with an Au wire, the solder ball is connected to the ball pad 7, and the insulating layer 9 When the semiconductor chip and the semiconductor chip are resin-sealed with a mold resin, a semiconductor device (semiconductor package) is obtained. This semiconductor device is connected to a mother board made of solder balls.

これに対し、図２に示すように、従来の両面配線テープキャリア２１は、スプロケットホールエリアの両方（両面）にＣｕ箔層３が形成されたものである。   On the other hand, as shown in FIG. 2, the conventional double-sided wiring tape carrier 21 has a Cu foil layer 3 formed on both sides (both sides) of the sprocket hole area.

次に、両面配線テープキャリア１の製造方法を図３（ａ）〜図３（ｆ）で説明する。   Next, a method for manufacturing the double-sided wiring tape carrier 1 will be described with reference to FIGS.

まず、ベース材である絶縁性フィルム２として、両面にＣｕ箔層３を有するポリイミド樹脂製フィルムを用意し、これを細長で長尺のテープ状としておく（図３（ａ））。絶縁性フィルム２の裏面側の２層のＣｕ箔層３は、Ｃｕ箔層とその上に形成したＣｕめっき層である。このポリイミド樹脂製フィルムの幅方向の両端に、長さ方向に沿ってスプロケットホール４を規格に基づいてパンチングして形成する（図３（ｂ））。   First, a polyimide resin film having a Cu foil layer 3 on both sides is prepared as an insulating film 2 as a base material, and this is formed into an elongated and long tape shape (FIG. 3A). The two Cu foil layers 3 on the back side of the insulating film 2 are a Cu foil layer and a Cu plating layer formed thereon. Sprocket holes 4 are punched and formed along the length direction at both ends of the polyimide resin film in the width direction (FIG. 3B).

スプロケットホール４を形成した後、ポリイミド樹脂製フィルムにビアホール５を形成し（図３（ｃ））、そのビアホール５の壁面に導電性膜（図示せず）を形成し、その導電性膜の上にメッキ層６を形成する（図３（ｄ））。   After the sprocket hole 4 is formed, a via hole 5 is formed in the polyimide resin film (FIG. 3C), a conductive film (not shown) is formed on the wall surface of the via hole 5, and the conductive film is formed on the conductive film. A plating layer 6 is formed on the substrate (FIG. 3D).

さて、図３（ｅ）に示すように、メッキ層６を形成した後、ポリイミド樹脂製フィルムにドライフィルムラミネート加工を行い、露光・現像技術によりＣｕ箔層３をエッチングし、所望の回路パターンをドライフィルム上に形成する。その後、スプロケットホール部のＣｕ箔層３が除去されないように、一方のＣｕ箔層３上に樹脂等の塗布による保護膜形成を行い、エッチング技術によりＣｕ箔回路パターンの形成を行う。つまり、保護膜形成を両面へのＣｕ箔層３へ行うのではなく、片面のみ行うことにより、一方のＣｕ箔層３のみがエッチング加工時に除去され、もう一方のＣｕ箔層３のみが残存することになる。さらに、一方のＣｕ箔層３の一部にワイヤボンディングパッド７を形成し、他方のＣｕ箔層３の一部にボールパッド８を形成する。   As shown in FIG. 3 (e), after the plating layer 6 is formed, the polyimide resin film is subjected to a dry film laminating process, and the Cu foil layer 3 is etched by an exposure / development technique to form a desired circuit pattern. Form on dry film. Thereafter, a protective film is formed on one Cu foil layer 3 by applying a resin or the like so that the Cu foil layer 3 in the sprocket hole portion is not removed, and a Cu foil circuit pattern is formed by an etching technique. That is, by forming the protective film only on one side rather than on the Cu foil layer 3 on both sides, only one Cu foil layer 3 is removed during the etching process, and only the other Cu foil layer 3 remains. It will be. Further, a wire bonding pad 7 is formed on a part of one Cu foil layer 3, and a ball pad 8 is formed on a part of the other Cu foil layer 3.

その後、絶縁性フィルム２とＣｕ箔層３上に、ワイヤボンディングパット７とボールパッド８を除いて絶縁層９を形成すると、図１に示した両面配線テープキャリア１が得られる（図１（ｆ））
本実施の形態の作用を説明する。 Thereafter, when the insulating layer 9 is formed on the insulating film 2 and the Cu foil layer 3 except for the wire bonding pad 7 and the ball pad 8, the double-sided wiring tape carrier 1 shown in FIG. 1 is obtained (FIG. 1 (f ))
The operation of the present embodiment will be described.

図４に、スプロケットホール部のＣｕ箔層３を両面残存させた場合（図２の両面配線テープキャリア２１）、片面一方のみを残存させた場合（本実施の形態に係る図１の両面配線テープキャリア１）、また参考として両面のＣｕ箔層全てを除去した場合のテープ反り量の測定結果を示す。   In FIG. 4, when both sides of the Cu foil layer 3 of the sprocket hole part are left (double-sided wiring tape carrier 21 of FIG. 2), when only one side is left (double-sided wiring tape of FIG. 1 according to the present embodiment) The measurement results of the amount of warpage of the tape when the carrier 1) and the Cu foil layers on both sides are removed as a reference are shown.

測定の方法は、図５に示すような測定器具５１を用い、各両面配線テープキャリアを定盤５２上にグランド面が下向きになるように置き、テープ中心のＥ点をゼロ点とし、Ａ点〜Ｄ点で示した４点の高さ（Ｚ方向）を測定し、下式
（反り量）＝Ｍａｘ（Ａ−Ｄ）−Ｅ
より反り量を測定した。反り量測定機器には、焦点顕微鏡を用いた。 The measuring method is to use a measuring instrument 51 as shown in FIG. 5 and place each double-sided wiring tape carrier on the surface plate 52 so that the ground surface faces downward. Measure the height (Z direction) of 4 points indicated by ~ D point, and the following formula (warping amount) = Max (AD) −E
The amount of warpage was measured. A focus microscope was used as the warpage measuring instrument.

なお、今回の実験に使用した機材材料の構成は下記の通りである。また、今回の実験においては、グランド面のＣｕ箔層３を除去した。   The equipment materials used in this experiment are as follows. In this experiment, the Cu foil layer 3 on the ground surface was removed.

銅厚 シグナル面：１２μｍ
グランド面：２７μｍ
絶縁性フィルム厚 ２５μｍ
図４に示すように、Ｃｕ箔層３を両面全て除去した場合に最も反り量を小さくできることが分かるが、上述したように、テープ製造工程時に搬送不具合が発生してしまう。これに対し、片面一方のみＣｕ箔層を除去した両面配線テープキャリア１では、Ｃｕ箔層３を両面全て除去した場合に比べれば若干反り量が大きいものの、Ｃｕ箔層３を両面残存させた場合に比べ、反り量が大幅に小さくなっていることが分かる。 Copper thickness Signal surface: 12μm
Ground plane: 27μm
Insulating film thickness 25μm
As shown in FIG. 4, it can be seen that the amount of warpage can be minimized when all of the Cu foil layer 3 is removed, but as described above, a conveyance failure occurs during the tape manufacturing process. On the other hand, in the double-sided wiring tape carrier 1 in which the Cu foil layer is removed on only one side, the amount of warping is slightly larger than when the Cu foil layer 3 is removed on both sides, but the Cu foil layer 3 is left on both sides. It can be seen that the amount of warpage is significantly smaller than

このように、両面配線テープキャリア１よれば、テープ幅方向両端部のＣｕ箔層３のどちらか一方のみをエッチング加工等により除去する、すなわちテープ幅方向両端部のスプロケットホールエリアの一方のＣｕ箔層のみ残存させることにより、テープ反り量の低減を図ることができる。   Thus, according to the double-sided wiring tape carrier 1, only one of the Cu foil layers 3 at both ends in the tape width direction is removed by etching or the like, that is, one Cu foil in the sprocket hole area at both ends in the tape width direction. By leaving only the layer, the amount of tape warp can be reduced.

したがって、両面配線テープキャリアの反り量低減のためにテープ幅方向両端部のスプロケットホールエリアの一方のＣｕ箔層のみ残存させることにより、両面配線テープ構成・構造に起因するテープ反りを低減することができる。   Therefore, by reducing only the one Cu foil layer in the sprocket hole area at both ends of the tape width direction in order to reduce the amount of warpage of the double-sided wiring tape carrier, tape warping caused by the double-sided wiring tape configuration / structure can be reduced. it can.

上記実施の形態において、今回の実験に使用した材料の構成厚およびＣｕ箔層３除去面を示したが、これとは異なる機材構成厚、もしくは除去面（例えばシグナル面）であっても、前記のような構造を達成することも考えられる。   In the above embodiment, the constituent thickness of the material used in this experiment and the removal surface of the Cu foil layer 3 are shown. It is also conceivable to achieve such a structure.

従来、両面配線テープキャリアは折り曲げ化、薄膜化およびファインピッチ化が可能であるが、柔軟な材料であるポリイミド材を基材として用いているため、実装時にテープ反りの問題があり、場合によってはＣｕもしくはステンレスフレームにテープを貼り付けた後に実装を行っていた。ただし、本実施の形態に係る両面配線テープキャリア１により、両面配線テープの反り量が低減でき、フレーム貼り付けの必要が無くなるため、実装コストの低減となることからテープ品の拡販が可能となる。   Conventionally, double-sided wiring tape carriers can be bent, thinned and fine pitched, but since a polyimide material, which is a flexible material, is used as a base material, there is a problem of tape warping during mounting, and in some cases Mounting was performed after tape was applied to Cu or a stainless steel frame. However, the double-sided wiring tape carrier 1 according to the present embodiment can reduce the amount of warpage of the double-sided wiring tape and eliminates the need to attach a frame, thereby reducing the mounting cost and increasing the sales of tape products. .

また、両面配線テープキャリアは、実装工程でのワイヤボンディングおよびハンダボール搭載のために、そのＣｕ箔層３表面にＡｕ／Ｎｉメッキを行うが、スプロケットホール部のＣｕ箔層３を片面除去することにより、Ａｕ／Ｎｉメッキ加工を施される面積そのものを小さくすることができる。これにより両面配線テープキャリアの製造コストを下げることが可能になり、テープ製品拡販を促進できる。   Further, the double-sided wiring tape carrier is subjected to Au / Ni plating on the surface of the Cu foil layer 3 for wire bonding and solder ball mounting in the mounting process, but the Cu foil layer 3 in the sprocket hole portion is removed on one side. Thus, the area itself subjected to Au / Ni plating can be reduced. This makes it possible to reduce the manufacturing cost of the double-sided wiring tape carrier and promote the sales expansion of tape products.

本発明の好適な実施形態を示す両面配線テープキャリアの横断面図である。It is a cross-sectional view of a double-sided wiring tape carrier showing a preferred embodiment of the present invention. 従来の両面配線テープキャリアの横断面図である。It is a cross-sectional view of a conventional double-sided wiring tape carrier. 図３（ａ）〜図３（ｆ）図１に示した両面配線テープキャリアの製造方法を示す横断面図である。3 (a) to 3 (f) are cross-sectional views showing a method for manufacturing the double-sided wiring tape carrier shown in FIG. 本発明と従来例におけるテープ反り量の測定結果の一例を示す図である。It is a figure which shows an example of the measurement result of the tape curvature amount in this invention and a prior art example. テープ反り量の測定方法を示す図である。It is a figure which shows the measuring method of tape curvature amount. 半導体チップ搭載後の従来の両面配線テープキャリアの横断面図である。It is a cross-sectional view of a conventional double-sided wiring tape carrier after mounting a semiconductor chip. 図７（ａ）は従来の両面配線テープキャリアの平面図、図７（ｂ）はその正面図である。FIG. 7A is a plan view of a conventional double-sided wiring tape carrier, and FIG. 7B is a front view thereof.

符号の説明Explanation of symbols

１ 両面配線テープキャリア
２ 絶縁性フィルム
３ Ｃｕ箔層
４ スプロケットホール
５ ビアホール
６ メッキ層
９ 絶縁層
９ｔ 半導体チップ搭載部 DESCRIPTION OF SYMBOLS 1 Double-sided wiring tape carrier 2 Insulating film 3 Cu foil layer 4 Sprocket hole 5 Via hole 6 Plating layer 9 Insulating layer 9t Semiconductor chip mounting part

Claims (3)

複数の半導体チップ搭載部を有し、テープ幅方向両端部のスプロケットホールエリアの一方のＣｕ箔層のみを残存させる両面配線テープキャリアの製造方法において、
両面にＣｕ箔層を有する長尺の絶縁性フィルムにその絶縁性フィルムを貫通するビアホールを形成し、そのビアホールの壁面に導電性薄膜を形成し、その導電性膜上に両面のＣｕ箔層を導通化するためのメッキ層を形成し、前記絶縁性フィルムの両面のＣｕ箔層を同時あるいは逐次フォトエッチングして一面にＣｕ配線パターンを形成する際に、テープ幅方向両端部のスプロケットホールエリアの一方のＣｕ箔層上に樹脂等の塗布により保護膜を形成した後、他方のＣｕ箔層のエッチングを行って保護膜に保護されたＣｕ箔層のみを残存させることを特徴とする両面配線テープキャリアの製造方法。 Have a plurality of semiconductor chip mounting portion, in the manufacturing method of the two surface wires tape carrier to leave only one of Cu foil layer of sprocket holes area in the tape width direction end portions,
A via hole penetrating the insulating film is formed in a long insulating film having a Cu foil layer on both sides, a conductive thin film is formed on the wall surface of the via hole, and a Cu foil layer on both sides is formed on the conductive film. When forming a Cu wiring pattern on one side by forming a plated layer for electrical conductivity and simultaneously or sequentially photo-etching the Cu foil layers on both sides of the insulating film, the sprocket hole areas at both ends of the tape width direction Double-sided wiring tape characterized in that after forming a protective film on one Cu foil layer by applying a resin or the like, the other Cu foil layer is etched to leave only the Cu foil layer protected by the protective film Carrier manufacturing method . 前記導電性膜は、Ｓｎ−Ｐｄまたはその化合物、あるいはグラファイト、導電性カーボン、あるいはポリピロールの如き導電性ポリマの内から選ばれたものからなる請求項１記載の両面配線テープキャリアの製造方法。 The conductive film, Sn-Pd or a compound thereof, or graphite, conductive carbon or the method for producing the double-sided circuit tape carrier according to claim 1, wherein consisting of those selected from among such conductive polymer polypyrrole. 前記メッキ層は、前記導電性薄膜上に酸性電解Ｃｕメッキを直接施すことによって形成される請求項１または２記載の両面配線テープキャリアの製造方法。 The plating layer, the method for producing the double-sided circuit tape carrier according to claim 1 or 2, wherein is formed by applying an acidic electrolytic Cu plating directly on the conductive thin film.
JP2005366535A 2005-12-20 2005-12-20 Manufacturing method of double-sided wiring tape carrier Expired - Fee Related JP4506666B2 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54121251U (en) * 1978-02-15 1979-08-24
JPS62291125A (en) * 1986-06-11 1987-12-17 Seiko Epson Corp Manufacture of circuit board
JPH0291956A (en) * 1988-09-29 1990-03-30 Toshiba Corp Film carrier
JPH04146637A (en) * 1990-10-08 1992-05-20 Ibiden Co Ltd Film carrier
JPH06236905A (en) * 1993-02-08 1994-08-23 Furukawa Electric Co Ltd:The Tape carrier

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54121251U (en) * 1978-02-15 1979-08-24
JPS62291125A (en) * 1986-06-11 1987-12-17 Seiko Epson Corp Manufacture of circuit board
JPH0291956A (en) * 1988-09-29 1990-03-30 Toshiba Corp Film carrier
JPH04146637A (en) * 1990-10-08 1992-05-20 Ibiden Co Ltd Film carrier
JPH06236905A (en) * 1993-02-08 1994-08-23 Furukawa Electric Co Ltd:The Tape carrier

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