JP4503955B2 - Solid-state imaging device and camera - Google Patents

Description

  The present invention relates to a MOS type solid-state imaging device used for a digital camera or the like.

Various types of conventional MOS type solid-state imaging devices have been proposed (see, for example, Patent Document 1).
FIG. 7 is a diagram showing an example of a conventional solid-state imaging device composed of MOS transistors. The solid-state imaging device 22 includes a photodiode unit (hereinafter abbreviated as a PD unit) 1 that photoelectrically converts incident light on a semiconductor substrate, a read transistor 2 that reads signal charges obtained from the PD unit 1, and a read transistor 2 Floating diffusion section (hereinafter abbreviated as FD section) 7 for storing the signal charge read in step 7, detection transistor 4 for detecting the signal charge stored in the FD section 7, and resetting the signal charge stored in the FD section 7 An imaging region 8 in which a plurality of amplification unit pixels each having a reset transistor 3, a vertical signal line 5, and a VDD power source 6 are arranged in a two-dimensional manner is provided. Furthermore, a horizontal shift register 9 for selecting a pixel column by a vertical signal line 5, a vertical shift register 10 for selecting a pixel row, a timing generation circuit 11 for supplying pulses necessary for driving, and an output amplifier 12 are provided.

  FIG. 8 is a cross-sectional view of a conventional solid-state imaging device. In this solid-state imaging device, a P-type semiconductor well layer 13 of an imaging unit and a P-type semiconductor well layer 14 of a peripheral circuit region are formed on an N-type substrate 16. The P-type semiconductor well layer 13 in the image pickup section and the P-type semiconductor well layer 14 in the peripheral circuit region have the same well potential 15, which is normally the ground potential (0 V). On the P-type semiconductor well layer 13 of the imaging unit, an N-type semiconductor PD unit 1, an FD unit 7, a VDD power supply 6, a read transistor 2, and a reset transistor 3 are formed. The VDD power supply 6, the read transistor 2, and the reset transistor 3 have a high level of 3V and a low level of 0V. Also, two N-type semiconductors are formed in the P-type semiconductor well layer 14 in the peripheral circuit region, and are connected to the gates of the read transistor 2 and the reset transistor 3, respectively. Although a cross-sectional view of the detection transistor 4 is not shown in FIG. 8, the detection transistor 4 is also formed on the P-type semiconductor well layer 13 of the imaging unit.

  FIG. 9 is a diagram illustrating an element circuit diagram of an imaging region in a solid-state imaging device according to a conventional technique. The signal charge photoelectrically converted by the PD unit 1 is accumulated in the PN junction capacitor of the PD unit 1 and then read out to the PN junction capacitor of the FD unit 7 by the read transistor 2. Since the FD portion 7 mainly has a PN junction capacitance, the potential of the FD portion 7 is determined by the amount of the read electric charge, and the gate voltage of the detection transistor 4 thereby changes, whereby the vertical signal line 5 A signal is taken out as a change in potential.

  FIG. 10 is a diagram showing the pixel unit drive timing in the prior art. The voltage pulse (hereinafter abbreviated as VDD pulse) of the VDD power source 6 during the operation of the Nth row and the (N + 1) th row, the Nth row. A reset pulse of the reset transistor 3 (hereinafter abbreviated as an Nth row reset pulse), a read pulse of the Nth row readout transistor 2 (hereinafter abbreviated as an Nth row read pulse), (N + 1) a reset pulse of the reset transistor ( Hereinafter, the states of the (N + 1) th row reset pulse) and the (N + 1) th row readout transistor readout pulse (hereinafter, abbreviated as the (N + 1) th row readout pulse) are shown. The Low level is ground (0V), and the High level is 3V.

FIG. 11 is a diagram showing the potential at each time of the pixel portion described in FIG. In FIG. 11, the vertical axis indicates the low level on the top and the high level on the bottom. First, at time T1 in FIG. 11A, the PD unit 1 has signal charges, the gate of the read transistor 2 is at the low level, the gate of the reset transistor 3 is at the low level, and the VDD power source 6 is at the high level. It has become. At time T2 in FIG. 11B, the gate of the reset transistor 3 is set to the high level, and the FD portion 7 is set to the high level of the voltage of the VDD power source 6. At time T <b> 3 in FIG. 11C, the readout pulse is completed, so that the charge in the PD unit 1 is read out to the FD unit 7. At this time, the gate voltage of the detection transistor 4 changes due to a change in the potential of the FD unit 7, whereby a signal is extracted as a change in the potential of the vertical signal line 5. After the VDD power source 6 becomes low level at time T4 in FIG. 11 (d), the gate of the reset transistor 3 becomes high level again at time T5 in FIG. 11 (e), so that the FD portion 7 becomes low level. Is set. At time T6 in FIG. 11F, the gate of the reset transistor 3 is at a low level. At time T7 in FIG. 11 (g), the VDD power supply 6 is again set to the high level in order to detect the (N + 1) -th row signal. Similarly, from time T8 to time T14, the operation from time T1 to time T7 in the pixels on the Nth row is repeated for the (N + 1) th row.
JP 2003-46846 A

However, the conventional technique has a problem that the following malfunction may occur.
At time T2 in FIG. 11B described in the background art, when the Low level of the FD unit 7 in which the N-th row detection transistor 4 is not selected becomes the High level of the VDD power supply voltage, the FD unit 7 And the gate of the read transistor 2, the gate voltage of the read transistor 2 is also swung in the positive direction at the same time when the FD section 7 suddenly becomes the high level of the VDD power supply 6. . Therefore, the gate of the read transistor 2 is opened, and a part of the charge in the PD portion 1 in the Nth row is released to the FD portion 7 side, and the potential of the PD portion 1 becomes a positive potential. As a result, the charge of the PD unit 1 decreases, and the saturation charge amount of the PD unit 1 decreases.

  Further, at time T7 in FIG. 11 (g), when the VDD power supply 6 becomes high level again, a steep voltage change occurs. Then, because of the coupling capacitance 41 between the VDD power supply 6 and the gate of the reset transistor 3, the gate voltage of the reset transistor 3 is also swung in the positive direction at the same time. As a result, the gate of the reset transistor 3 opens, and some of the electrons in the FD portion 7 escape to the VDD power source 6 side, and the potential of the FD portion 7 becomes a positive potential. Due to the potential change of the FD portion 7, the gate voltage of the detection transistor 4 becomes a positive potential, and the detection transistor 4 that should be turned off is turned on. In the end, the charge detected in the original selected row is added with the erroneously detected charge due to the operation of the non-selected row, so that the original correct charge signal cannot be obtained. There arises a problem that a malfunction that cannot be detected may occur.

  Further, FIG. 12 shows a potential diagram when the reset transistor is a depletion type. When the reset transistor 3 is a depletion type, when the low level of the FD section 7 in which the detection transistor 4 is not selected is set to the high level of the VDD power supply 6 voltage at time T7 in FIG. Since the potential 17 under the gate of the transistor is high, the coupling capacitor 41 between the VDD power supply 6 and the gate of the reset transistor 3 easily causes the voltage of the gate of the reset transistor 3 to be swung in the positive direction. Electrons for non-selection are more likely to spill from the FD portion 7 to the VDD power source 6.

  As described above, the low level of the gate of the readout transistor 2 and the gate of the reset transistor 3 and the P-type semiconductor well layer 13 of the imaging unit are all 0 V. Therefore, at times T2 and T7, the drain region Due to the sudden change to the positive potential and the coupling capacitances 40 and 41 with the drain region, the potential of the gate of the read transistor 2 and the gate of the reset transistor 3 is originally shifted to the positive side, and the imaging unit If the potential of the well layer 13 of the P-type semiconductor is exceeded, a malfunction may occur.

  Therefore, the present invention enables a gate potential of a read transistor and a reset transistor to be appropriately set in a MOS type solid-state imaging device having a circuit for determining row selection and non-selection by a VDD power source, and further, coupling capacitance It is an object of the present invention to provide a solid-state imaging device that prevents a decrease in saturation charge caused by the above-described phenomenon and a malfunction in which an unselected row is erroneously selected.

In order to achieve the above object, a solid-state imaging device according to the present invention is a MOS solid-state imaging device in which a plurality of unit pixels are arranged two-dimensionally on a semiconductor substrate, and photoelectric conversion means for photoelectrically converting incident light A P-type MOS transistor reading means for reading the signal charge obtained by the photoelectric conversion means, a storage means for storing the signal charge read by the reading means, and the signal charge stored by the storage means. The detecting means for detecting, the reset means for the N-type MOS transistor for resetting the signal charge accumulated in the accumulating means, and the low level of the gate of the resetting means, the P of the imaging area under the gate of the resetting means And a potential setting means for setting the potential lower than that of the mold well.

  When the reset means is P-type, the reset means includes a potential setting means for setting a high level of the gate of the reset means higher than the potential of the N-type well in the imaging region under the gate of the reset means. To do.

Further, it is a MOS type solid-state imaging device in which a plurality of unit pixels are two-dimensionally arranged on a semiconductor substrate, and photoelectric conversion means for photoelectrically converting incident light, and N for reading signal charges obtained by the photoelectric conversion means Connected to a pulse-modulated power source, a reading means for the MOS transistor, a storage means for storing the signal charges read by the reading means, a detection means for detecting the signal charges stored by the storage means, and an N-type MOS transistor, and the reset means of the N-type MOS transistor for resetting the accumulated said signal charge in said storage means, the Low level of the gate of the reading means, imaging under the gate of the reading means And a potential setting means for setting the potential lower than the potential of the P-type well in the region.

  In the case where the readout means is P-type, the readout means includes a potential setting means for setting a high level of the gate of the readout means higher than the potential of the N-type well in the imaging region under the gate of the readout means. To do.

Further, it is a MOS type solid-state imaging device in which a plurality of unit pixels are arranged two-dimensionally on a semiconductor substrate, and includes a photoelectric conversion means for photoelectrically converting incident light, and a P for reading out signal charges obtained by the photoelectric conversion means. Type MOS transistor reading means, storage means for storing the signal charges read by the reading means, detection means for detecting the signal charges stored by the storage means, and the signals stored by the storage means An N-type MOS transistor resetting means for resetting the charge and a potential setting means for setting the P-type well potential in the imaging region higher than the P-type well potential in the peripheral circuit region are provided.

  In the case where the reset means is P-type, the reset means includes a potential setting means for setting the N-type well potential in the imaging region to be lower than the N-type well potential in the peripheral circuit region.

  Further, it is a MOS type solid-state imaging device in which a plurality of unit pixels are two-dimensionally arranged on a semiconductor substrate, and photoelectric conversion means for photoelectrically converting incident light, and N for reading signal charges obtained by the photoelectric conversion means Type MOS transistor reading means, storage means for storing the signal charges read by the reading means, detection means for detecting the signal charges stored by the storage means, and the storage means stored by the storage means It is characterized by comprising reset means for resetting signal charges and potential setting means for setting the P-type well potential in the imaging region higher than the P-type well potential in the peripheral circuit region.

  In the case where the reading means is P-type, the reading means includes a potential setting means for setting the N-type well potential in the imaging region to be lower than the N-type well potential in the peripheral circuit region.

  According to the present invention, the P-type well in the imaging region and the P-type well in the peripheral circuit region are separated, the P-type well potential in the peripheral circuit region is set lower than the P-type well potential in the imaging region, Even if there is a coupling capacitance between the gate of the reading means and the storage means, the potential of the gate of the reading means is set so that the potential of the gate of the reading means does not exceed 0V and is shifted to a positive potential. Further, it is possible to prevent the saturation charge from being lowered due to the charge photoelectrically converted by the photoelectric conversion means spilling into the storage means.

  In addition, because of the coupling capacitance between the VDD power supply and the reset means gate, the potential of the reset means gate is 0 V even when the gate voltage of the reset means is swung in the positive direction as in the prior art. As a result, the electrons for deselecting the storage means do not spill from the storage means to the VDD power supply side, preventing the potential level of the storage means in the non-selected row from becoming a positive potential. Thus, the detection means is not turned on, and a malfunction in which an unselected row is selected can be prevented.

  Further, the P-type well potential in the peripheral circuit region is set lower than the low level of the gate of the reset unit and the gate of the readout unit, so that the P-type well layer and the N-type diffusion layer in the peripheral circuit region are reversed. It is possible to prevent a forward leakage current from being generated by biasing.

  Further, since the well in the imaging region and the well in the peripheral circuit region are separated, a means for setting the gate potential of the reading means and the resetting means can be made inside the solid-state imaging device.

  The present invention is also effective when the N-type MOS transistor is a P-type MOS transistor as in the case where the N-type MOS transistor is used for the resetting means, the reading means, and the detecting means.

  In particular, when the reset transistor is N-type, the potential setting circuit can be simplified if the potential of the P-type well in the imaging region or the potential of the P-type well in the peripheral circuit region is set to the ground potential (0 V). When the reset transistor is P-type, the potential setting circuit can be simplified by setting the potential of the N-type well in the imaging region or the potential of the N-type well in the peripheral circuit region to the ground potential (0 V).

  In addition, by using the solid-state imaging device of the present invention for a camera or the like, it is possible to realize an excellent camera or the like that does not malfunction, and its practical value is extremely high.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a diagram showing a cross section and potential setting in the solid-state imaging device according to the present embodiment. This is different from the prior art in that the potential 19 of the P-type well layer 14 in the peripheral circuit region and the potential 18 of the P-type well layer 13 in the imaging unit are set to different potentials. The potential setting unit 50 includes a read pulse generation unit 52, a reset pulse generation unit 53, 0V, and −2V. The read pulse generator 52 sets the potential of the N-type diffusion layer in the peripheral circuit region and the gate of the read transistor 2. The reset pulse generator 53 sets the potential of another N-type diffusion layer in the peripheral circuit region and the gate of the reset transistor 3. The potential 18 of the P-type well layer 13 of the imaging unit is set to 0V. The potential 19 of the P-type well layer 14 in the peripheral circuit region is set to -2V.

  FIG. 2 is a diagram showing a circuit of the readout pulse generator 52 and the reset pulse generator 53 in the solid-state imaging device according to the present embodiment. This circuit supplies voltage pulses having a high level of 3V and a low level of −1V to the gates of the read transistor 2 and the reset transistor 3, respectively. In this circuit, when the high level potential setting input unit 31 is turned on and the low level potential setting input unit 32 is turned off, the high level potential setting transistor 33 is turned on and the low level potential setting transistor 34 is turned off. Therefore, the pulse output unit 35 is set to 3V. On the contrary, when the high level potential setting input unit 31 is turned off and the low level potential setting input unit 32 is turned on, the high level potential setting transistor 33 is turned off and the low level potential setting transistor 34 is turned on. The pulse output unit 35 is set to −1V.

  FIG. 3 shows pixel unit driving timing in the solid-state imaging device according to the present embodiment. The difference between FIG. 3 and FIG. 10 showing the prior art is that the low level potential of the gate of the reset transistor 3 and the gate of the readout transistor 2 is set to −1V, which is lower than 0V of the P-type well layer potential 18 of the imaging unit. It is a point that has been set.

  FIG. 4 is a potential diagram at the pixel unit drive timing of FIG. 4 differs from FIG. 11 in the prior art in two places, FIG. 4 (b) and FIG. 4 (g). At time T2 in FIG. 4B, since the low level potential of the gate of the read transistor 2 is set to −1V, there is a coupling capacitor 40 between the gate of the read transistor 2 and the FD portion 7. However, since the potential of the gate of the read transistor 2 does not exceed 0V and is not shifted to a positive potential, it is possible to prevent the saturation charge from being lowered due to the charge accumulated in the PD portion 1 spilling into the FD portion 7. .

  At time T7 in FIG. 4G, since the low level potential of the gate of the reset transistor 3 is set to −1 V, the low level of the FD portion 7 in which the detection transistor 4 is not selected is set to the VDD power source. Even when the gate voltage of the reset transistor 3 is swung in the positive direction by the coupling capacitor 41 between the VDD power supply 6 and the gate of the reset transistor 3 when the six voltage is set to the high level, the gate of the reset transistor 3 Therefore, the phenomenon that electrons for deselecting the FD section 7 do not spill from the FD section 7 to the VDD power source 6 does not occur even for a moment, and the non-selected row Therefore, it is possible to prevent a malfunction of the selected row when the potential level of the FD portion 7 becomes higher.

  Further, by setting the P-type well potential 19 in the peripheral circuit region to −2 V, the P-type well layer 14 and the N-type diffusion layer in the peripheral circuit region (the same potential as the gate of the reset transistor 3 and the gate of the read transistor 2). A reverse bias can be made between the two and a forward leakage current can be prevented.

  When the reset transistor 3 is a P-type MOS transistor, the high level of the reset transistor 3 is set higher than the potential of the N-type well in the imaging region under the gate of the reset transistor 3 and the peripheral circuit region The object can be achieved by setting the potential lower than the N-type well potential. When the readout transistor 2 is a P-type MOS transistor, the High level of the readout transistor 2 is set higher than the potential of the N-type well in the imaging region under the gate of the readout transistor 2, and the peripheral circuit region The object can be achieved by setting the potential lower than the N-type well potential.

  As described above, according to the solid-state imaging device of the present embodiment, the gate potential of the readout transistor and the reset transistor can be appropriately set, and further, the saturation charge is reduced due to the coupling capacitance and is not selected. Since it is possible to prevent a malfunction in which a row is erroneously selected, it is possible to prevent deterioration of pixel characteristics as in the related art.

(Embodiment 2)
FIG. 5 is a circuit diagram of the pixel portion in the solid-state imaging device of the type having no readout transistor according to the embodiment of the present invention. The PD unit 1 is directly connected to the FD unit 7. The signal charge obtained by the PD unit 1 is directly stored in the FD unit 7. Other operations are the same as those described with reference to FIG.

  Therefore, similarly to the first embodiment of the present invention, the potential of the gate of the reset transistor 3 is set to −1V, which is lower than 0V of the P-type well layer potential 18 of the imaging unit, so that at time T7, the VDD power source 6 and Because of the coupling capacitance 41 between the gate of the reset transistor 3 and the gate voltage of the reset transistor 3 is swung in the positive direction as in the prior art, the gate potential of the reset transistor 3 exceeds 0V. Therefore, electrons for deselecting the FD unit 7 do not spill from the FD unit 7 to the VDD power supply 6 side, and the potential level of the FD unit 7 in the non-selected row becomes a positive potential. This prevents the detection transistor 4 from being turned on, thereby preventing a malfunction in which an unselected row is selected.

(Embodiment 3)
FIG. 6 is a block diagram when any one of the solid-state imaging devices according to the embodiments of the present invention described so far is used in a camera. The camera 20 includes a lens 21, a solid-state imaging device 22a, a drive circuit 23, a signal processing unit 25, and an external interface unit 26. The light that has passed through the lens 21 enters the solid-state imaging device 22a. The signal processing unit 25 drives the solid-state imaging device 22a through the drive circuit 23, and takes in an output signal from the solid-state imaging device 22a. The signal processed by the signal processing unit 25 can be output to the outside through the external interface unit 26. By using the solid-state imaging device according to the first or second embodiment of the present invention, it is possible to realize a camera with excellent saturation characteristics that does not cause a malfunction in which a non-selected row is erroneously selected.

  As described above, the solid-state imaging device and the camera according to the present invention have been described based on the embodiment. However, the present invention is not limited to this embodiment. For example, the present invention is a case where an N-type MOS transistor is used as a reset transistor, a readout transistor, and a detection transistor, respectively, but may be applied when each transistor is a P-type MOS transistor. Further, the set value of the potential is not necessarily −1V or −2V, and the generation circuit is not necessarily described in the embodiment.

  In particular, when the reset transistor is N-type, the potential setting circuit can be simplified if the potential of the P-type well in the imaging region or the potential of the P-type well in the peripheral circuit region is set to the ground potential (0 V). When the reset transistor is P-type, the potential setting circuit can be simplified by setting the potential of the N-type well in the imaging region or the potential of the N-type well in the peripheral circuit region to the ground potential (0 V).

  The solid-state imaging device according to the present invention has an effect of preventing a malfunction due to a decrease in saturation charge and an erroneous selection of a non-selected row due to a coupling capacitance, and is used in a mobile phone, a digital camera, or the like This is useful as a solid-state imaging device.

It is a figure which shows the cross section and electric potential setting in the solid-state imaging device concerning Embodiment 1 of this invention. It is a circuit diagram of the electric potential setting part in the solid-state imaging device concerning Embodiment 1 of the present invention. It is a figure which shows the pixel part drive timing in the solid-state imaging device which concerns on Embodiment 1 of this invention. It is a figure which shows the potential in the solid-state imaging device concerning Embodiment 1 of this invention. It is a circuit diagram of the pixel part in the solid-state imaging device concerning Embodiment 2 of the present invention. It is a block diagram of the camera which concerns on Embodiment 3 of this invention. It is a figure which shows the example of the solid-state imaging device comprised by the conventional MOS transistor. It is a figure which shows the cross section in the conventional solid-state imaging device. It is a pixel circuit diagram in the conventional solid-state imaging device. It is a figure which shows the pixel part drive timing in the conventional solid-state imaging device. It is a figure which shows the potential in each time of the pixel part in the conventional solid-state imaging device. It is a figure which shows the potential in each time of the pixel part of the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photodiode (PD) part 2 Reading transistor 3 Reset transistor 4 Detection transistor 5 Vertical signal line 6 VDD power supply 7 Floating diffusion (FD) part 8 Imaging area 9 Horizontal shift register 10 Vertical shift register 11 Timing generation circuit 12 Output amplifier 13 Imaging P-type well layer in region 14 P-type well layer in peripheral circuit region 15 Conventional P-type well potential 16 N-type substrate 17 Potential under reset transistor gate 18 P-type well potential in imaging region 19 P-type in peripheral circuit region Well potential 20 Camera 21 Lens 22, 22a Solid-state imaging device 23 Drive circuit 25 Signal processing unit 26 External interface unit 31 High level potential setting input unit 32 Low level potential setting input unit 33 High level potential Setting transistor 34 Low level potential setting transistor 35 Pulse output unit 40 Coupling capacitor 41 Coupling capacitor 50 Potential setting unit 52 Read pulse generating unit 53 Reset pulse generating unit

Claims (5)

A MOS type solid-state imaging device in which a plurality of unit pixels are arranged two-dimensionally on a semiconductor substrate,
Photoelectric conversion means for photoelectrically converting incident light;
N-type MOS transistor reading means for reading the signal charge obtained by the photoelectric conversion means;
Storage means for storing the signal charges read by the reading means;
Detection means for detecting the signal charge accumulated in the accumulation means;
N-type MOS transistor resetting means for resetting the signal charge stored in the storage means;
A solid-state imaging device comprising: a potential setting unit that sets a low level of the gate of the reset unit to be lower than a potential of a P-type well in an imaging region under the gate of the reset unit. A MOS type solid-state imaging device in which a plurality of unit pixels are arranged two-dimensionally on a semiconductor substrate,
Photoelectric conversion means for photoelectrically converting incident light;
P-type MOS transistor readout means for reading out signal charges obtained by the photoelectric conversion means;
Storage means for storing the signal charges read by the reading means;
Detection means for detecting the signal charge accumulated in the accumulation means;
P-type MOS transistor resetting means for resetting the signal charge stored in the storage means;
A solid-state imaging device comprising: a potential setting unit that sets a high level of the gate of the reset unit to be higher than a potential of an N-type well in an imaging region under the gate of the reset unit. Potential setting means for setting the P-type well potential in the imaging region higher than the P-type well potential in the peripheral circuit region
The solid-state imaging device according to claim 1, further comprising: Potential setting means for setting the N-type well potential in the imaging region to be lower than the N-type well potential in the peripheral circuit region;
The solid-state imaging device according to claim 2, further comprising: The camera using the solid-state imaging device of any one of Claims 1-4.

Images