JP4072526B2 - Solid-state imaging device, camera, power supply device and method thereof - Google Patents

Description

  The present invention relates to a MOS type solid-state imaging device used for a digital camera or the like.

Conventionally, various types of MOS solid-state imaging devices have been proposed (see, for example, Patent Document 1).
FIG. 10 is a diagram illustrating a configuration example of a conventional solid-state imaging device including MOS transistors. The solid-state imaging device 22 includes a photodiode portion (hereinafter abbreviated as “PD portion”) 1 that photoelectrically converts incident light on a semiconductor substrate, a read transistor 2 that reads signal charges obtained from the PD portion 1, and a read operation. Floating diffusion part (hereinafter abbreviated as “FD part”) 7 for storing the signal charge read out by the transistor 2, detection transistor 4 for detecting the signal charge accumulated in the FD part 7, accumulated in the FD part 7 An imaging region 8 (a region indicated by a broken line in FIG. 10) is provided in which amplification type unit pixels each having a reset transistor 3, a vertical signal line 5, and a VDD power source 6 for resetting signal charges are arranged two-dimensionally. Here, a portion indicated by a two-dot chain line in FIG. 10 is a “pixel portion (also referred to as a unit pixel)” 14 constituting a circuit of one pixel unit.

  Further, the solid-state imaging device 22 includes a horizontal shift register 9 that selects a pixel column by a vertical signal line 5, a vertical shift register 10 that selects a pixel row, a timing generation circuit 11 that supplies pulses necessary for driving, and an output amplifier 12. Prepare.

  FIG. 11 is a schematic diagram including a cross section of the pixel portion 14 in FIG. In FIG. 11, the PD unit 1, the VDD power source 6, and the FD unit 7 are made of an N-type semiconductor and are formed on a well layer 13 of a P-type semiconductor. The gates of the read transistor 2 and the reset transistor 3 are polysilicon electrodes. Although the cross section of the detection transistor 4 is not shown in FIG. 11, the source and drain of the detection transistor 4 are made of an N-type semiconductor, and the gate is a polysilicon electrode. The VDD power source 6 is connected to the drain of the detection transistor 4 and the drain of the reset transistor 3.

  FIG. 12 is a circuit diagram showing each element in FIG. The signal charge photoelectrically converted by the PD unit 1 is accumulated in the PN junction capacitor 1 a of the PD unit 1, and then read out to the PN junction capacitor 7 a of the FD unit 7 by the read transistor 2. Since the FD portion 7 is mainly composed of a PN junction capacitance, the potential of the FD portion 7 is determined by the amount of the read electric charge, whereby the gate voltage of the detection transistor 4 is changed to change the vertical signal line. A signal is taken out as a potential change of 5.

  FIG. 13 is a diagram illustrating the driving timing of the pixel unit 14 in the prior art. FIG. 13 shows a voltage pulse of the VDD power source 6 (hereinafter abbreviated as “VDD pulse”) and a reset pulse of the N-th row reset transistor 3 (hereinafter “N”) during the operations of the N-th and (N + 1) -th rows. Abbreviated as “row reset pulse”), a readout pulse of the Nth row readout transistor 2 (hereinafter abbreviated as “Nth row readout pulse”), (N + 1) a reset pulse of the reset transistor (hereinafter referred to as “N + 1 row reset”). The pulse is abbreviated as “pulse” and the read pulse of the (N + 1) -th row read transistor (hereinafter abbreviated as “N + 1-th row read pulse”).

FIGS. 14A to 14G are diagrams showing potentials at times T1 to T7 of the respective portions of the pixel portion 14 corresponding to FIG. 14A to 14G, the upper level is indicated as “Low level”, and the lower level is indicated as “High level”. First, at time T1 in FIG. 14A, the PD unit 1 has signal charge, the gate of the read transistor 2 is low level, the gate of the reset transistor 3 is low level, and the VDD power supply 6 is high level. Yes. At time T <b> 2 in FIG. 14B, the gate of the reset transistor 3 becomes High level, so that the FD unit 7 is set to the High level of the voltage of the VDD power supply 6. At time T <b> 3 in FIG. 14C, since the read pulse is completed (that is, low level), the charge in the PD unit 1 is read out to the FD unit 7. At this time, when the gate voltage of the detection transistor 4 changes due to the potential change of the FD portion 7, a signal is extracted as the potential change of the vertical signal line 5. After the VDD power source 6 becomes low level at time T4 in FIG. 14D, the gate of the reset transistor 3 again becomes high level at time T5 in FIG. 14E, so that the FD portion 7 becomes low level. Is set. At time T6 in FIG. 14F, the gate of the reset transistor 3 is at a low level. At time T7 in FIG. 14 (g), the VDD power supply 6 again goes to the high level in order to detect the (N + 1) -th row signal. Similarly, from time T8 to time T14, the operation from time T1 to time T7 in the pixel on the Nth row is repeated for the (N + 1) th row.
JP 2003-46864 A

However, the conventional technique has a problem that the following malfunction may occur.
At time T7 in FIG. 14 (g) described in the background art, a steep voltage change occurs when the VDD power supply 6 again becomes a high level. Then, because of the coupling capacitance 41 between the VDD power supply 6 and the gate of the reset transistor 3, the gate voltage of the reset transistor 3 is also swung in the positive direction at the same time. As a result, the gate of the reset transistor 3 opens, and some of the electrons in the FD portion 7 escape to the VDD power source 6 side, and the potential of the FD portion 7 becomes a positive potential. Due to the potential change of the FD portion 7, the gate voltage of the detection transistor 4 becomes a positive potential, and the detection transistor 4 that should be turned off is turned on. As a result, a malfunction occurs in which the charge detected in the originally selected row is affected by the row in which the originally non-selected row is selected, and the original correct charge signal cannot be obtained. For example, bright light is emitted. There arises a problem that a malfunction that cannot be detected may occur.

  Therefore, the present invention provides a solid-state imaging device and the like that prevent malfunctions in which a non-selected row is selected in a MOS type solid-state imaging device having a circuit that determines whether a row is selected or not by a VDD power supply. For the purpose.

In order to achieve the above object, a solid-state imaging device according to the present invention is a MOS type solid-state imaging device configured on a semiconductor substrate, which photoelectrically converts incident light and obtains signal charges obtained by the photoelectric conversion. A plurality of unit pixels having a storage means for storing the signal charge and a reset means including a MOS transistor for resetting the signal charge stored in the storage means in accordance with a reset signal, and a power supply voltage serving as a reset voltage for the reset means For the coupling capacitance by adding a predetermined time slope to the period related to the change of the power supply voltage from the non-detection potential to the detection potential. The charging / discharging of the signal charge accumulated in the accumulation means is suppressed.
As a result, the period of the voltage of the VDD power supply from the non-detection potential (Low level) to the detection potential (High level) is lengthened, thereby resetting for the coupling capacitance between the VDD power supply side and the gate of the reset means. It is possible to prevent the gate voltage of the means from being simultaneously swung in the positive direction, and finally, it is possible to prevent a malfunction in which a non-selected row is selected.

Note that the present invention can be realized not only as such a solid-state imaging device but also as a power supply method for the solid-state imaging device.
According to the present invention, in the MOS type solid-state imaging device, by increasing the period during which the voltage of the VDD power supply is changed from the Low level to the High level, the coupling capacitance between the VDD power supply side and the gate of the reset unit is increased. In addition, the gate voltage of the reset means is not swung in the positive direction at the same time as in the prior art. For this reason, electrons for deselecting the storage means do not spill from the storage means to the VDD power supply side, preventing the potential level of the storage means in the non-selected row from becoming a positive potential and turning on the detection means. Therefore, it is possible to prevent a malfunction in which an unselected row is selected.

  The present invention is a case where an N-type MOS transistor is used for each of resetting means, reading means, and detecting means, but it is also effective when these means are P-type MOS transistors.

  In addition, by using the solid-state imaging device of the present invention for a camera or the like, it is possible to realize an excellent camera or the like that does not malfunction, and its practical value is extremely high.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
(Embodiment 1)
In the configuration of the solid-state imaging device 122 (not shown) according to Embodiment 1 of the present invention, the position where power is supplied as the VDD power supply 6 shown in FIGS. The power supply output unit 60 in FIG. 1 is replaced with the position 60a in the present invention, but the rest of the configuration is the same. Details of the position 60a for supplying VDD power will be described with reference to FIG.
FIG. 1 is a circuit diagram of an output unit of the VDD power supply circuit 65 in the solid-state imaging device 122 according to Embodiment 1 of the present invention. When the resistor 30 is connected in series after the VDD power supply output unit 60, because of the capacitor 35 connected to the position 60a, the change in the rising period and the falling period of the power supply pulse is moderated at the position 60a via the resistor 30, respectively. Can be. A position 60a after passing through the resistor 30 is set as a power supply position in the solid-state imaging device 122 of FIG.

  FIG. 2 is a diagram illustrating the drive timing of the pixel unit 14 in the solid-state imaging device 122 according to Embodiment 1 of the present invention. The difference from the prior art is that the rise period and fall period of the VDD pulse are longer (that is, the VDD pulse rises slowly and falls slowly). As shown in FIG. 1, by setting the position where the VDD power is supplied to a position 60a, the VDD pulse rise period and fall period such as time T3 to time T4, time T7 to time T8, and time T10 to time T11 are used. The inclination of the waveform is made dull (that is, a temporal inclination is added) compared to the inclination of the waveform in the solid-state imaging device 22 of the prior art shown in FIG.

  FIG. 3 is a diagram illustrating the relationship of “the potential of the FD unit” with respect to “the rise time of the VDD power supply” in the solid-state imaging device 122 according to Embodiment 1 of the present invention. When the rise time of the VDD power supply is set to 5 nanoseconds, the potential of the FD section 7 becomes 10% of the amplitude of the VDD power supply, which is equal to or lower than the threshold value of the detection transistor 4, and it can be seen that the stability is achieved. Furthermore, when the rise time of the VDD power supply is set to 10 nanoseconds, the potential of the FD unit 7 becomes 5% of the amplitude of the VDD power supply, and a margin for the threshold value of the detection transistor 4 can be taken. Further, when the time is 25 nanoseconds, the potential of the FD unit 7 can be set to the low level of the VDD power source, and the detection transistor 4 connected to the FD unit 7 is completely stabilized. Therefore, the rise time of the VDD power supply is preferably 5 nanoseconds or more.

  FIG. 4 is a diagram showing a relationship of “the potential of the FD portion in the Nth row at time T8” with respect to “the maximum value of the gradient during the rising period of the VDD power supply” in the solid-state imaging device 122 according to Embodiment 1 of the present invention. is there. When the maximum value of the slope in the rise period of the VDD power supply is set to 0.15 volts / nanosecond, the potential of the FD portion 7 in the Nth row at time T8 becomes 10% of the amplitude of the VDD power supply, which is below the threshold of the detection transistor 4 It turns out that it becomes stable. Further, when the maximum value of the slope in the rise period of the VDD power supply is set to 0.1 volt / nanosecond, the potential of the FD section 7 becomes 5% of the amplitude of the VDD power supply, so a margin for the threshold value of the detection transistor 4 is taken. Can do. Further, when the maximum value of the slope in the rising period of the VDD power supply is set to 0.02 volts / nanosecond, the potential of the FD section 7 can be set to the low level of the VDD power supply, so that the detection transistor connected to the FD section 7 4 is completely stable. Therefore, it is preferable that the maximum value of the slope in the rising period of the VDD power source is 0.15 volts / nanosecond or less.

  If the value of the resistor 30 in FIG. 1 is adjusted, the “VDD power supply rise time” shown in FIG. 3 and the “maximum slope value during the VDD power supply rise period” shown in FIG. Can be set to a value.

  FIG. 5 is a diagram illustrating the potential at each time of each unit of the pixel unit 14 in the solid-state imaging device 122 according to Embodiment 1 of the present invention. FIGS. 5A to 5F are the same as FIGS. 14A to 14F of the prior art. However, as shown in FIG. 5G, during the period from time T7 to time T8, which is the rising period of the VDD pulse, the VDD pulse is gradually changed from the low level (also referred to as “non-detection potential”) to the high level. (Also referred to as “detection potential”), when the voltage at the position 60a changes from the low level to the high level even when there is the coupling capacitor 41 between the VDD power source 6 and the gate of the reset transistor 3. In addition, the gate voltage of the reset transistor 3 is not greatly swung in the positive direction.

  Therefore, it is possible to avoid the conventional problem that some of the electrons in the FD section 7 are lost to the VDD power supply side. As a result, the low level of the voltage at the position 60a can be set so that the FD portion 7 is stabilized, so that the gate voltage of the detection transistor 4 becomes a positive potential, and the potential of the originally unselected FD portion 7 becomes high, and the selected row It is possible to prevent malfunctions that occur.

As described above, according to the solid-state imaging device according to the embodiment of the present invention, it is possible to prevent a malfunction in which an unselected row is erroneously selected.
(Embodiment 2)
FIG. 6 is a diagram showing the drive timing of the pixel unit 14 in the solid-state imaging device 222 (not shown) according to Embodiment 2 of the present invention. A difference from FIG. 2 of the first embodiment is that a ramp waveform is used for the waveform in the rising and falling periods of the VDD pulse. The ramp waveform in this case can be easily realized by using a generally well-known ramp waveform generation circuit.

The slope at the time when the VDD pulse rises during the period from time T7 to time T8 in FIG. 6 greatly affects the potential fluctuation of the potential of the FD portion 7. Supply a ramp waveform whose duration from Low level to High level is longer than 5 nanoseconds, or a ramp waveform whose time derivative in the duration from Low level to High level is less than 0.15 volts / nanosecond Thus, the gate potential of the detection transistor 4 connected to the FD unit 7 is completely stabilized at the non-detection potential. Further, when the ramp waveform is used not only in the rising period but also in the falling period, the same ramp waveform generating circuit can be used in both periods, so that the efficiency of the circuit can be improved.
(Embodiment 3)
The solid-state imaging device 322 (not shown) according to the embodiment of the present invention is different from the solid-state imaging device 122 according to the first embodiment only in the circuit of the output unit of the VDD power supply circuit 65.

  FIG. 7 is a circuit diagram of an output unit of the VDD power supply circuit 65 in the solid-state imaging device 322 according to the embodiment of the present invention. The resistor 31 is connected in series to the VDD power output unit 60, and the capacitor 32 and the power pulse resetting transistor 33 are connected to the position 60b after the resistor 31 as shown in FIG. When the power pulse rises, if the power pulse reset input 34 connected to the gate of the power pulse reset transistor 33 is turned off, there is a capacitor 32 connected to the position 60b. At the position 60b, the VDD pulse can be gradually changed. Further, at the time of falling, by turning on the power pulse reset input unit 34, the charge accumulated in the capacitor 32 can be rapidly lowered to a low level, so that a steep falling can be realized. The position 60b after the resistor 31 is used as a power supply position instead of the VDD power output unit 60 of the solid-state imaging device 22 in FIG.

FIG. 8 is a diagram illustrating the drive timing of the pixel unit 14 in the solid-state imaging device according to Embodiment 3 of the present invention. As shown in FIG. 8, in the solid-state imaging device 322, the ramp waveform is used only during the rising period of the VDD pulse from time T7 to T8. Even if the fall is a steep voltage change, no malfunction occurs in the solid-state imaging device 322. Therefore, the whole drive time can be shortened by making the fall period from time T10 to time T11 steep. it can. In addition, since the slope of the ramp waveform rising during the rising period from time T7 to T8 can be reduced, the voltage of the FD unit 7 is stabilized. As a result, the gate voltage of the detection transistor 4 connected to the FD unit 7 is completely stabilized at the non-detection potential.
(Embodiment 4)
FIG. 9 is a block diagram when one of the solid-state imaging devices 122, 222, or 322 (referred to as 22a for convenience) according to the embodiments of the present invention described so far is used in a camera. The camera 20 includes a lens 21, a solid-state imaging device 22a, a drive circuit 23, a signal processing unit 25, and an external interface unit 26. The light that has passed through the lens 21 enters the solid-state imaging device 22a. The signal processing unit 25 drives the solid-state imaging device 22a through the drive circuit 23, and takes in an output signal from the solid-state imaging device 22a. The signal processed by the signal processing unit 25 is output to the outside through the external interface unit 26. By using the solid-state imaging device 122, 222, or 322 according to the first to third embodiments of the present invention, it is possible to realize a camera that does not cause a malfunction in which a non-selected row is erroneously selected.

  As described above, the solid-state imaging device and the camera according to the present invention have been described based on the embodiment. However, the present invention is not limited to this embodiment. For example, in the present invention, an N-type MOS transistor is used as a reset transistor, a readout transistor, and a detection transistor, but a P-type MOS transistor may be applied to each transistor. However, in this case, since the polarity of each signal is inverted, the “period from the low level to the high level” described in the first to third embodiments is replaced with the “period from the high level to the low level”. It is necessary to pay attention to changes at each level.

  Note that the circuit that realizes the gentle rise and fall of the VDD pulse may be other than the circuit shown in this embodiment.

  The solid-state imaging device according to the present invention has an effect of preventing a malfunction in which an unselected row is erroneously selected when determining row selection and non-selection by a VDD power source, and is used for a mobile phone, a digital camera, and the like. This is useful as a MOS type solid-state imaging device.

It is a circuit diagram of the output part of the VDD power supply circuit in the solid-state imaging device according to the first embodiment of the present invention. It is a figure which shows the drive timing of the pixel part in the solid-state imaging device concerning Embodiment 1 of this invention. It is a figure which shows the potential of the FD part with respect to the rise time of VDD power supply in the solid-state imaging device concerning Embodiment 1 of this invention. It is a figure which shows the potential of the FD part with respect to the maximum value of the inclination in the rising period of VDD power supply in the solid-state imaging device which concerns on Embodiment 1 of this invention. (A)-(g) is a figure which shows the potential in T1-T7 of each part of the pixel part in the solid-state imaging device concerning Embodiment 1 of this invention. It is a figure which shows the drive timing of the pixel part in the solid-state imaging device concerning Embodiment 2 of this invention. It is a circuit diagram of the output part of VDD power supply circuit in the solid-state imaging device concerning Embodiment 3 of this invention. It is a figure which shows the drive timing of the pixel part in the solid-state imaging device which concerns on Embodiment 3 of this invention. It is a block diagram of the camera which concerns on Embodiment 4 of this invention. It is a figure which shows the structural example of the conventional solid-state imaging device comprised by the MOS transistor. It is a schematic diagram including the cross section of the pixel part in the conventional solid-state imaging device. It is the circuit diagram shown about each element in the conventional solid-state imaging device. It is a figure which shows the drive timing of the pixel part in the conventional solid-state imaging device. (A)-(g) is a figure which shows the potential in T1-T7 of each part of the pixel part in the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photodiode (PD) part 2 Read-out transistor 3 Reset transistor 4 Detection transistor 5 Vertical signal line 6 VDD power supply 7 FD part 7a PN junction capacity 8 Imaging area 9 Horizontal shift register 10 Vertical shift register 11 Timing generation circuit 12 Output amplifier DESCRIPTION OF SYMBOLS 13 Well layer 14 Pixel part 20 Camera 21 Lens 22 Solid-state imaging device 22a Solid-state imaging device 23 Drive circuit 25 Signal processing part 26 External interface part 30 Resistor 31 Resistor 32 Capacitor 33 Power supply pulse reset transistor 34 Power supply pulse reset input part 35 Capacitor 41 Coupling capacity 60 VDD power supply output unit 60a position 60b position 65 VDD power supply circuit

Claims (4)

Arranging a plurality of unit pixels on a semiconductor substrate two-dimensionally, a MOS type solid-state imaging device to determine the selection of the row and unselected and the supply voltage,
Photoelectric conversion means for photoelectrically converting incident light;
Reading means for reading the signal charge obtained by the photoelectric conversion means;
Storage means for storing the signal charges read by the reading means;
Detection means for detecting the signal charge accumulated in the accumulation means;
Resetting means for resetting the signal charge accumulated in the accumulating means according to a reset signal;
Said reset means, the reset voltage, and a power supply means for supplying a voltage pulse of the supply voltage,
The photoelectric conversion means, the readout means, the storage means, the detection means, and the reset means are included in the unit pixel,
The readout means, the detection means and the reset means include a MOS transistor,
The power supply means has a coupling capacitance between the gate of the MOS transistor in the reset means and the power supply voltage, and the time required for the change from the low level potential to the high level potential during the rising edge of the voltage pulse Is a solid-state imaging device characterized by being longer than 5 nanoseconds. Arranging a plurality of unit pixels on a semiconductor substrate two-dimensionally, a MOS type solid-state imaging device to determine the selection of the row and unselected and the supply voltage,
Photoelectric conversion means for photoelectrically converting incident light;
Reading means for reading the signal charge obtained by the photoelectric conversion means;
Storage means for storing the signal charges read by the reading means;
Detection means for detecting the signal charge accumulated in the accumulation means;
Resetting means for resetting the signal charge accumulated in the accumulating means according to a reset signal;
Said reset means, the reset voltage, and a power supply means for supplying a voltage pulse of the supply voltage,
The photoelectric conversion means, the readout means, the storage means, the detection means, and the reset means are included in the unit pixel,
The readout means, the detection means and the reset means include a MOS transistor,
The power supply means has a coupling capacitance between the gate of the MOS transistor in the reset means and the power supply voltage, and the slope in the rising period of the voltage pulse is smaller than 0.15 V / nanosecond. Solid-state imaging device. In the power supply means, the time required for the change from the low level potential to the high level potential during the rising period of the voltage pulse is the change from the high level potential to the low level potential during the falling period of the voltage pulse. 3. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is longer than a time required for. The solid-state imaging device according to claim 1, wherein the power supply unit supplies the power supply voltage to all the unit pixels.

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