JP4496912B2 - Measurement and evaluation method for field effect transistor - Google Patents

Description

  The present invention relates to a transistor measurement and evaluation apparatus that represents an alternating current operation of a transistor such as a field effect transistor and a method thereof.

The problem is that an accurate model that can represent the AC operation of a transistor such as a MOSFET (Metal Oxide Semiconductor) is not possible, and the target performance cannot be obtained when manufacturing an integrated circuit or the like. Inviting results such as.
In many cases, an equivalent circuit of an operating point bias is generally used as a means for expressing the operation of a transistor. For example, when obtaining an equivalent circuit parameter under an operating point bias in an FET, parasitic resistances such as a gate, a drain, and a source are values calculated from measured values under a condition called cold bias.

FIG. 22 shows a specific configuration example of a conventional MOSFET equivalent circuit. Here, an equivalent circuit limited to an element structure excluding external parasitic capacitance and parasitic inductance such as an FET package is shown.
A resistor _Rg is connected between the FET input terminal TG and the internal gate G0, and a gate-source capacitor _Cgs and a matching resistor _Rgs are connected in series between the internal G0 and the internal source S0. The parasitic source resistance R _s is connected between S0 and the source output terminal TS.
Between the internal gate G0 and the internal drain D0, a gate-drain capacitance C _dg and a resistor R _gd are connected in series.
A conductance g _m , a drain / source resistance r _ds , and a drain / source capacitance C _ds are connected in parallel between the internal drain D 0 and the internal source S 0.
Further, a parasitic drain resistance _Rd is connected between the internal drain D0 and the FET output terminal TD.
The parasitic source resistance R _s and the parasitic drain resistance R _d are resistance parts having no bias dependence, and R _gs and R _gd are bias dependence and need to be adjusted according to the operating frequency.

  Further, even when the FET is set to a bias condition that is actually used and, for example, the S (scattering) parameter is measured, the S parameter differs if the operation bias is different, and the equivalent circuit obtained from the S parameter cannot be used. There are drawbacks.

In order to obtain the equivalent circuit of the FET, the cold bias method is used in addition to the parameter measurement in the above-described operation state. In this call bias method, different gate voltages are applied to the FET, and the parameters of each element are measured in that state. For example, it is difficult to extract g _m because of the amplification effect in FET, and the bias voltage is adjusted to lower the drain voltage to near 0V to set the operation state so that g _m can be ignored, and other parameters are extracted. ing. However, the constant of the parameter of each element using this method has a drawback that the error is large.

  The conventional method has made a basic mistake to apply a resistance value that does not vary with bias obtained under cold bias conditions, even for resistance components with high bias dependency such as drain and source resistance, so the equivalent circuit model that has been completed And the actual FET operation did not necessarily match. It was also a problem to use it for equivalent circuit parameters obtained from other than the target operating point bias.

In this way, the movement of the conventional equivalent circuit model and the mismatch of the actual FET operation are dealt with by an easy complexity of the equivalent circuit, and a large amount of time and effort is required to calculate complicated or lower circuit parameters. And spending time.
Japanese Patent Laid-Open No. 3-105268 JP-A-6-266789

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a transistor measurement evaluation apparatus and method for deriving an accurate equivalent circuit model representing the AC operation of the transistor.

  The present invention is a method for measuring and evaluating a transistor having a parasitic element and a core transistor excluding the parasitic element by a storage means for storing data and a control means for performing arithmetic processing on the data according to a program, the control means Are obtained in the second step from the first step of measuring the frequency characteristics of the transistor and converting the impedance, the second step of obtaining the parasitic resistance from the impedance-converted parameter, and the impedance parameter. A third step of subtracting the parasitic resistance; a fourth step of obtaining an admittance parameter by converting the impedance parameter obtained in the third step; and obtaining another parasitic resistance from the admittance parameter; and the impedance From the parameters, the fourth step A fifth step of subtracting the other parasitic resistance obtained in step 5, a sixth step of converting the parameter obtained in the fifth, and the parameter of the core transistor from the parameter obtained in the sixth step. And a seventh step for obtaining the value of the component.

In the conventional analysis of the equivalent circuit, the S parameter such as the cold bias condition as well as the S parameter frequency characteristic under the desired bias condition is necessary. However, in the equivalent circuit presented this time, the S parameter at the desired operating point is not necessary. Only measurements are required, and no special software such as an optimizer to optimize parameters is required. As a result, the time and effort required for modeling are not required.
In addition, the configuration of the equivalent circuit is relatively simple, making it easy for designers to use and predicting frequency bands and the like.
Furthermore, since the equivalent circuit matches the measured value with high accuracy, highly accurate circuit design can be realized in a short time.

An equivalent circuit 10 of the field effect transistor of the present invention will be described with reference to FIG.
FIG. 1 shows a specific configuration example of a MOSFET equivalent circuit according to an embodiment of the present invention. Here, an equivalent circuit limited to an element structure excluding external parasitic capacitance and parasitic inductance such as an FET package is shown.
An equivalent gate resistance _Rg is connected between the input terminal TG of the MOSFET and the internal gate G0, and a gate-source capacitance _Cgs is connected between the internal gate, the internal G0, and the internal source S0. Further, an equivalent source resistance Rs is connected between the internal S0 and the source output terminal TS.
A gate-drain capacitance _Cdg is connected in series between the internal gate G0 and the internal drain D0.
A conductance g _m , a drain / source resistance r _ds , and a drain / source capacitance C _ds are connected in parallel between the internal drain D 0 and the internal source S 0.
Further, an equivalent drain resistance _Rd is connected between the internal drain D0 and the FET output terminal TD.

When the Z parameter and the Y parameter are used for the equivalent circuit of the MOSFET of FIG. 1, the equivalent circuit shown in FIG. 2 is obtained. Although an example of a MOSFET will be described here, other FETs such as JFET, HEMT, SBFET, etc. may be used.
The equivalent gate resistance _{Z g} in _{R g,} the equivalent source resistance _{Z s} to _{R s,} the equivalent drain resistance Zd correspond respectively to Rg.
In the Y parameter, Y _gs corresponds to C _gs , Y _gd corresponds to C _gd , Y _ds corresponds to admittance in which C _ds and R _ds are connected in parallel, and Y _gm corresponds to g _m .
The core portion of the FET composed of the Y parameters excluding Z impedance Z _g , Z _s , and Z _d is shown in FIG. 3 and will be referred to as a core (Core) FET for convenience.
Thus, the total FET equivalent circuit is obtained by adding the resistance component and the induction component Z _g , Z _s , and Z _d in series to the core FET.
The FET equivalent circuit shown in FIGS. 1, 2 and 3 is similar to the equivalent circuit of the conventional example shown in FIG. 22 and its parameter calculation method, but the values of components (elements) and their handling are different.
In particular, unlike the conventional example, the equivalent gate, source, and drain resistances have a significant feature in that they do not have an assumption that they do not depend on DC bias.

Next, in order to obtain the constant of each component of the FET, the Y parameter of the core FET is obtained and then combined with the Z parameter other than the core.
As shown in FIG. 4, first, the Y parameter of the core FET is converted into a Z parameter, and the converted Z parameter is connected in circuit with the Z parameter other than the core FET. To combine).
As shown in FIG. 4, a specific calculation can be performed by replacing Z parameters with each other, and Y _core must be converted into an inverse matrix and converted into Z parameters. (Here, it is assumed that the inverse matrix of Y _core is established.) The Y parameter Ycore of the core FET is converted into a Z parameter (1 / Y _core ), and it is combined with Z _g , Z _s , and Z _d . Thus, the Z parameter of the FET total is obtained.

  The Z parameter of the core FET is

  The Z parameter of the total FET is

となる。

It becomes.

In the equivalent circuit parameter calculation method of FET, a method of deriving a complicated equivalent circuit as shown in FIG. 2 using a simple circuit configuration including three elements C _EP , R _EP , and R _ES shown in FIG. State.
First, a description will be given of the circuit configuration including the above-described three elements, the operation thereof, and the principle of calculating circuit parameters by a geometric method.
In the circuit shown in FIG. 5, the total impedance Z of the circuit is

When M = 1 + ω ² * C _EP ² * R _EP ² is rewritten (hereinafter, the symbol “*” indicates multiplication),

It can be expressed as. When the equation of Equation 4 is displayed in coordinates on the complex surface,

と表される。

It is expressed.

In general, when Expression 5 is drawn on the complex plane, as shown in FIG. 6, when the frequency is changed from 0 to infinity, the locus of the impedance Z becomes a semicircle.
When the frequency is 0 (ω = 0) and the frequency is very low, the impedance Z is

Z (ω = 0) = R _ES + R _EP

It becomes.
The impedance Z when the frequency is infinite (ω = ∞) or the frequency is very high is

Z (ω = ∞) = R _ES

It becomes.
The center of this semicircle is R _ES + R _EP / 2.

Therefore, since the start point of the locus of impedance Z in FIG. 6 is (R _ES + R _EP , 0) and the end point is (RES, 0), the center of this semicircle is ((R _ES + R _EP ) / 2, 0).
In order to confirm whether or not the locus of this impedance Z is a circle, the locus of the broken line in FIG. 6 is shifted to the origin side by R _ES + R _EP / 2, and the center of the circle is taken as the origin on this complex plane. What is necessary is just to obtain | require the distance with the line which the impedance Z draws centering on.
The coordinates after moving are

The field effect transistor measurement and evaluation method of the present invention includes a storage means for storing data, and a control means for calculating and processing the data in accordance with a program, and an equivalent source resistance, equivalent drain resistance and equivalent gate resistance of the field effect transistor , the equivalent source resistance, a measurement and evaluation method of a field effect transistor having a core transistor excluding the equivalent drain resistance and equivalent gate resistance, with said control unit measures the frequency characteristics of the field effect transistor, S parameters A first step of converting from (scattering parameter) to a Z parameter; a second step of obtaining the equivalent source resistance and equivalent drain resistance from the frequency trajectory of the Z parameter ; and the second step from the matrix of the Z parameter. Equivalent to the equivalent source resistance obtained in the step A third step of subtracting the matrix component of the drain resistance ;
An admittance parameter is obtained by converting the Z parameter obtained in the third step, the fourth step of obtaining the equivalent gate resistance from the admittance parameter, and a matrix of Z parameters obtained in the third step. wherein a fifth step of subtracting the matrix elements of the equivalent gate resistance, the sixth step of converting the Z parameter obtained in the fifth step the admittance parameter, said sixth admittance parameters obtained in step Then, the seventh step of calculating the values of the constituent elements of the core transistor is performed .

It becomes. The square of the distance between the coordinates of the equation 6 and the origin is the following equation:

It is represented by In this equation (Formula 7), it can be seen that the distance from the origin to the impedance Z is always constant regardless of the frequency (ω). That is, the locus of impedance Z of the circuit constituted by R _ES , R _EP , and C _EP shown in FIG. 5 draws a circle on the complex plane, and its radius is R _EP / 2.

Next, the principle of calculating the parameter Z of the equivalent circuit by a geometric method will be described. 6 As described above, when it is found that the impedance Z of the circuit composed of the three elements C _EP , R _EP , and R _ES draws a circle on the complex plane, geometrical methods such as a minimum phase check method and an intercept frequency detection method are used. The parameters of the equivalent circuit can be calculated by a simple method.
FIG. 7 shows how to obtain parameters by the minimum phase check method. In FIG. 7, a tangent line is drawn from the origin of the complex plane to the impedance Z, and the angle between the tangent line and the real axis is obtained. When this angle is θ, the above three elements are respectively

R _ES = | Z ₀ | * (1 + Sinθ) / Cosθ

R _EP = -2 * | Z ₀ | * Tanθ

C _EP = | Z ₀ | / ω ₀ * R _ES * R _EP

It can be asked.
However, | Z ₀ |, θ, and ω ₀ are values at the minimum phase point.

The intercept frequency detection method is a method of calculating the diameter and radius of the impedance Z from the maximum resistance (R _EP + R _ES ) and the minimum value Xmin of the reactance, and calculating R _EP and R _ES , but detailed description is omitted here. To do.

A method for deriving the parameters of the core FET of the equivalent circuit of the FET shown in FIG. 1 will now be described using the characteristics of the above-described three-element structure circuit and the calculation method of the element. In calculating each parameter of the FET, inductive components such as wiring are removed in advance.
Z ₂₂ of the impedance Z in the equation (2), that is, the output impedance Z ₂₂ when the input terminal is open may be ignored because the input of R _g is open, and as a result, C _gd and C _gs are connected in series. Therefore, these two capacitors can be combined and expressed as one capacitor. Further, in FIG. 1, C _ds between the internal drain D0 and the internal source S0 is connected in parallel. Therefore, this C _ds is added (combined) to the above-described one capacity and expressed as a total capacity C _EP. be able to.
As a _{result, C EP} is connected in parallel with _{r ds, R S} and _{R d} is connected to an equivalent circuit in both ends. Here, when r _ds is regarded as R _EP , a resistance R _ES combining R _S and R _d , the circuit finally becomes the same as FIG.
From this, R _S + R _d can be obtained, but the values of the individual parameters R _S and R _d and other parameters cannot be calculated.

In addition, when the intercept frequency detection method is used, R _EP and R _ES can be calculated for the constituent elements of the above-described equivalent circuit by obtaining an impedance circle from Rmax (= R _EP + R _ES ) and the minimum reactance Xmin. ,

R _EP = −Xmin / 2

R _ES = Rmax−R _EP

It is obtained. This method is also effective in a low frequency region where the minimum phase point detection method cannot be applied.

Next, a method for deriving the parasitic source resistance R _S of the equivalent circuit of the FET will be described.
It has been shown that the impedance Z ₂₂ described above draws a circle on the complex plane. This similar impedance Z ₁₂ is also expected that a circle as well. From the formula of formula 2, if you divide it into a real part and an imaginary part,

_{Z 12 = R S + Y gd} / Δ Ycore

= R _S + jω * C _dg / Δ _Ycore

= R _S + B * C _dg / (ω ² * A ² + B ² ) −jω * A * C _dg / (ω ² * A ² + B ² )

It becomes.
Here _{A = C ds * C gS +} (C dS + C gS) * C gd)
B = (C _ds + C _gS ) * g _ds + C _gd * gm
It is.

Similar to the Z ₂₂ for Z _12, is as follows determine the start and end points of the circle.

Z ₁₂ (ω = ∞) = R _S
Z ₁₂ (ω = 0) = R _S + C _gd / B
= R _S + C _gd / ((C _ds + C _gS ) * g _ds + C _gd * gm)

It shows a diagram showing the impedance locus of the Z ₁₂ in FIG. The radius of the circle is Im (Z ₁₂ ) _min , and the center of the circle is R _s + Re (Z ₁₂ ) _max / 2.

Next, how to obtain the equivalent drain resistance of the FET equivalent circuit will be described.
Similar to Z _12, locus although minus _{Z 12} from _{Z 22} is the radius

C _gs / 2 * ((C _ds + C _gS ) * g _ds + C _gd * gm)

Draw a circle.
In the same manner as that for determining the equivalent source resistance, measured and the maximum value _{Re (Z 22} -Z 12) of the simulation and the like _Z 22 _{-Z 12} max, the minimum value _{Im (Z 22} -Z 12) impedance circle from min reactance The diameter and radius are obtained.
As an example, the equivalent drain resistance is

R _d = Re (Z ₂₂ −Z ₁₂ ) max + 2 * Im (Z ₂₂ −Z ₁₂ ) min

Can be calculated from Further, when obtaining the resistances of the equivalent source and the equivalent drain, they can be obtained by using a minimum phase detection method or the like as necessary.
Thus, from an equal _{Z 12} equivalent source _resistance, but was determined the equivalent drain resistance from Z 22 _{-Z 12,} legs equivalent source resistance equivalent drain resistance equivalent source resistance from _{Z 12} in addition to this and from _{Z 22} You may ask for what you did.
Moreover, when obtaining the equivalent source resistance and the equivalent drain resistance, it is assumed that the trajectories of Z ₁₂ , Z ₂₂ -Z ₁₂ , Z ₂₂ draw a circle on the complex plane. It is also possible to obtain the equivalent source resistance and the equivalent drain resistance by predicting the locus.

It will now be described determined direction of the equivalent gate resistance _{R g} of the FET equivalent circuit.
When the equivalent source resistance and equivalent drain resistance of the components of the FET equivalent circuit are obtained, r _ds , g _{m and the} like in FIG. 1 can be easily obtained. Once four of the eight parameters are known, the remaining values can be calculated using commercially available software. However, if the three resistors R _g , R _d , and R _{s in} the equation (1) can be eliminated, the parameters of the equivalent circuit can be calculated without using sophisticated software.
When the two resistances of the equivalent drain resistance R _d and the equivalent source resistance R _s are eliminated from the equation (1),

It becomes.
The Y ₁₁ component of the inverse matrix of Z ^* _(FET) is

Y ₁₁ ^* _(FET) = ((Y _gs + Y _gd ) / Δ Y _core ) / C

Where _{C = (((Y gd +} Y ds) / Δ Ycore)) + R g) * (Y gs + Y gd) - (Y gd / Δ Ycore) * (Y gd -Y gm)

It is.
Taking the reciprocal of this Y ₁₁ ^* _(FET) ,

1 / Y ₁₁ ^* _(FET) = R _g + 1 / (Y _gs + Y _gd )
= R _g + 1 / jω * (C _gs + C _gd )

Next, the real part of the inverse of Y ₁₁ component of the inverse matrix having 8 expression corresponds to the equivalent gate resistance. This method is characterized in that the equivalent gate resistance appears only in the real part, so that the value can be easily specified.
Here it was determined equivalent gate resistance from Y ₁₁ component, but it is also possible to calculate from other components such as Y _12.

With the above derivation method, the equivalent drain, gate, and source resistances are obtained, and when these three known data are eliminated from the equation (1), the inverse matrix of the equation (1) coincides with Y _core . As a result, the remaining parameters of the FET equivalent circuit are obtained.
Each element of the Y parameter of the FET core is

-Y12 _(core) = _Ygd = jω * _Cgd

Y _{11 (core)} + Y _{12 (core)} = Y _gs = jω * C _gs

Y _{22 (core)} + Y _{12 (core)} = Y _ds = 1 / r _ds + jω * C _ds

Y _{21 (core)} −Y _{12 (core)} = Y _gm = g _m

It becomes.
As described above, the method for calculating the equivalent gate resistance, source resistance, drain resistance and the values of the constituent elements of the core FET has been described.

FIG. 9 is a flowchart showing a method for deriving the equivalent (or parasitic) drain, gate, and source resistance of the FET equivalent circuit and the method for deriving the parameters of the constituent elements of the FET core section, which have been described so far.
In step ST1, the S parameter of the FET is measured using a network analyzer. At this time, the calibrated S parameter is obtained by removing the lead inductance, stray capacitance, etc. of the package. Thereafter, the measured S parameter is converted into a Z parameter. This conversion can be easily calculated using software. The S parameter and Z parameter are generally expressed as complex numbers.
In step ST2, an equivalent source resistance R _s that is a component of the FET equivalent circuit is derived from the frequency characteristic of the Z ₁₂ component of the Z parameter using the method described above. The Request equivalent drain resistance _{R d} of the frequency characteristic of the _Z 22 _{-Z 12.}
In step ST3, the subtracting equivalent drain determined in step ST2,3 from Z parameters, source resistance _R d, the _{R s.}
The stearyl-up ST4, convert the Z parameter in the Y parameter, determining the equivalent gate resistor _{R g} from the real part of the component _{Y 11} of the Y parameter at step ST5.
In step ST 6, it subtracts the equivalent gate resistor _{R g} obtained in step ST 5 from Z parameters obtained in step ST 3. As a result, a core FET obtained by subtracting the equivalent drain, gate, and source resistance from the FET can be obtained.
In step ST7, in order to obtain an equivalent circuit of the core FET, the Z parameter obtained in step ST6 is converted into a Y parameter.
In step ST8, the core FET Y parameters, _C dg from the frequency characteristics of the _{-Y 12, C} gs the frequency characteristic of _Y 11 ₊ Y _{12, g} from the frequency characteristic of Y 21 _{-Y 12 m,} the frequency of Y 22 _{+ Y 12} C _ds and r _ds are calculated from the characteristics.
In this way, first, the equivalent drain, gate, and source resistances of the FETs were obtained, and these values were removed from the total FETs so that only the core FETs were obtained, and the parameters of the constituent elements of the core FETs were obtained.

A specific configuration example for deriving the model parameters of the total FET according to the above-described method will be described below.
FIG. 10 shows an evaluation apparatus 70 for deriving the parameters of the FET transistor. Commands and data are input to the computer (CPU) 72 from the outside via the keyboard 73. The computer 72 is composed of a storage medium such as a RAM, a ROM, and an HDD, and is connected to a storage means 75 for storing programs and data. Examples of this program include a simulation program, a program for controlling a measuring instrument for data measurement, and a program for processing measurement data.
The interface 76 uses a computer 72 to control the measuring device 77 from the outside via a keyboard 73, and to exchange data between different devices so that data can be transferred between the computer and the measuring device. .

The measurement data measured by the measuring device 77 and the result of computation processing by the computer 72 in accordance with the program stored in the storage means are output to a display (display device) 71 and a printer 74.
The measuring device 77 includes, for example, an S parameter measuring device and the like, and a system capable of automatically measuring simulation data using the above-described computer 72 and interface 76 is constructed. The S parameter measurement data can be displayed on the display device 71, and the measurement data can be further converted into a Z parameter, a Y parameter, etc., and displayed again.

An example of a method for deriving the parameters of the total FET according to the flowchart shown in FIG.
In step ST1, a command is input from the keyboard 73, the S parameter measuring device of the measuring device 77 is controlled, for example, the FET is set to a predetermined operation bias, and S parameter is measured. The measured S parameter data of the FET is stored in the RAM or the like of the storage means 75 via the interface 76.
At this time, using the S parameter correction program stored in the storage means 75, the calibrated S parameter is obtained by removing the lead inductance, stray capacitance, etc. of the package.
In order to confirm the influence of the corrected S parameter, the frequency characteristic of the S parameter is displayed on the display device 71, and as a result, the influence of the lead inductance, stray capacitance, etc. can be investigated.
As a result, the display device 71 shows S parameter measurement data S ₁₁ , S ₁₂ , S ₂₁ , and S ₂₂ in FIGS.
Calculation is performed from the obtained S parameter according to the simulation program stored in the storage means 75. As shown in step ST2 of the flowchart of FIG. 9, a Z parameter is obtained from this S parameter, and an equivalent source resistance R _s is calculated from the Z ₁₂ component of this matrix.
The calculation result is temporarily stored in the RAM or the like of the storage unit and displayed on the display device 71. For example, as a display example, in FIG. 12, the horizontal axis indicates the range of 0 to 10 [Ω] in the real part, the vertical axis indicates the range of 0 to −6 [Ω], and the Z ₁₂ impedance circle is plotted. . As a result, when the frequency is 0 (or very low frequency), R _s + Re (Z ₂₁ ) max is 8.95 [Ω] and Im (Z ₂₁ ) min is 3.16 Ω, so the equivalent source resistance R _{s to be obtained is obtained.} Is

R _s = 8.95-3.60 * 2 = 1.75 [Ω]

It becomes.
Such calculation is automatically derived using a simulation program, and the result is displayed on the display device 71 described above. Also, the diagram of FIG. 12 can be displayed at the same time, and the results of the simulation can be confirmed sequentially.

Then, in accordance with the simulation program, corresponding to step ST2 in the flowchart of FIG. 9 to determine the equivalent drain resistance R _d. Furthermore, Z ₂₂ -Z ₁₂ of the Z parameter component stored in the storage unit 75 is calculated and stored in the storage unit 75, and the frequency characteristic of Z ₂₂ -Z ₁₂ shown in FIG. 13 is displayed on the display device 71. As a result, the following calculation is performed according to the simulation program stored in the storage means 75 using the computer 72.
When the frequency is 0 (or very low frequency), R _d + Re (Z ₂₂ −Z ₁₂ ) max is 25.63 [Ω], and Im (Z ₂₂ −Z ₁₂ ) min is 11.05 [Ω]. The equivalent drain resistance R _{d to be obtained} is

R _d = 25.63-11.05 * 2 = 3.53 [Ω]

It becomes.

Next, as shown in step ST5 of the flowchart of FIG. 9, using the data stored in the computer 72 and the storage means 75, the equivalent source and drain resistances are subtracted from the Z parameter and the data is stored in the storage means 75. To do. Equivalent gate resistance is converted into a Y parameter by inverting the matrix of the stored Z parameter is determined from a real part of the inverse of the Y ₁₁ component.
It is displayed on the display device 71 stores the frequency characteristics of the obtained Y ₁₁ component in the storage unit 75. An example is shown in FIG. The real part is shown on the horizontal axis and the imaginary part is shown on the vertical axis, and the equivalent gate resistance _Rg is calculated using a simulation program. In FIG. 14, the real part is 6.91 [Ω]. That is, the equivalent gate resistance R _g is

R _g = 6.91 [Ω]

It is obtained.
Thus, the gate, source, and drain resistances, which are equivalent resistances other than the FET core, are calculated.

As in step ST8 of the flowchart of FIG. 9, the parameters of each component of the FET core part can be obtained from each frequency characteristic.
Since the corrected S parameter, Z parameter, and Y parameter obtained in step ST1 are stored in the storage means 75 of the evaluation apparatus 70, first, the equivalent resistances of R _g , R _d , and R _s are deleted from the Z parameter. Memorize the result. Next, the Z parameter stored in the storage means 75 is converted into a Y parameter based on the simulation program, and the Y parameter (Y _core ) of the core FET described above is obtained.

_{-Y 12 (core) = Y gd} = jωC gd

Y _{11 (core)} + Y _{12 (core)} = Y _gs = jωC _gs

Y _{22 (core)} + Y _{12 (core)} = Y _ds = 1 / r _ds + jωC _ds

Y _{21 (core)} −Y _{12 (core)} = Y _gm = gm

From these equations, the parameters of each component of the core FET can be obtained. The following calculation is performed using the computer 72, the simulation program stored in the storage means 75, and the stored Y parameter data.

In FIG. 15, the display device 71 shows the relationship between the absolute value of 1 / Y _gd and the phase plotted in the frequency range from 100 MHz to 100 GHz.
as a result,

C _gd = Im (Y _gd ) /ω=0.194 [PF]

Is obtained.
Similarly, FIG. 16 shows a display device 71 in which the relationship between the absolute value of 1 / _Ygs and the phase is plotted against frequency. From this measurement data, C _gs is calculated by the simulation program.

C _gs = Im (Y _gs ) /ω=0.0593 [PF]

Is calculated.
FIG. 17 shows the frequency characteristics of Y _{gm on} the display device 71. As a result, g _m is calculated by the simulation program.

g _m = 100 [mS]

Is calculated.
FIG. 18 shows the frequency characteristic of 1 / Y _{ds on} the display device 71. Using a simulation program from this graph data,
Each value of r _ds and C _ds is

C _ds = Im (Y _ds ) /0.0518 [PF]

r _ds = 1 / Re (Y _ds ) = 105 [Ω]

Is calculated.

The equivalent circuit of the FET is obtained using the values of the parameters obtained above, and the frequency characteristic indicated by the S parameter shown in the equivalent circuit is plotted, while the S parameters S ₁₁ , S ₁₂ , S ₂₁ , and S ₂₂ of the actual FET are plotted. The data are shown in FIGS. 19 (A) to (D). As a result, it can be seen that there is no difference between the two at almost all frequencies. That is, the FET equivalent circuit obtained here is correct.

FIGS. 20A and 20B show g _m obtained from the current characteristics and Y _sf obtained from the equivalent circuit model. The value of _{g m} results actual FET is 81.8 [mS], whereas the values of the equivalent circuit model is both consistent with 81.8 [mS].
21A and 21B, the output conductance obtained from the actual FET current characteristics is 7.75 [mS], and the value obtained from the equivalent circuit model may be 7.77 [mS]. Match.
In FIG. 22A, the current gain | h ₂₁ | ² characteristic is plotted in the range of 100 MHz to 100 GHz for an actual FET and an equivalent circuit model. It can be seen that both coincide in this frequency range. FIG. 22B shows the frequency characteristic of the one-way maximum gain (MUG), and is a plot of actual FET measurement data and equivalent circuit model data. As a result, the two match in this MUG.

As described above, in the FET equivalent circuit model according to the present invention, the necessary data is only the S parameter under the target bias condition, and the conventional method has the cold bias (Cold BIAS) in addition to the S parameter frequency characteristic at the time of the operation bias. ) The time required for modeling the equivalent circuit is shortened compared to the fact that the S parameter under the condition was also necessary.
In addition, there is an advantage that special software such as an optimizer is not required, and time and effort required for modeling for optimization are not required. Further, as shown in FIG. 1, the configuration of the equivalent circuit is simpler than that of the conventional example, and it is easy for a designer who designs a circuit using the equivalent circuit. For example, when designing an amplifier, there is also an advantage that the mirror capacity of the transistor can be seen by human eyes and the bandwidth can be predicted immediately.

It is the block diagram which showed the structure of the equivalent circuit model of FET. FIG. 2 is a circuit configuration diagram showing parameters of an equivalent circuit model of the FET shown in FIG. 1. FIG. 3 is a circuit configuration diagram showing a core FET portion of the equivalent circuit of the FET shown in FIG. 2. FIG. 3 is an explanatory diagram for calculating a Z parameter of the FET shown in FIG. 2. It is a 3 element circuit block diagram for demonstrating the principle of operation of FET. FIG. 6 is a frequency characteristic diagram of the three-element circuit shown in FIG. 5. It is explanatory drawing for calculating | requiring the element constant of 3 element circuit structure shown in FIG. FIG. 6 is another explanatory diagram for obtaining an element constant of the three-element circuit configuration shown in FIG. 5. FIG. 2 is a flowchart for obtaining a constant of an equivalent circuit of the FET shown in FIG. 1. It is a block diagram of the evaluation apparatus for FET measurement evaluation. It is data which shows the frequency characteristic of the measurement S parameter of FET. It is a frequency characteristic figure of Z parameter for calculating | requiring an equivalent source resistance. It is a frequency characteristic figure of Z parameter for calculating | requiring an equivalent drain resistance. It is a frequency characteristic figure of Y parameter for obtaining an equivalent gate resistance. It is | 1 / Y _gd | frequency characteristic diagram for _obtaining gate-drain capacitance. It is | 1 / Y _gs | frequency characteristic diagram for _obtaining gate-source capacitance. a 1 _{/ Y gm} frequency characteristic diagram for determining the g _m. It is | 1 / Y _ds | frequency characteristic diagram for _obtaining C _ds and r _ds . It is the figure which showed the S characteristic data of the frequency characteristic of an equivalent circuit, and measured value. Is a diagram showing an actual measurement value and the g _m of the equivalent circuit. It is the figure which showed the output conductance and measured value of an equivalent circuit. It is the figure which showed the current gain, MUG, and measured value of an equivalent circuit. It is an equivalent circuit of a conventional FET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,100 ... FET equivalent circuit, 30 ... Core FET equivalent circuit, 50 ... Three element circuit block diagram, 70 ... Evaluation apparatus, 71 ... Display apparatus, 72 ... Computer (CPU), 73 ... Keyboard, 74 ... Printer, 75 ... Storage means, 76 ... interface, 77 ... measuring device, R _g ... equivalent gate resistance, R _s ... equivalent source resistance, R _d ... equivalent drain resistance.

Claims (5)

Storage means for storing data, the control means for carrying out arithmetic processing based on a program of the data, the equivalent source resistance of the field-effect transistor, the equivalent drain resistance and equivalent gate resistance, the equivalent source resistance, the equivalent drain resistance and equivalent gate resistance Measuring and evaluating a field effect transistor having a core transistor excluding
Using the control means,
A first step of measuring frequency characteristics of the field effect transistor and converting from an S parameter (scattering parameter) to a Z parameter ;
A second step of determining the equivalent source resistance and equivalent drain resistance from the frequency trajectory of the Z parameter;
A third step of subtracting a matrix component of the equivalent source resistance and equivalent drain resistance obtained in the second step from the Z parameter matrix ;
A fourth step of obtaining an admittance parameter by converting the Z parameter obtained in the third step, and obtaining the equivalent gate resistance from the admittance parameter;
A fifth step of subtracting the matrix component of the equivalent gate resistance from the matrix of Z parameters obtained in the third step;
A sixth step of converting the Z parameter obtained in the fifth step into an admittance parameter ;
A seventh step of obtaining the value of the constituent element of the core transistor from the admittance parameter obtained in the sixth step
Field- Evaluation Transistor Measurement and Evaluation Method The equivalent source resistance, said by varying the frequency from zero to equivalently infinite with Z ₁₂ of the Z parameter obtained in the first step, obtaining the infinite end point of the frequency characteristic showing a circle The method for measuring and evaluating a field effect transistor according to claim 1 . The equivalent drain resistance is obtained from a real part and an imaginary part of a circle of a frequency locus of Z ₂₂ -Z ₁₂ of the Z parameter.
The method for measuring and evaluating a field effect transistor according to claim 1 . The equivalent drain resistance, and the maximum value of the real _(Z 22 _{-Z 12),} is a value obtained by adding the minimum value of 2 × imaginary _(Z 22 _{-Z 12)}
A method for measuring and evaluating a transistor according to claim 3 . The equivalent gate resistance is the real part of the inverse of Y ₁₁ component of the admittance parameters obtained in said fourth step
The method for measuring and evaluating a field effect transistor according to claim 1 .

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