JP4496455B2 - 共有メモリマルチプロセッサシステムのためのディレクトリベース予測方法および装置 - Google Patents

共有メモリマルチプロセッサシステムのためのディレクトリベース予測方法および装置 Download PDF

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JP4496455B2
JP4496455B2 JP2001174337A JP2001174337A JP4496455B2 JP 4496455 B2 JP4496455 B2 JP 4496455B2 JP 2001174337 A JP2001174337 A JP 2001174337A JP 2001174337 A JP2001174337 A JP 2001174337A JP 4496455 B2 JP4496455 B2 JP 4496455B2
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data block
processor
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processor node
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JP2002049600A5 (enExample
JP2002049600A (ja
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カクシラス ステファノス
クリフォード ヤング レジナルド
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Agere Systems LLC
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
JP2001174337A 2000-06-09 2001-06-08 共有メモリマルチプロセッサシステムのためのディレクトリベース予測方法および装置 Expired - Fee Related JP4496455B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/591918 2000-06-09
US09/591,918 US6889293B1 (en) 2000-06-09 2000-06-09 Directory-based prediction methods and apparatus for shared-memory multiprocessor systems

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JP2002049600A JP2002049600A (ja) 2002-02-15
JP2002049600A5 JP2002049600A5 (enExample) 2005-05-19
JP4496455B2 true JP4496455B2 (ja) 2010-07-07

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JP2001174337A Expired - Fee Related JP4496455B2 (ja) 2000-06-09 2001-06-08 共有メモリマルチプロセッサシステムのためのディレクトリベース予測方法および装置

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US (1) US6889293B1 (enExample)
EP (1) EP1162542B1 (enExample)
JP (1) JP4496455B2 (enExample)
DE (1) DE60132132T2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7398282B2 (en) * 2000-06-16 2008-07-08 Fujitsu Limited System for recording process information of a plurality of systems
US7017015B2 (en) * 2002-12-20 2006-03-21 Rockwell Automation Technologies, Inc. Method and system for coordinating the access of data by two computer processes
US7340565B2 (en) * 2004-01-13 2008-03-04 Hewlett-Packard Development Company, L.P. Source request arbitration
US7240165B2 (en) 2004-01-15 2007-07-03 Hewlett-Packard Development Company, L.P. System and method for providing parallel data requests
US7962696B2 (en) 2004-01-15 2011-06-14 Hewlett-Packard Development Company, L.P. System and method for updating owner predictors
US7363435B1 (en) * 2005-04-27 2008-04-22 Sun Microsystems, Inc. System and method for coherence prediction
US7395376B2 (en) 2005-07-19 2008-07-01 International Business Machines Corporation Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of shared memory blocks
WO2007096979A1 (ja) 2006-02-24 2007-08-30 Fujitsu Limited 情報処理装置およびデータ転送方法
JP4945611B2 (ja) * 2009-09-04 2012-06-06 株式会社東芝 マルチプロセッサ
RU2459241C1 (ru) * 2011-03-29 2012-08-20 Государственное образовательное учреждение высшего профессионального образования "Казанский государственный энергетический университет" (КГЭУ) Цифровое прогнозирующее устройство
WO2013042240A1 (ja) * 2011-09-22 2013-03-28 富士通株式会社 情報処理装置及び情報処理装置の制御方法
US10996989B2 (en) * 2016-06-13 2021-05-04 International Business Machines Corporation Flexible optimized data handling in systems with multiple memories
US10528471B2 (en) * 2016-12-27 2020-01-07 Eta Scale Ab System and method for self-invalidation, self-downgrade cachecoherence protocols
US9691019B1 (en) * 2017-03-07 2017-06-27 Google Inc. Depth concatenation using a matrix computation unit
US10896367B2 (en) 2017-03-07 2021-01-19 Google Llc Depth concatenation using a matrix computation unit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214766A (en) * 1989-04-28 1993-05-25 International Business Machines Corporation Data prefetching based on store information in multi-processor caches
EP0394642A3 (en) 1989-04-28 1992-07-15 International Business Machines Corporation Data prefetching in caches
US6032228A (en) * 1997-11-26 2000-02-29 International Business Machines Corporation Flexible cache-coherency mechanism

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DE60132132D1 (de) 2008-02-14
EP1162542A1 (en) 2001-12-12
US6889293B1 (en) 2005-05-03
DE60132132T2 (de) 2009-01-02
JP2002049600A (ja) 2002-02-15
EP1162542B1 (en) 2008-01-02

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