JP4493432B2 - Inverter control device - Google Patents

Description

  The present invention relates to an inverter control device that performs two-phase PWM (pulse width modulation) control of an inverter.

  A conventional general inverter control device is configured as shown in FIG. The control target of this inverter control device is the inverter 1. The inverter 1 converts a DC power obtained from a commercial AC power supply through a converter or a DC power 2 from a battery DC power 2 into AC power, and the converted AC power is converted into a three-phase AC motor 3 (for example, a permanent magnet synchronous motor). Supply and drive. The inverter 1 is composed of a high-power switching element such as an IGBT having a logarithm corresponding to the number of phases of the load that is the three-phase AC motor 3, and is switching-controlled by the inverter control device 10.

The inverter control device 10 includes a speed detector 11 that detects the rotational speed of the electric motor 3, and a current expressed in a dq2-phase coordinate system based on the deviation between the speed detected by the speed detector 11 and the speed command. A current command generator 13 for generating commands Id ^* and Iq ^* , and a U-phase current detector 14u and a W-phase current detector 14w provided on the U-phase output and W-phase output side of the output phases of the inverter 1 And a UVW / dq converter 15 for taking out the measured currents Id and Iq converted into the d-q2 phase coordinate system.

Further, the inverter control device 10 takes out the deviations between the current commands Id ^* and Iq ^* from the current command generator 13 and the measured currents Id and Iq from the UVW / dq converter 15, respectively. Current controller 16d, 16q for converting to dq-axis voltage commands Vd ^* , Vq ^* , and these dq-axis voltage commands Vd ^* , Vq ^* as inputs, U-phase voltage command Vu, V-phase voltage command Vv and W-phase voltage command A dq / UVW converter 17 for converting to Vw and outputting, and a PWM converter 18 are provided.

  As shown in FIG. 5, the PWM converter 18 compares the U-phase voltage command Vu with a carrier wave es having a predetermined waveform such as a triangular wave, and U-phase PWM signals Su (+), Su (- ), And the drive of the switching elements, eg, UN and UP, which form a pair corresponding to the U phase of the inverter 1 is controlled. The V-phase voltage command Vv and the W-phase voltage command Vw are not shown in the figure, but the same processing is performed to obtain the V-phase PWM signals Sv (+), Sv (−), the W-phase PWM signals Sw (+), Sw (−) is taken out. Therefore, if the level of the voltage command Vu, Vv, Vw of each phase is varied, the pulse width of the PWM signal can be varied.

  By the way, in such PWM control, there is a problem of simultaneous ON operation of both switching elements UP and UN.

  In general, the configuration of one phase of the inverter 1 is such that the switching element UN and the switching element UP are connected in series between the power supply lines of the DC power supply 2, and the on / off control is performed alternately as shown in FIG. Yes. That is, it is assumed that the switching elements UN and UP connected in series do not turn on at the same time. However, in the inverter control device 10, both switching elements UN and UP may be simultaneously turned on due to a delay in switching between the switching elements UN and UP. When the switches are turned on at the same time, a short-circuit current flows through both switching elements UN and UP, which causes a problem that both switching elements UN and UP are destroyed [Problem 1].

  On the other hand, from the viewpoint of reducing electromagnetic wave noise and switching loss and improving the efficiency of power conversion, a method called two-phase PWM control is considered in which switching is made to the switching pause phase of each phase every 60 ° of the voltage phase as shown in FIG. It has been. In this method, when there is a phase difference between the current command and the voltage command applied to the PWM converter 18, the switching pause phase is based on the discontinuity of the voltage commands Vu, Vv, Vw of each phase. There is a problem that the voltage command of the other phase exceeds the power supply voltage of the inverter 1, the current waveform of the electric motor 3 is distorted, and the controllability is deteriorated [Problem 2].

  Therefore, in order to solve the above problems, an inverter control device 10 based on two-phase PWM control as shown in FIG. 7 has been developed. This inverter control device 10 is provided with dead time compensation means for solving the former problem, while switching the switching pause phase sequentially every 60 ° phase of the voltage phase in order to solve the latter problem.

  In the former dead time compensation means, as shown in FIG. 8 derived from FIG. 5, the switching timing for turning on the switching elements UP and UN which are the outputs of the PWM converter 18 is a predetermined time (hereinafter referred to as dead time). As a result of shifting Dt and preventing both switching elements UP and UN from being turned on at the same time, a shortage of voltage output at the time of ON due to the dead time Dt occurs, so that the shortage voltage is compensated.

  Therefore, in addition to the detection currents Iu and Iw detected by the current detectors 14u and 14w on the U-phase output side and the W-phase output side of the inverter 1, Iv = −Iu− through the current calculation unit 21 from the current condition of Iu + Iv + Iw = 0. Iws is extracted and supplied to the dead time compensator 22 where the dead time voltage compensation amounts DtCmpU, DtCmpV, and DtCmpW for each phase are generated and given to the phase voltage commands Vu, Vv, and Vw of the dq / UVW converter 17. Compensate.

  The dead time compensation unit 22 is specifically as shown in FIG. 9, and determines the positive / negative of the detection currents Iu, Iv, Iw of each phase, and changes in a step shape according to the positive / negative, and has predetermined upper and lower limits. After passing through each phase limiter function 22-1u, 22-1v, 22-1w for limiting by the limit current value Ir and each phase division function 22-2u, 22-2v, 22-2w for dividing by the predetermined current value Ir The gain adjustment is performed by the phase gain adjustment functions 22-3u, 22-3v, and 22-3w, and dead time voltage compensation amounts DtCmpU, DtCmpV, and DtCmpW are extracted (Patent Document 1).

  Therefore, in the case of the U phase, the U phase dead time voltage compensation amount DtCmpU as shown in FIG. 10B can be extracted with respect to the input of the detection current Iu shown in FIG. FIG. 4C shows the voltage command Vu output from the dq / UVW conversion unit 17.

On the other hand, the latter offset voltage compensation means includes a two-phase PWM conversion unit 23 between the dq / UVW conversion unit 17 and the PWM conversion unit 18, and a current phase Qi detected by a current phase detector 24 such as a resolver. And the current deviation amount from the current phase Qi obtained by the current deviation amount calculation unit 25 from the d-axis voltage command Vd ^* and the q-axis voltage command Vq ^{* by the} calculation formula tan ⁻¹ (Vd ^* / Vq ^* ). Then, the voltage phase Qv shown in FIG. 10D is extracted from the phase detector 26 and supplied to the two-phase PWM converter 23. The two-phase PWM conversion unit 23 sequentially switches to the switching pause phase every 60 ° phase of the voltage phase Qv, for example, the maximum voltage command level and switching to the voltage command Vu ^* of the switching pause interval corresponding to the U phase switching pause phase. An offset voltage such as a correction voltage is also applied to the voltage commands Vv ^* and Vw ^* for the V phase and W phase other than the idle phase, and the maximum voltage command level is set for the U phase switching idle phase. Is compensated so that the V-phase voltage command Vv ^** and the W-phase voltage command Wv ^** output from the inverter 1 do not exceed the power supply voltage of the inverter 1 (Patent Document 2).

(Patent Document 1)
Japanese Patent Laid-Open No. 10-4690 (Patent Document 2) JP-A-8-340691

By the way, in the two-phase PWM control as described above, for each voltage command Vu, Vv, Vw having a deviation of 120 ° for each phase, as shown in FIG. The switching pause phase is switched, the switching pause interval is set to the maximum voltage command level, and the voltage commands Vu, Vv, Vw of the other phases are corrected using the correction voltage when switching the switching pause phase, and the desired voltage is set. The commands Vu ^** , Vv ^** and Vw ^** are taken out.

Therefore, the switching pause phase is switched every 60 ° of the voltage phase, but at the same time, voltage compensation must be accurately performed for an undervoltage corresponding to the dead time Dt.
However, the phase limiter functions 22-1u, 22-1v, 22-1w of the dead time compensation unit 22 as described above change stepwise by determining whether the detected currents Iu, Iv, Iw of each phase are positive or negative. Therefore, square wave dead time voltage compensation amounts DtCmpU, DtCmpV, and DtCmpW as shown in FIG. 10B are generated and given to the phase voltage commands Vu, Vv, and Vw. As a result, it is detected by the current phase detector 24 due to square wave changes in the dead time voltage compensation amounts DtCmpU, DtCmpV, and DtCmpW, as well as the fact that the intended compensation voltage level cannot be output or the switching timing is shifted. The current phase Qi changes discontinuously, and as a result, the voltage phase Qv changes discontinuously every 60 ° as shown in FIG. 10D due to the dead time voltage compensation amounts DtCmpU, DtCmpV, and DtCmpW of each phase. Further, the phase voltage commands Vu, Vv, Vw of the dq / UVW converter 17 also change discontinuously every 60 °. This causes a problem that the voltage phase Qv is distorted and the switching pause phase cannot be normally switched.

  The present invention has been made in view of the circumstances as described above, and provides an inverter control device that generates a dead time voltage compensation amount that does not change excessively and compensates for a voltage shortage due to dead time accurately and stably. For the purpose.

In order to solve the above-described problem, the present invention sequentially switches to a switching pause phase every 60 ° of the voltage phase with respect to the input voltage command of each phase, generates a pause section and inputs it to the PWM conversion means. A dead time is formed when each relative switching element constituting the inverter by the PWM conversion means is turned on, and a voltage shortage due to the dead time is generated by the dead time compensation unit for each phase dead time voltage compensation amount. In the inverter control device for giving a phase voltage command, the dead time compensation unit is:
A limiter function that changes the output of each phase current command value in a gentle slope in synchronization with the positive / negative change of each phase current command value and limits and outputs it with a predetermined upper / lower limit current value, and this phase limiter function The first division element that divides each output by the absolute value of the limit current value and the output of the first division element of each phase are adjusted by a predetermined gain coefficient, and the dead time voltage compensation amount of each phase is calculated. And a gain adjustment function to be taken out.

  According to the present invention, the voltage shortage due to dead time can be accurately compensated, the voltage phase can be stabilized by generating a dead time voltage compensation amount without excessive change, and switching suspension of two-phase PWM control Phase switching can be performed accurately.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing an overall configuration of an inverter control device according to the present invention, and FIG. 2 is a configuration diagram showing an embodiment of a main part of the inverter control device according to the present invention.

  Since the inverter control apparatus including the inverter 1 has substantially the same configuration as that in FIG. 7, the same components are denoted by the same reference numerals, and overlapping portions are left to the description of FIG. 7.

As shown in FIG. 1, this inverter control device takes out current command values Iu ^* , Iv ^* , and Iw ^* for each phase from, for example, the speed control unit 12 and supplies them to the dead time compensation unit 30 that is the main part of the present invention. .
As shown in FIG. 2, the dead time compensation unit 30 is provided with limiter functions 31u, 31v, 31w corresponding to the current command values Iu ^* , Iv ^* , Iw ^* of each phase. The limiter functions 31u, 31v, 31w synchronize the current command values Iu ^* , Iv ^* , Iw ^* of each phase with the positive / negative changes of the current command values Iu ^* , Iv ^* , Iw ^* of each phase. And has a function of limiting with a predetermined upper / lower limit current value ± Ir by changing at a gentle slope. The outputs of the limiter functions 31u, 31v, 31w are input to the corresponding 1 / Ir division elements 32u, 32v, 32w, respectively. Each 1 / Ir division element 32u, 32v, 32w divides the upper / lower limit current value ± Ir, which is the output of each limiter function 31u, 31v, 31w, by the limit current value Ir and outputs ± 1; and The change portion of the gentle slope between the upper limit current value + Ir and the lower limit current value -Ir generates an output that changes with a gentle slope from +1 to -1, and from -1 to +1, and gain adjustment corresponding to each phase Input to the functions 33u, 33v, 33w. These gain adjustment functions 33u, 33v, and 33w adjust the outputs of the 1 / Ir division elements 32u, 32v, and 32w by a desired gain coefficient, and add elements 34a and 34b and subtraction elements 35u, Input 35v, 35w.

  These addition elements 34a and 34b add all the outputs of the phase gain adjustment functions 33u, 33v, and 33w, and divide the addition output by the 1/3 division element 36 to output the outputs of the phase gain adjustment functions 33u, 33v, and 33w. The average value is taken out and input to the subtraction elements 35u, 35v, 35w corresponding to each phase. These subtraction elements 35u, 35v, and 35w subtract the average value obtained by the 1/3 division element 36 from the output of the corresponding phase gain adjustment function 33u, 33v, 33w, and the dead time voltage compensation amount DtCmpU for each phase. , DtCmpV, DtCmpW are generated and added to the phase voltage commands Vu, Vv, Vw of the dq / UVW converter 17 to compensate for dead time.

Therefore, according to the embodiment as described above, by using the current command values Iu ^* , Iv ^* , Iw ^* of each phase as the input current to the dead time compensation unit 30, the change in the output current of the inverter 1 is affected. In such a state, the dead time voltage compensation amounts DtCmpU, DtCmpV, and DtCmpW for each phase can be generated.

Further, each phase limiter function 31u, 31v, 31w of the dead time compensation unit 30 performs dead time voltage compensation while changing the current command values Iu ^* , Iv ^* , Iw ^* of each phase with a slow slope in synchronization with the current change of the current command values Iu ^* , Iv ^* , Iw ^*. Positive and negative switching of the quantities DtCmpU, DtCmpV, and DtCmpW is performed. As a result, the phenomenon of distortion every 60 ° phase of the voltage phase Qv as shown in FIG. This means that the switching pause phase of the two-phase PWM control can be accurately executed, and at the same time, the respective phase voltage commands Vu, Vv, Vw of the dq / UVW converter 17 are stabilized (see FIG. 3C).

Further, since each phase current command value Iu ^* , Iv ^* , Iw ^* is input to the dead time compensation unit 30 with a phase shift of 120 °, all outputs of the phase gain adjustment functions 33u, 33v, 33w are added. When the output is divided by the 1/3 division element 36 and this division output is subtracted from the output of each phase gain adjustment function 33u, 33v, 3, a stepped U-phase dead with a gentle slope as shown in FIG. The time voltage compensation amount DtCmpU can be generated, and the U phase voltage shortage due to the dead time can be accurately compensated. The V-phase and W-phase dead time voltage compensation amounts DtCmpV and DtCmpW can be generated in the same manner, and eventually the U-phase voltage shortage due to the dead time of each phase can be accurately compensated.

In addition, this invention is not limited to the said embodiment, In the range which does not deviate from the summary, various deformation | transformation can be implemented. In the above embodiment, each phase current command value Iu ^* , Iv ^* , Iw ^* is obtained from the detection speed of the motor 3. However, various types of phase current commands are conventionally used for this kind of inverter control and motor control. Since there are methods for acquiring the values Iu ^* , Iv ^* , and Iw ^* , the phase current command values Iu ^* , Iv ^* , and Iw ^* may be acquired using those well-known techniques. Further, in the configuration of FIG. 2 which is the embodiment, the addition elements 34a and 34b, the subtraction elements 35u, 35v and 35w, and the division element 36 are omitted, and the outputs of the gain adjustment functions 33u, 33v and 33w are directly used as dead time. The voltage compensation amounts may be DtCmpU, DtCmpV, and DtCmpW.

Further, the gain adjustment function 33u or 33v, 33w corresponding to the phase in which the switching element is stopped may be set to zero, and the dead time voltage compensation amount may be bypassed in each phase voltage command. The reason is that each phase voltage command corresponding to the switching pause phase is set to the highest voltage command level, so that no dead time occurs and it is not necessary to perform dead time voltage compensation in the switching pause phase. In a region where the phase changes at a low speed, each phase current command value Iu ^* , Iv ^* , Iw ^* is input to the dead time compensation unit 30 in consideration of a minute current detection noise, and the phase changes at a high speed. Then, in consideration of a delay in current control, each phase detection current Iu, Iv, Iw may be input to the dead time compensation unit 30 to generate the dead time voltage compensation amounts DtCmpU, DtCmpV, DtCmpW.

  In addition, each embodiment can be implemented in combination, and in that case, the effect of the combination can be obtained.

The block diagram which shows one Embodiment of the inverter control apparatus which concerns on this invention. The block diagram which shows one Embodiment of the principal part of the inverter control apparatus which concerns on this invention. The wave form diagram of each required component part of an inverter control apparatus. The block diagram of the conventional general inverter control apparatus. The wave form diagram explaining the principle of PWM conversion. The figure set to the level of the highest voltage command in order to provide the switching pause section of ± 30 degrees at the peak time of the voltage command of each phase. The block diagram of another conventional inverter control apparatus which provided the two-phase PWM conversion part between the dq / UVW conversion part and the PWM conversion part, and provided the dead time compensation means. The figure explaining the reason which produces | generates a dead time. The figure which shows the structure of the conventional dead time compensation part. The wave form diagram of each required component when the conventional dead time compensation part is used.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Inverter, 3 ... Electric motor, 10 ... Inverter control apparatus, 11 ... Speed detector, 12 ... Speed control part, 13 ... Current command generation part, 14u, 14w ... Current detector, 15 ... UVW / dq conversion part, 16d , 16q ... current control unit, 17 ... dq / UVW conversion unit, 18 ... PWM conversion unit, 23 ... two-phase PWM conversion unit, 24 ... current phase detector, 25 ... current deviation amount calculation unit, 26 ... phase detection unit, 30 ... Dead time compensation unit, 31u, 31v, 31w ... Limiter function, 32u, 32v, 32w ... 1 / Ir division element, 34a, 34b ... Addition element, 35u, 35v, 35w ... Subtraction element, 36 ... 1/3 division element.

Claims (4)

In response to the voltage command of each phase that is input, the switching phase is sequentially switched to the switching pause phase every 60 ° of the voltage phase, and a pause interval is generated and input to the PWM conversion means. An inverter control device that forms a dead time when the switching element is turned on, generates a dead time voltage compensation amount for each phase by a dead time compensation unit, and provides the voltage command for each phase to the voltage shortage due to the dead time. ,
The dead time compensation unit is
A limiter function for changing the input current of each phase current command value in a gentle slope in synchronization with the positive / negative change of each phase current command value, and limiting and outputting with a predetermined upper / lower limit current value,
A first division element for dividing the output of each phase limiter function by the absolute value of the limit current value;
An inverter control device comprising: a gain adjustment function for adjusting an output of the first division element of each phase by a predetermined gain coefficient and extracting a dead time voltage compensation amount of each phase. The inverter control device according to claim 1,
The dead time compensation unit is
Arithmetic means for adding and averaging the outputs of the gain adjustment functions of the respective phases;
An inverter control apparatus comprising: means for subtracting the output of the gain adjustment function for each phase by the average value obtained by the computing means to extract a dead time voltage compensation amount for each phase. In the inverter control device according to claim 1 or 2,
An inverter control device, wherein a gain coefficient of the gain adjustment function corresponding to a phase in which the switching element is suspended is set to zero. In the inverter control device according to any one of claims 1 to 3,
Inverter control, wherein the detected current of the output of the inverter is input to the dead time compensation unit instead of each phase current command value input to the dead time compensation unit only in a region where the phase changes at high speed apparatus.

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