JP2000060137A - Power converting equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable restraining a circulating current, when the number of parallel connections of converters is large by obtaining a mean current of each phase of each converter from a detected combined current, and correcting an output command value from the outside according to the deviation between the mean current and the output current of each phase. SOLUTION: U-phase output currents I1u, I2u, I3u of converters 7-1, 7-2, 7-3 are combined via reactors 9-1u, 9-2u, 9-3u, and supplies a converter combined current Iu to the U-phase of a secondary winding of a generator-motor 13. A circulating current is obtained from the deviation between a mean output current of combined current detected values IFAu, IFAv, lFAw and converter output current detected values IF1u, lF1v, IF1w of the converter 7-1. By multiplying the circulating current with a gain, converter output voltage command values Vu*, Vv*, Vw* are corrected so as to reduce the circulating current. As a result, the circulating current flowing through the converters 7-1, 7-2, 7-3 can be restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power converter in which a plurality of converters are connected in parallel, and more particularly to a power converter suitable for suppressing a circulating current flowing between a plurality of converters.

[0002]

2. Description of the Related Art As a conventional inverter control device, as described in Japanese Patent Application Laid-Open No. 63-287371, a difference between output currents of two inverters connected in parallel to a load via a reactor is multiplied by a gain. Discloses a technique in which a modulated wave, which is a PWM voltage command value, is added to each synchronization signal generated for each period of a PWM control carrier wave to suppress a circulating current flowing between two inverters.

[0003]

As described above, in the prior art, the circulating current correction amount is calculated from the difference between the output currents of the inverters. Therefore, this control device can be applied to a case where there are three or more inverters. Therefore, there is a problem that the circulating current flowing between the converters cannot be suppressed.

The detected value of the circulating current is an instantaneous value,
If a filter is added to the detection value, the phase will be delayed.
There was a problem that the filter could not be put into control.

Furthermore, since the detection of the circulating current is an instantaneous AC value, if the circulating current is corrected by detecting the current ripple of the pulse frequency component due to the deviation of the pulse, the converter cannot be controlled stably. there were.

In addition, there is a problem that the direct current component that constantly occurs in the current ripple of the pulse frequency component of the circulating current deteriorates the balance between converters, and that the output current capacity of the converter cannot be used up to the maximum value.

An object of the present invention is to provide a power converter capable of suppressing a circulating current even when the number of converters in parallel is three or more.

Another object of the present invention is to provide a power converter capable of stably controlling a converter.

Still another object of the present invention is to provide a power converter capable of utilizing a current between converters up to a maximum current capacity.

[0010]

In order to achieve the above object, a power converter according to the present invention comprises a plurality of converters for outputting a three-phase current in accordance with an external output command value. In a power converter that outputs a combined current of a converter,
Converter output detection means for detecting each phase output current of each converter, and combined current detection means for detecting the combined current,
An average current calculation means for obtaining an average current for each phase of each converter from the combined current detected by the combined current detection means; an average current for each phase obtained by the average current calculation means; A deviation from each phase output current detected by the detector output detection means, and correcting the external output command value by the deviation to suppress a circulating current. Things.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a power converter according to one embodiment of the present invention. In the following description, there are three converters and three PWM control devices, respectively. However, since they have the same configuration, only one control system will be described.

As shown in FIG. 1, converters 7-1 and 7-2
And 7-3 have a three-parallel connection configuration to increase the output current capacity. The U-phase, V-phase and W-phase output terminals of the converter 7-1 have current detectors 8-1u and 8-1 respectively.
Reactors 9-1u, 9-1v and 9-1w are connected via v, 8-1w. Here, converters 7-1,
7-2, 7-3 U-phase output currents I1u, I2u, I3u
Are combined via the reactors 9-1u, 9-2u, and 9-3u to supply the converter combined current Iu to the U phase of the secondary winding of the generator motor 13. The converter output current IFAu detected by the current detector 12u is output from the PWM controller 6
-1, 6-2, 6-3 and the three-phase / two-phase converter 15a. The three-phase / two-phase converter 15a converts the three-phase input values into d-axis current detection values Idf and q-axis current detection values Iqf, which are orthogonal two-axis data, using the determinant shown in Equation 1. . Note that the d-axis current detection value Idf and the q-axis current detection value Iqf, which are the two-axis data described above, represent an active power component and a reactive power component, respectively.

[0013]

(Equation 1)

Here, ω shown in Expression 1 is the generator motor 13
, And is detected by the frequency detector 18. Further, the detected d-axis current value Idf and the detected q-axis current value Iqf obtained by Equation 1 are DC components. In the above description, the U-phase output terminals of the converters 7-1, 7-2, and 7-3 are described, but the V-phase and the W-phase have the same configuration.

The detected d-axis current value Idf and the detected q-axis current value Iqf are input to the current regulator 3 together with the specified d-axis current value Id * and the specified q-axis current value Iq *. In the current regulator 3, the d-axis current command value Id * and the q-axis current command value I
q *, d-axis current detection value Idf, and q-axis current detection value I
qf is calculated and amplified, and the output value of the generator d
The shaft voltage command Vd * and the generator q-axis voltage command Vq *
It is input to the phase-to-phase converter 4a.

[0016]

(Equation 2)

Here, ω shown in Expression 2 is the generator motor 13
Is the secondary side excitation frequency. The two-phase / three-phase converter 4a converts the three-phase converter output voltage command values Vu *, Vv *, and Vw * into three-phase converter output voltages by the determinant shown in Expression 2, and outputs the PWM controller 6-1 to the PWM controller 6-2 -3 respectively.

FIG. 2 is a control block diagram of the PWM controller shown in FIG. Although FIG. 2 shows only the PWM controller 6-1, the PWM controllers 6-2 and 6-3 have the same configuration.

As shown in FIG. 2, converter output voltage command values Vu *, Vv *, Vw * are added to adder / subtracters 19au, 19a.
v, 19aw. Adder / subtractor 19au, 19a
v, 19aw are output from the PWM pulse generator 22.
u, 22v, 22w and output pulses Pu, P
v, Pw are converted by a converter 7- connected to a PWM controller 6-1.
1 is input to the gates of the U-phase, V-phase, and W-phase elements.
Then, the converter 7-1 turns on / off the element based on the PWM pulse and outputs a phase current.

In the dividers 20u, 20v, and 20w, the combined current IFA of the converters 7-1, 7-2, and 7-3 is used.
u, IFAv, IFAw divided by the number of parallel converters,
The average output current signals IFu, IFv, IFw are created. The average output current signals IFu, IFv, IFw are input to the adders / subtractors 19bu, 19bv, 19bw. Here, converter output current detection values IF1u, IF1v, I detected by current detectors 8-1u, 8-1v, 8-1w.
F1w is also input to the adders / subtractors 19bu, 19bv, 19bw, respectively, and outputs the average output current signals IFu, IFv, IF.
The deviation from w is calculated for each of the U, V, and W phases of the converter 7-1. This deviation is calculated by the converter 7-
1, 7-2 and 7-3, and the circulating current does not appear in the combined current. Therefore, the average output current created from the combined current and the converters 7-1, 7-2, 7- The circulating current can be detected from the difference from the output current of No. 3. The circulating current is multiplied by gains in multipliers 21u, 21v, 21w, and these outputs are added to adders / subtracters 19au, 19av, 19av.
aw.

As described above, according to the present embodiment, the average output currents Ifu, Ifv, Ifw of the combined current detection values IFAu, IFAv, IFAw and the converter output current detection values IF1u, IF1v, IF1v, IF1v, The circulating current is obtained from the deviation of IF1w, the gain is multiplied by the gain, and the converter output voltage command values Vu *, Vv *, Vw are reduced so as to reduce the circulating current.
* Has been corrected. As a result, the converters 7-1, 7-2,
The circulating current flowing between 7 and 7 can be suppressed. Further, since the combined current of the converters 7-1, 7-2, and 7-3 is detected and an average output current reference signal is created, even if the converter 7-1 has two or more parallel multiplexes, the circulating current can be reduced. Can be suppressed.

In this embodiment, the three-phase to two-phase converter 15a
Is used to perform the three-phase / two-phase conversion, but a three-phase / two-phase zero-phase conversion equation may be used. Instead of using the two-phase / three-phase converter 4a in the two-phase / three-phase conversion, a two-phase / three-phase zero-phase conversion type may be used.

Next, another embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 3 is a control block diagram of a PWM controller according to another embodiment of the present invention, and FIG. 4 is a control block diagram of the internal oscillator shown in FIG.

In this embodiment, as shown in FIG. 3, the combined current detection values IFAu, IFAv, IFAw are divided by a divider 20.
u, 20v, 20w divided by the number of parallel converters,
The internal oscillator input signals 31u, 31v, 31w are input to the internal oscillators 24u, 24v, 24w. In the internal oscillators 24u, 24v, and 24w, the internal oscillator output signals 32u, 32v, and 32w are added to the adders / subtractors 19bu, 19b.
v, 19 bw. Here, the adder / subtractor 19b
u, 19bv, 19bw, the internal oscillator output signal 32
u, 32v, 32w and converter output currents IF1u, IF1
v, the deviation from IF1w, ie, converters 7-1 and 7-
The circulating current between 2, 7 and 3 is determined. Multiplier 21u,
21v and 21w, adders / subtracters 19bu, 19bv, 1
The deviation obtained by 9bw is multiplied by a gain, and the value is input to adders / subtractors 19au, 19av, 19aw.

Next, the operation of the internal oscillator 24u will be described with reference to FIG. In the following description, the U-phase is described, but the configuration is the same for all three phases. As shown in FIG. 4, the internal oscillator input signal 31u and the internal oscillator 24
The internal oscillator output signal 32u of the internal oscillator 24u is input to the phase difference detecting means 28u, and the internal oscillator input signal 31u of the internal oscillator 24u.
The phase difference Δθ between u and the internal oscillator output signal 32u is calculated. The calculated phase difference Δθ is input to the adder / subtractor 19cu. The integrated value of the reference angular frequency 25 of the internal oscillator 24u, that is, the phase is calculated by the integrator 26u, added to the phase difference Δθ by the adder / subtractor 19cu, and input to the oscillator 27u. The oscillator 27u inputs a sine wave of magnitude “1” to the multiplier 33u based on the input phase signal. The internal oscillator input signal 31 of the internal oscillator 24u
The amplitude of u is calculated by the amplitude detecting means 29u and input to the multiplier 33u through the filter 30u. Therefore, the internal oscillator output signal 32u of the internal oscillator 24u has a filter effect only for the amplitude of the internal oscillator input signal 31u, which is the average output current, and follows the signal without phase delay.

As described above, according to the present embodiment, the internal oscillator output signal 32u in which only the amplitude of the average current of the converters 7-1, 7-2 and 7-3 has a filter effect is used. Since the circulating current is suppressed, the circulating current can be suppressed without being affected by the ripple of the pulse frequency component included in the detection current.

FIG. 5 shows a PWM according to another embodiment of the present invention.
It is a control block diagram of a controller.

In this embodiment, the converters 7-1, 7-2, 7
-3, the combined current detection values IFAu, IFAv, IFA
The three phases w are input to the divider 20b, and the deviation from the converter output current detection values IF1u, IF1v, IF1w, that is, the circulating current, is calculated by the adders / subtractors 19bu, 19bv, 19bw. Then, these circulating currents are input to a three-phase / two-phase converter 15b, and two-axis data is calculated.
The signal is multiplied by a and input to the phase adjuster 34, and these outputs are input to the two-phase / three-phase converter 4b to convert them into three-phase AC signals. The AC signal from the two-phase / three-phase converter 4b is input to the adders / subtractors 19au, 19av, and 19aw together with the converter output voltage command values Vu *, Vv *, and Vw *, and corrects the voltage command value so as to reduce the circulating current. And PW
Gate pulses Pu, Pv, Pw are output by M pulse generators 22u, 22v, 22w.

In this case, the combined current is converted to a three-phase to two-phase converter 15
After the three-phase to two-phase conversion by b, the correction can be performed using the value obtained by dividing the number of converters by the divider 20b. As described above, according to the present embodiment, the circulating current
Since the three-phase two-phase conversion is performed by the phase converter 15b,
The required voltage correction amount can be instantaneously calculated as a vector amount from the circulating current, and the circulating current can be efficiently suppressed.

FIG. 6 shows a PWM according to another embodiment of the present invention.
It is a control block diagram of a controller. In the present embodiment, the PWM controller shown in FIG. 5 has a structure in which a filter 35 is provided between the phase adjuster 34 and the two-phase to three-phase converter 4b.

As described above, according to the present embodiment, three-phase to two-phase conversion is performed to convert to a DC amount on the rotating coordinates.
Since a filter can be added without causing a phase delay in the detected value of the circulating current, the converter can be stably controlled and the circulating current can be suppressed.

FIG. 7 shows a PWM according to another embodiment of the present invention.
It is a control block diagram of a controller. In the present embodiment, in the PWM controller shown in FIG.
v, 19bw are output to gain calculators 17u, 1
7v, 17w, and gain calculators 17u, 17v,
The output signal of 17w and the output signal of the two-phase / three-phase converter 4b are input to the multipliers 14u, 14v, and 14w, and the voltage is corrected according to the magnitude of the circulating current of each phase. .

As described above, according to the present embodiment, the amount of voltage correction is determined according to the magnitude of the circulating current of the own phase, so that when the circulating current of the own phase is large, the amount of correction can be increased in proportion thereto. When it is small, the correction amount can be made small, so that the change of the correction amount due to the influence of the circulating current of another phase can be made small.

Further, in this embodiment, it is also possible to calculate the voltage command value correction value using the three-phase to two-phase conversion.

FIG. 8 is a block diagram showing a power converter according to another embodiment of the present invention. Note that FIG. 8 shows only the U phase since the three phases have the same configuration.

In this embodiment, the converters 7-1u and 7-2u are connected in parallel. U-phase output currents from converters 7-1u and 7-2u connected in parallel are combined via reactors 9-1u and 9-2u, respectively. The converters 7-1u and 7-2u and the reactor 9-
Current detectors 8-connected between 1 u and 9-2 u, respectively.
The circulating current detected from 1u, 8-2u is added to the adder / subtractor 1
The difference of the detection current is obtained by inputting the value to 9du. Then, the difference between the detected currents is input to the three-phase to two-phase converter 15c,
The circulating current is converted into a voltage component vector by the phase adjuster 34, returned to three-phase data by the two-phase to three-phase converter 4c, and multiplied by the gain by the multiplier 14b. The signal from the multiplier 14b is added to the adder / subtractor 19 together with the converter output voltage command value Vu *.
au1 and 19au2, and corrects the converter output voltage command value Vu * so as to reduce the circulating current.

As described above, according to the present embodiment, the circulating current can be detected with a simple configuration in the case of two-parallel connection, and the circulating current can be suppressed as in the above-described embodiment.

FIG. 9 is a block diagram showing a power converter according to another embodiment of the present invention. In this embodiment, the converter 7-
Current regulators 3 respectively corresponding to 1, 7-2, 7-3
1, 3-2, 3-3, two-phase three-phase converter 4a, three-phase two
A phase converter 15a is provided, and the current regulators 3-1 and 3-
The d-axis current command value Id * and the q-axis current command value Iq * for one medical examination converter are input to the input signals 2 and 3-3. Here, the feedback signal I of the current regulator 3-1
The output current detection values IF1u, IF1v, IF1w of the converter 7-1 are added to the three-phase two-phase converter 15a for F1d, IF1q.
The value converted by 1 is used. In the above description, the control system of the converter 7-1 has been described.
2, 7-3 also have a current control system similar to the converter 7-1.

As described above, according to the present embodiment, the current regulators 3-1, 3-2, and 3--3 correspond to the number of converters 7-1, 7-2, and 7-3, respectively. By providing 3, the converter operates so as to reduce the deviation between the output current of each converter and the command value, so that the currents flowing through the converters become equal, and as a result, the circulating current can be suppressed.
FIG. 10 is a control block diagram of a PWM controller according to another embodiment of the present invention. In the present embodiment, in addition to the configuration of FIG. 6, the DC component of the circulating current is calculated based on the output signals from the adders / subtractors 19bu, 19bv, and 19bw.
u, 16v, 16w, and multipliers 33au, 33a
v, 33aw, multiplying the gain by the adder / subtracter 19eu,
It is configured to correct the voltage command value by inputting it to 19ev and 19ew.

As described above, according to the present embodiment, since the DC component is detected, it is possible to suppress the circulating current caused by variations in the inductance value, the resistance value, and the switching element characteristics of the circuit.

[0041]

The circulating current is obtained from the difference between the average output current obtained from the combined current and the output current of each converter, and the voltage command value is corrected so as to reduce the circulating current by multiplying by a gain. The circulating current flowing through can be suppressed. Further, in order to apply a filter effect only to the amplitude of the average current of the combined current, the average current is divided into a phase and an amplitude component, and the phase of the signal of the internal oscillator matches the phase of the average current. Since the circulating current is suppressed using an amplitude value including a filter effect for the amplitude component of, the circulating current can be suppressed without being affected by the ripple of the pulse frequency component included in the detection current.

Since the amount of voltage correction is determined according to the magnitude of the circulating current of the own phase, the amount of correction can be increased in proportion to the amount of the circulating current of the own phase, and reduced when the amount of the circulating current of the own phase is small. Therefore, a change in the correction amount due to the influence of the circulating current of another phase can be reduced.

Further, since the DC component is detected, it is possible to suppress the circulating current caused by variations in the inductance value and resistance value of the circuit and the characteristics of the switching element.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a power conversion device according to an embodiment of the present invention.

FIG. 2 is a control block diagram of the PWM control device shown in FIG.

FIG. 3 is a control block diagram of a PWM control device according to another embodiment of the present invention.

FIG. 4 is a control block diagram of the internal oscillator shown in FIG.

FIG. 5 is a control block diagram of a PWM control device according to another embodiment of the present invention.

FIG. 6 is a control block diagram of a PWM control device according to another embodiment of the present invention.

FIG. 7 is a control block diagram of a PWM control device according to another embodiment of the present invention.

FIG. 8 is a configuration diagram showing a power converter according to another embodiment of the present invention.

FIG. 9 is a configuration diagram showing a power converter according to another embodiment of the present invention.

FIG. 10 is a control block diagram of a PWM control device according to another embodiment of the present invention.

[Explanation of symbols]

Id *: d-axis current command value, Iq *: q-axis current command value,
3,3-1,3-2,3-3,3u ... current regulator, 4
a, 4b, 4au... two-phase three-phase converter, Vu *, Vv *, V
w * ... converter output voltage command value, 6-1, 6-2, 6-3
... PWM controllers, 7-1, 7-2, 7-3, 7-1u,
7-2u... Converters, 8-1u, 8-1v, 8-1w, 8
-2u, 8-2v, 8-2w, 8-3u, 8-3v, 8
-3w, 12u, 12v, 12w ... current detector, Vd *
... Generator d-axis voltage command, Vq * ... Generator q-axis voltage command,
9-1u, 9-1v, 9-1w, 9-2u, 9-2v,
9-2w, 9-3u, 9-3v, 9-3w ... reactor, I1u, I1v, I1w, I2u, I2v, I2w,
I3u, I3v, I3w ... converter output current, Iu, I
v, Iw: converter combined current, 13: generator motor, 14
a, 14b, 14u, 14v, 14w ... multiplier, 15
a, 15b, 15c: three-phase two-phase converter, Idf: d-axis current detection value, Iqf: q-axis current detection value, 16u, 16v, 1
6w: DC component calculator, 17u, 17v, 17w: Gain calculator, 18: Frequency detector, ω: Excitation frequency, IF
1u, IF1v, IF1w, IF2u, IF2v, IF
2W, IF3u, IF3v, IF3w ... Converter output current detection value, IFAu, IFAv, IFAw ... Combined current detection value, Δθ ... Phase difference, 19au, 19av, 19aw, 1
9bu, 19bv, 19bw, 19cu, 19du, 1
9eu, 19ev, 19ew, 19au1, 19au2
... addition and subtraction units, 20u, 20v, 20w, 20b ... dividers, 21u, 21v, 21w ... gain multipliers, 22u,
22v, 22w ... PWM pulse generator, Pu, Pv, P
w: gate pulse, IFu, IFv, Ifw: average output current, 24u, 24v, 24w: internal oscillator, 25: reference angular frequency, 26u: integrator, 27u: oscillator, 28u
... Phase difference detecting means, 29u amplitude detecting means, 30u filter, 31u internal oscillator input signal, 32u internal oscillator output signal, 33u, 33au, 33av, 33aw
... Multiplier, 34 ... Phase adjuster, 35 ... Filter, IF1
d, IF1q, IF2d, IF2q, IF3d, If3q
... Two-axis component of converter output current detection value.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Joe Kubota 7-2-1, Omika-cho, Hitachi City, Ibaraki Pref. Hitachi, Ltd. Power and Electricity Development Division (72) Inventor Headquarters Mitsuyuki Omika-cho, Hitachi City, Ibaraki Prefecture 7-2-1, Hitachi, Ltd. Power and Electricity Development Division (72) Inventor Mikisuke Higuchi 3-1-1, Sakaicho, Hitachi-shi, Ibaraki F-term in Hitachi, Ltd. Hitachi Plant (reference) 5H007 AA00 BB06 CC05 CC23 DC02 DC04 EA02

Claims (6)

[Claims] 1. A power converter for connecting a plurality of converters for outputting a three-phase current in accordance with an external output command value in parallel and outputting a combined current of the converters. A converter output detecting means for detecting a phase output current, a combined current detecting means for detecting the combined current, and an average current for each phase of each converter is obtained from the combined current detected by the combined current detecting means. An average current calculation means, a deviation between the average current for each phase determined by the average current calculation means and each phase output current detected by the converter output detection means, and an output command value from the outside. And an output command value correcting unit that suppresses the circulating current by correcting the deviation with the deviation. 2. A power converter for connecting a plurality of converters for outputting a three-phase current in accordance with an output command value from the outside in parallel and outputting a combined current of the converters. A converter output detecting means for detecting a phase output current, a combined current detecting means for detecting the combined current, and an average current for each phase of each converter is obtained from the combined current detected by the combined current detecting means. Average current calculation means, filter means for removing ripples of the average current, and calculating a deviation between the average current from which ripples have been removed by the filter means and each phase output current by the converter output detection means, A power conversion device comprising output command value correction means for correcting an output command value by the deviation and suppressing a circulating current. 3. A power converter for connecting a plurality of converters for outputting a three-phase current in accordance with an output command value from the outside in parallel and outputting a combined current of the converters. A converter output detecting means for detecting a phase output current, a combined current detecting means for detecting the combined current, and an average current for each phase of each converter is obtained from the combined current detected by the combined current detecting means. Average current calculation means, the deviation of the average current for each phase determined by the average current calculation means and the deviation of each phase output current determined by the converter output detection means,
An electric power converter, comprising: an output command value correcting unit that converts the deviation into an active power component and a reactive power component, and corrects the external output command value by the deviation to suppress a circulating current. 4. The power converter according to claim 3, further comprising a filter for removing a ripple of the average current. 5. The power conversion device according to claim 2, wherein said filter means includes a phase adjustment means for adjusting a phase of an average current. 6. A power converter for connecting a plurality of converters for outputting a three-phase current according to an external output command value in parallel and outputting a combined current of the converters. A converter output detecting means for detecting a phase output current, a combined current detecting means for detecting the combined current, and an average for obtaining an average current for each phase of each converter from the combined current detected by the combined current detecting means Current calculating means, DC component detecting means for detecting a DC component of an average current for each phase obtained by the average current calculating means and a deviation of each phase output obtained by the converter output detecting means, and An output command value correcting means for correcting the output command value of the above by the deviation and suppressing a circulating current.