JP4492169B2 - amplifier - Google Patents

Description

  The present invention relates to an amplifier, and more particularly to a low distortion amplifying circuit which is used in a microwave band and a millimeter wave band and is small and has a built-in distortion compensating circuit (linearizer).

  In a field effect transistor intended for high frequency power, the distortion characteristics of the element often have an adverse effect on the system. Up to now, distortion characteristics have been improved by removing distortion components caused by non-linearity of the element by externally attaching a distortion compensation circuit such as a linearizer (hereinafter referred to as a linearizer). A method has been adopted.

For example, FIG. 6 is a circuit diagram showing a conventional low distortion semiconductor amplifier, in which an output matching circuit 52 is provided on the drain electrode side of a nonlinear element (for example, FET: field effect transistor) 1 having a source electrode grounded, Further, a passive circuit 54, a linearizer 51, and a passive circuit 53 are provided on the gate electrode side.

  Next, the operation of this semiconductor amplifier will be described. In the semiconductor amplifier of FIG. 6, the gain of the nonlinear element decreases as the input power increases, the phase characteristics deteriorate (that is, the phase shift increases in the positive direction), and the distortion increases. In many cases, the linearizer 51 is provided on the gate electrode side and has a characteristic that the gain (relative ratio) increases and the phase shift increases in the negative direction, and is externally attached to the amplifier.

  As a result, the gain and phase of the nonlinear amplifying element 1 and the linearizer 51 become opposite phases and cancel each other, and the entire amplifier achieves low distortion characteristics. The passive circuits 53 and 54 provided before and after the linearizer 51 shown in FIG. 6 generate reflection components that are generated due to the mismatch in matching between the linearizer 51 and the nonlinear amplifying element 1 when the linearizer 51 is externally attached. It is for removing.

  The linearizer 51 includes a combination of passive elements such as a coupler and a combination of active elements such as a diode. As a specific example, as shown in FIG. 7, there is a linearizer (small distortion compensation circuit) in which a FET 6 having a source / drain ground structure is arranged. Referring to FIG. 7, a capacitor 4 is provided in parallel with the signal line, and a gate of a FET 6 having a source / drain ground structure is connected to the capacitor 4 via a transmission line 5.

  A control voltage is supplied from the gate bias terminal 103 to the CAD 6 via the transmission line 10, and the setting of the capacitance value of the FET 6 is controlled. Note that the matching circuits 2 and 3 are connected in series to the signal line, and the capacitor 4 is connected to the connection point between the matching circuits 2 and 3. Reference numerals 101 and 102 denote input / output terminals of the linearizer.

In this circuit, at the time of microwave input, the gate capacitance of the common source / drain structure FET 6 is increased, whereby the relative gain is increased and the relative phase is decreased to compensate for the distortion of the high output amplifier. Is. By applying a control voltage from the gate bias terminal 103 to the negative side of the gate of the source / drain grounded structure FET 6, the initial state of the gate capacitance can be changed. Such source and drain grounded structure FET, examples of using the linearizer is disclosed in Patent Document 1.
JP 2003-332851 A

  FIG. 8 is an example showing the results before and after distortion compensation by the above-described conventional linearizer. When the output level increases, distortion compensation is performed with a change in the gate capacitance of the common source / drain FET 6. The compensated output level is determined by the gate width of the FET 6 and the gate control voltage.

  The conventional low distortion semiconductor amplifier is configured as described above. However, as shown in FIG. 8, there is a case where the distortion is deteriorated in the region where the output level is low. As shown in FIG. 9, this occurs because the phase characteristics of the linearizer are degraded in a region where the output level is low. Usually, in a region where the output level is low, the phase characteristic of the high output amplifier is small and the phase of the linearizer is also kept low. However, when distortion compensation is performed in a large output region using a linearizer, the nonlinearity of the linearizer becomes strong in a region where the output level is low. In FIG. 9, “PM” is Phase Modulation and indicates a change in phase.

  Therefore, as shown in FIG. 8, there is a problem that the phase characteristic is deteriorated in a region where the output level is low, and as a result, the distortion characteristic is deteriorated in a region where the output level of the entire amplifier is low.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an output that is small in size, reduces power consumption in a distortion compensation circuit, and further performs distortion compensation. It is an object of the present invention to provide an amplifier circuit capable of increasing the dynamic range.

The amplifier according to the invention comprises
An amplifier including a non-linear amplifying element that amplifies and outputs an input signal, and a distortion compensation circuit that increases linearity of input / output characteristics of the non-linear amplifying element,
The distortion compensation circuit includes:
It is composed of a passive element and a field effect transistor whose source and drain are grounded.
The field effect transistor is characterized in der Rukoto a plurality of field-effect transistor whose gate widths are different from each other are connected in parallel.

In addition, a matching circuit for adjusting impedance characteristics between the nonlinear amplifying element and the distortion compensation circuit is further included. The distortion compensation circuit includes a capacitor connected in parallel to the input signal line of the nonlinear amplifying element, and a common connection point of each gate of the field effect transistor is connected to the capacitor. Features.

Further, the distortion compensation circuit includes a transmission line or a resistor connected between the capacitor and a common connection point of each gate of the field effect transistor. Moreover, said common connection point of the gates of the field effect transistor, which is characterized in that the control voltage is supplied, also the non-linear amplifying element and the distortion compensating circuit is formed on the same semiconductor substrate Features.

  The operation of the present invention will be described. A capacitor and a transmission line are connected as a passive circuit in parallel with the signal line. The gates of a plurality of source / drain grounded FETs are connected to the other end of the transmission line. A control voltage is applied to the common connection point of the gates of these source / drain grounded FETs. Thereby, it is possible to suppress deterioration of the phase characteristics and distortion characteristics of the amplifier at the output level.

  According to the present invention, a capacitor, which is a passive element, is connected in parallel to the signal line, the gate of the source / drain grounded structure FET is connected to this capacitor, and a plurality of source / drain grounded structure FETs are connected in parallel. By adopting a configuration in which the gate control voltage is shared, there is an effect that it is possible to suppress deterioration of the phase characteristics and distortion characteristics of the amplifier at the output level. In addition, the distortion compensation circuit can be realized with a simple configuration, and the dynamic range of distortion compensation can be expanded. Furthermore, it is possible to develop the hybrid IC due to the simplicity of the structure.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention, and the same parts as those in FIG. 7 are denoted by the same reference numerals. In this example, a plurality of FETs having a source / drain ground structure are connected in parallel. That is, the gates of the FETs 6 to 8 are connected in common, connected to the gate bias terminal 103 via the transmission line 10, and connected to the signal line via the transmission line 5 and the resistor 4. The sources and drains of these FETs 6 to 8 are all grounded. The other configuration is the same as that of FIG.

のように表記される。 As described above, the behavior of the phase shift characteristic with respect to the input level of the conventional linearizer is as shown in FIGS. 8 and 9, and the distortion characteristic degradation in the low input level region is the linearizer itself (in this case, the source This is due to the deterioration of the phase characteristics of the common drain FET 6). The reason for this will be explained below using mathematical formulas. As in the linearizer showing the conventional distortion compensation circuit of FIG. 7, the phase characteristic φ (phase: radians) when one source / drain grounded FET 6 is connected in parallel to the signal line is:

It is written like this.

  Here, Z0 is the connection impedance of the linearizer, ω is the frequency, C1 (p) is the non-linear gate capacitance of the common source / drain FET 6 having input dependence (p), and C is the capacitance of the capacitor 4. It can be explained that the phase characteristic decreases when C1 (p) increases as the input level increases. As will be described later, C1 (p) generally does not increase linearly with respect to the input. Therefore, depending on the gate width of the common source / drain structure FET 6 and the bias condition, the phase may change greatly at a low input level. This is a deterioration of the phase characteristics of the linearizer itself. When the deterioration of the phase characteristic is determined under the above conditions, the dynamic range of distortion compensation is greatly limited.

のように表記される。 On the other hand, the phase characteristics of the linearizer in the embodiment of the present invention shown in FIG. 1 are equivalent to those in which the gate capacities of FETs, which are a plurality of nonlinear elements, are connected in parallel. When the two source / drain grounded FETs 6 to 8 are connected, the phase characteristic φ (phase: radians) is

It is written like this.

  Here, C1 (p), C2 (p), and C3 (p) represent the non-linear gate capacitances of the source / drain grounded FETs 6 to 8 having input dependency (p), respectively. When the nonlinear gate capacitances C1 (p), C2 (p), and C3 (p) increase linearly as the input level increases, in the present invention, the gate width of the source / drain grounded structure FET in the linearizer in the conventional example is set. Since this is equivalent to summing multiple times, there is no difference from the prior art. However, as described above, in general, the nonlinear gate capacitance exhibits a nonlinear increase with respect to the input level.

  FIG. 2 shows a calculation result of the phase characteristic when the increase amount increases exponentially with respect to the input level as a specific example. The gate capacitances were 0.3 pF, 0.15 pF, and 0.05 pF, respectively. For comparison, the result of setting the gate capacitance to 0.5 pF (= 0.3 + 0.15 + 0.05) in the conventional circuit is shown. According to the present invention, it can be seen that the phase shift amount at the point where the input level is low is suppressed as compared with the conventional linearizer.

  FIG. 3 shows the result obtained by the large signal simulation (harmonic balance method) of the phase characteristics of the linearizer alone in the low distortion amplifier circuit according to the present invention in comparison with the conventional invention. With the circuit configuration of the present invention, it can be seen that the phase characteristics at the point of low input level are reduced as compared with the conventional circuit configuration. Furthermore, it can be seen that a reduction in phase characteristics that is the same as that of the conventional circuit can be realized even at a point with a large input level.

  FIG. 4 shows the large signal simulation (harmonic balance method) characteristic of the intermodulation distortion characteristic in the low distortion amplifier circuit of the present invention. For comparison, the calculation results of intermodulation distortion characteristics of an amplifier without distortion compensation are also shown. It can be seen that the conventional linearizer performs distortion compensation of about 5 dB at the output point (output 14 to 18 dBm) at which distortion compensation is performed. Conversely, at a low input level with a large back-off (output 11 dBm or less), It can be seen that the distortion characteristics deteriorate.

  On the other hand, in the linearizer of the present invention, the distortion compensation amount at the output point where distortion compensation is performed is not different from the conventional one, and the distortion characteristics can be improved far more than the conventional example even in the point of large back-off. It can be seen that the dynamic range of the output for distortion compensation is widened. In the calculation, two nonlinear gate capacitances having different gate width sizes were used. However, in order to reduce the phase distortion in a region where the output level is low, a source / drain grounded FET may be added. At this time, it is necessary to change the gate width to be added.

  FIG. 5 is a circuit diagram of another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. The linearizer in the low distortion amplifier circuit shown in this example is provided with a capacitor 4 and a resistor 9 as a passive circuit. That is, a resistor 9 is provided instead of the transmission line 5 of FIG.

となる。 The phase characteristics in the circuit of this example are as follows when three source / drain grounded FETs 6 to 8 are connected:

It becomes.

  Here, R is the resistance value of the resistor 9 in the passive circuit. As a result, as described above, as the input level increases, the nonlinear gate capacitances C1 (p), C2 (p), and C3 (p) increase and the phase characteristics decrease. At a low input point, deterioration of the phase characteristics of the linearizer can be suppressed by a plurality of nonlinear gate capacitors.

  In the above-described embodiment, three source / drain grounded FETs are provided in parallel. However, the present invention is not limited to this, and any number of two or more may be used.

It is a circuit diagram of one embodiment of the present invention. FIG. 3 is a diagram illustrating an example of input level dependency of a phase characteristic when the input level dependency of a nonlinear gate capacitance is considered in the circuit of FIG. 1. In the circuit of FIG. 1, it is a figure which shows the example of the large signal simulation (harmonic balance method) of the input level dependence of a phase characteristic when the input level dependence of a nonlinear gate capacity | capacitance is considered. It is a figure which shows the example of the large signal simulation (harmonic balance method) of the intermodulation distortion characteristic of the low distortion amplifier circuit in the circuit of FIG. 1 in comparison with a conventional example. It is a circuit diagram of other embodiments of the present invention. It is a figure which shows an example of a prior art. It is a figure which shows the other example of a prior art. It is the conceptual diagram which showed the intermodulation distortion characteristic of the linearizer of the circuit of FIG. 7 by the input level. It is the conceptual diagram which showed the phase characteristic of the conventional linearizer at the input level.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Amplifying element 2,3 Matching circuit 4 Capacitor 5,10 Transmission line 6-8 FET of source and drain ground structure
9 Resistance

Claims (6)

An amplifier including a non-linear amplifying element that amplifies and outputs an input signal, and a distortion compensation circuit that increases linearity of input / output characteristics of the non-linear amplifying element,
The distortion compensation circuit includes:
It is composed of a passive element and a field effect transistor whose source and drain are grounded.
The field effect transistor, an amplifier, characterized in der Rukoto a plurality of field-effect transistor whose gate widths are different from each other are connected in parallel.   The amplifier according to claim 1, further comprising a matching circuit for adjusting impedance characteristics of the nonlinear amplifying element and the distortion compensation circuit. The distortion compensation circuit includes a capacitor connected in parallel to an input signal line of the nonlinear amplifying element, and a common connection point of each gate of the field effect transistor is connected to the capacitor. The amplifier according to claim 1 or 2. 4. The amplifier according to claim 3, wherein the distortion compensation circuit includes a transmission line or a resistor connected between the capacitor and a common connection point of each gate of the field effect transistor. The amplifier according to claim 1, wherein a control voltage is supplied to a common connection point of each gate of the field effect transistor. 6. The amplifier according to claim 1, wherein the nonlinear amplifying element and the distortion compensation circuit are formed on the same semiconductor substrate .

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