JP4490939B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  In recent years, the demand for nonvolatile semiconductor memory devices such as EEPROMs has increased. In the nonvolatile semiconductor memory device, when the distance between adjacent memory cells in the word line direction becomes closer, there arises a problem that capacitive coupling between adjacent floating gates increases.

  In order to solve such a problem, a method has been proposed in which a recess is formed in an element isolation insulating film provided between memory cells and a control gate line (word line) is formed in the recess (for example, Patent Document 1). Hereinafter, such a method will be described with reference to FIGS.

  In FIG. 13, 101 is a semiconductor substrate having an element isolation trench 103 and an element forming portion 102, 104 is an element isolation insulating film, 105 is a lower gate insulating film (tunnel insulating film), and 106a and 106b are polysilicon films that become floating gates. Is shown. In the process of FIG. 13, after the polysilicon film 106b is formed on the element isolation insulating film 104 and the polysilicon film 106a, the silicon oxide film 111 is formed on the polysilicon film 106b. Further, after patterning the silicon oxide film 111 by lithography and etching, a side spacer film is formed on the entire surface, and the side spacer 112 is formed on the side surface of the silicon oxide film 111 by RIE or the like. In this manner, an etching mask including the silicon oxide film 111 and the side spacer 112 and having the opening 113 is formed.

  Next, as shown in FIG. 14, using the etching mask as a mask, the polysilicon film 106 b and the element isolation insulating film 104 are etched to form a recess 114.

  Next, as shown in FIG. 15, after removing the etching mask, an upper gate insulating film (ONO film) 107 is formed, and further, a polysilicon film 108a and a WSi film 108b to be control gate lines are formed. Thereafter, the WSi film 108b, the polysilicon film 108a, the upper gate insulating film 107, the polysilicon film 106b, and the polysilicon film 106a are patterned to separate the memory cells.

  As described above, in the above-described conventional technology, the concave portion 114 formed in the element isolation insulating film 104 is filled with the polysilicon film 108a, thereby suppressing the capacitive coupling between the adjacent floating gates (polysilicon films 106a and 106b). Is possible.

  However, in the above-described prior art, the pattern of the silicon oxide film 111 is formed using a lithography technique, and therefore, there is a gap between the pattern of the silicon oxide film 111 and the pattern of the element isolation trench 103 (element isolation insulating film 104). Registration errors can occur. Therefore, in order to reliably form the recess 114 in the element isolation insulating film 104, it is necessary to provide a margin for the width of the etching mask formed of the silicon oxide film 111 and the side spacer 112 in consideration of alignment errors. . That is, the width of the opening 113 of the etching mask must be narrower than the width of the element isolation trench 103 by a margin. As a result, the width of the recess 114 obtained by etching the polysilicon film 106 b and the element isolation insulating film 104 is necessarily narrower than the width of the element isolation groove 103. Therefore, when the interval between adjacent memory cells, that is, the width of the element isolation trench 103 becomes narrow, it becomes very difficult to fill the recess 114 with the polysilicon film 108a, and it becomes difficult to suppress capacitive coupling between the floating gates. .

Thus, conventionally, when the width of the element isolation trench is reduced, it becomes difficult to form the control gate line in the recess of the element isolation insulating film, and it becomes difficult to suppress capacitive coupling between the floating gates. There was a problem.
JP 2001-168306 A

  According to the present invention, even when the width of the element isolation trench is reduced, the control gate line can be reliably formed in the recess of the element isolation insulating film, and the capacitive coupling between the floating gates can be effectively suppressed. An object is to provide a semiconductor device.

  A semiconductor device according to an aspect of the present invention includes a semiconductor substrate having first and second element formation portions defined by element isolation grooves, and first and second elements formed on the first and second element formation portions, respectively. 1st and 2nd lower gate insulating films, 1st and 2nd floating gates formed on the 1st and 2nd lower gate insulating films, respectively, formed in the element isolation trench, and the first And an element isolation insulating film protruding from the surface of the semiconductor substrate so as to cover a side surface of the second lower gate insulating film and a part of the side surface of the first and second floating gates, and a recess is formed in the upper portion The bottom of the recess is located below the surface of the semiconductor substrate, and the heights of the upper ends contacting the side surfaces of the first and second floating gates are the heights of the first and second floating gates, respectively. An element isolation insulating film formed lower than a surface height; an upper gate insulating film formed on the surfaces of the first and second floating gates and on the surface of the element isolation insulating film; and the upper gate insulating film A control gate line formed on the upper and entire side surfaces of the first and second floating gates through the upper gate insulating film and through the upper gate insulating film and the element isolation insulating film; And the control gate line embedded to the bottom of the recess, and the entire side surface of the first floating gate facing the second floating gate is the element of the first element forming portion. The entire side surface of the second floating gate facing the first floating gate is aligned with the side surface delimited by the separation groove. They are aligned in separated side by serial the device isolation trench of the second element forming section.

  According to the present invention, the control gate line can be easily and reliably formed in the recess of the element isolation insulating film (lower insulating film), and the capacitive coupling between the floating gates can be effectively suppressed. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a plan view schematically showing a configuration of a semiconductor device (NAND type nonvolatile semiconductor memory device) according to an embodiment of the present invention.

  As shown in FIG. 1, each NAND cell unit has a configuration in which a select transistor ST is connected to a plurality of memory cells MC connected in series. The memory cells MC to MC arranged in the word line direction are connected by a common control gate line (word line) 26, and the selection transistors ST to ST are connected by a common selection gate line 26 '. A bit line 42 is connected to each select transistor ST via a bit line contact 43.

  2A is a cross-sectional view taken along line AA in FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB in FIG.

  The semiconductor substrate (silicon substrate) 11 has a plurality of element forming portions 12, and the adjacent element forming portions 12 are partitioned by element isolation grooves 13. The memory cell MC and the selection transistor ST are formed in the element forming portion 12, and the source / drain diffusion layer 14a is formed between the memory cells MC adjacent in the bit line direction, and the source / drain diffusion is formed between the memory cell MC and the selection transistor ST. The source / drain diffusion layer 14 c is shared between the select transistors ST facing the layer 14 b via the bit line contact 43.

  The memory cell MC includes a lower gate insulating film (tunnel insulating film) 21, a floating gate 22a, an upper gate insulating film (ONO film) 23, a control gate (a gate formed of a polysilicon film 24a and a tungsten silicide film (WSi film) 25a). A control gate line 26) is provided. As will be described later, since the floating gate material film and the lower gate insulating film are simultaneously patterned when forming the pattern of the element isolation trench 13, the floating gate 22a, the lower gate insulating film 21, and the side surfaces of the element forming portion 12 (element The side surfaces separated by the separation groove 13 are aligned with each other.

  An element isolation insulating film 31 having a recess is formed in the element isolation trench 13. The element isolation insulating film 31 includes a portion extending upward, and the extended portion is in contact with the side surface of the floating gate 22a. A control gate line 26 (polysilicon film 24a in the illustrated example) is formed in the recess of the element isolation insulating film 31, and this control gate line 26 suppresses capacitive coupling between adjacent floating gates 22a. Is possible.

  The films constituting the respective portions 22a ', 23', 24a 'and 25a' of the selection transistor ST are formed of the same film as the films constituting the respective portions 22a, 23, 24a and 25a of the memory cell MC. However, the selection gate line 26 'is connected to the electrode 22a' at a location not shown. Further, the thickness of the gate insulating film 21 'is larger than the thickness of the lower gate insulating film 21 of the memory cell MC.

  The memory cell MC and the select transistor ST are covered with an interlayer insulating film 41. A bit line 42 is formed on the interlayer insulating film 41, and the bit line 42 is connected to the source / drain diffusion layer 14 c through the bit line contact 43.

  Hereinafter, the manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIGS. 3 to 11 and 12 (a) correspond to the AA cross section of FIG. 1, and FIG. 12 (b) corresponds to the BB cross section of FIG.

  First, as shown in FIG. 3, a silicon oxide film having a thickness of about 10 nm is formed as a lower gate insulating film 21 on a semiconductor substrate 11 such as a silicon substrate by a thermal oxidation method. Note that a thicker insulating film is formed in a region where the selection transistor is formed. Subsequently, a polysilicon film having a thickness of about 160 nm is formed as the floating gate material film 22 by LP-CVD (low pressure chemical vapor deposition). Further, a silicon nitride film 27 having a thickness of about 90 nm is formed by a LP-CVD method as a stopper film in a CMP (chemical mechanical polishing) process. Subsequently, a photoresist pattern 28 is formed on the silicon nitride film 27 by using a lithography technique.

  Next, as shown in FIG. 4, the silicon nitride film 27, the polysilicon film 22, the lower gate insulating film 21, and the semiconductor substrate 11 are etched using the photoresist pattern 28 as an etching mask. As a result, the trench 33 and the patterned silicon nitride film 27, the polysilicon film 22, the lower gate insulating film 21, and the pattern portion 30 formed of the semiconductor substrate 11 are obtained. In the semiconductor substrate 11, an element forming portion 12 and an element isolation groove 13 having a depth of about 220 nm are formed. Since patterning is performed using the same photoresist pattern 28 as a mask, the polysilicon film 22, the lower gate insulating film 21, and the side surfaces of the element forming portion 12 (side surfaces separated by the element isolation trenches 13) are aligned with each other. .

  Next, as shown in FIG. 5, a silicon oxide film having a recess 34 is formed by a plasma CVD method as the lower insulating film 31 to be an element isolation insulating film. The thickness of the silicon oxide film 31 is less than ½ of the width of the groove 33 so that the groove 33 is not buried without forming the concave portion 34. In order to obtain the desired concave portion 34, the groove is formed. It is determined in consideration of the width and depth of 33. In this example, the thickness of the silicon oxide film 31 is set to about 200 nm in a flat region (not shown).

  Next, as shown in FIG. 6, polysilazane is applied to the entire surface, and heat treatment is performed in a steam-added oxidizing atmosphere to densify the polysilazane. Thereby, the upper insulating film 32 made of polysilazane is obtained. By using a coating film of polysilazane or the like as the upper insulating film 32, the recess 34 can be easily filled even if the recess 34 is deep.

  Next, as shown in FIG. 7, the upper insulating film 32 and the lower insulating film 31 formed outside the trench 33 are removed by CMP, and the upper insulating film 32 and the lower insulating film 31 are planarized. At this time, the silicon nitride film 27 functions as a CMP stopper. If the upper insulating film 32 is not formed, there arises a problem that abrasive particles remain in the concave portion 34 after CMP. However, since the concave portion 34 is filled with the upper insulating film 32, such a problem does not occur.

  Next, as shown in FIG. 8, the silicon nitride film 27 is removed, and the upper surface of the polysilicon film 22 is exposed.

  Next, as shown in FIG. 9, the upper insulating film 32 is removed by etching, and a recess 35 corresponding to the recess 34 is formed. For the etching, selective etching is used in which the etching rate of the upper insulating film 32 is higher than the etching rate of the lower insulating film 31. In this example, etching is performed using buffer hydrofluoric acid (a mixed liquid of hydrofluoric acid and ammonium fluoride). By using buffer hydrofluoric acid, the ratio (selection ratio) of the polysilazane etching rate to the etching rate of the CVD silicon oxide film can be increased. Hydrofluoric acid vapor may be used instead of buffer hydrofluoric acid. Since the etching proceeds from the upper part of the film, the upper part of the lower insulating film 31 is also etched in this step, and the side surface of the polysilicon film 22 is partially exposed. It is also possible to adjust the exposure amount (exposure width) of the side surface of the polysilicon film 22 by adjusting the etching conditions.

  Next, as shown in FIG. 10, an ONO film having a predetermined thickness is formed as the upper gate insulating film 23 by the LP-CVD method. The ONO film is formed by sequentially laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film. The upper gate insulating film 23 may be formed at least on the exposed surface of the polysilicon film 22, but in this example, since the ONO film is deposited by the LP-CVD method, the upper gate insulating film 23 is a lower insulating film (element The isolation insulating film 31 is formed to have a stretched portion. In the region where the select transistor is to be formed, the upper gate insulating film 23 is partially removed by etching, and the polysilicon film 22 is partially exposed.

  Next, as shown in FIG. 11, a control gate material film 26 is formed on the upper gate insulating film 23, and the recess 35 is filled with the control gate material film 26. Specifically, a polysilicon film 24 with a thickness of about 80 nm doped with phosphorus is formed by LP-CVD, and then a tungsten silicide film (WSi film) 25 with a thickness of about 85 nm is formed by sputtering. To do.

  Next, as shown in FIGS. 12A and 12B, a silicon nitride film having a thickness of about 300 nm is formed by LP-CVD. Further, a resist pattern (not shown) is formed on the silicon nitride film, and the silicon nitride film is etched using the resist pattern as a mask to form a silicon nitride film mask pattern 44. The mask pattern 44 extends in a direction perpendicular to the extending direction of the element isolation groove 13. Subsequently, the tungsten silicide film 25, the polysilicon film 24, the upper gate insulating film 23, and the polysilicon film 22 are patterned using the mask pattern 44 as an etching mask. As a result, the floating gate 22a formed with the pattern of the polysilicon film 22, the control gate line 26 formed with the pattern of the polysilicon film 24a and the tungsten silicide film 25a is obtained.

  Thereafter, the source / drain diffusion layers 14a, 14b and 14c are formed, the interlayer insulating film 41 is formed, the bit line 43 is formed, and the like. In this way, a semiconductor device as shown in FIGS. 1, 2A and 2B is obtained.

  As described above, in this embodiment, the upper insulating film 32 is formed on the lower insulating film 31 serving as the element isolation insulating film, and the concave portion 35 is formed by removing the upper insulating film 32 by selective etching. . Therefore, the recess 35 can be formed without using a lithography technique, and there is no need to provide a margin for forming the recess 35 as in the prior art. Therefore, it is possible to make the maximum width of the opening of the recess 35 equal to the width of the element isolation groove 13. Further, since the entire side surface of the floating gate 22a is aligned with the side surface of the element isolation trench 13 (element forming portion 12), the interval between the adjacent floating gates 22a is substantially constant, and the recess 35 is formed by the floating gate 22a. The width of the frontage is not narrowed. Therefore, in this embodiment, it is possible to widen the opening of the recess 35, and the control gate line 26 can be easily and reliably formed in the recess 35. Therefore, the capacitive coupling between the floating gates can be effectively suppressed by the control gate line 26 formed in the recess 35.

  When the uppermost position of the element isolation insulating film (lower insulating film) 31 is lower than the lower surface of the floating gate 22a, the upper gate insulating film (ONO film) 23 is formed between the control gate line 26 and the semiconductor substrate 11. There is a possibility that capacitive coupling between the control gate line 26 and the semiconductor substrate 11 becomes a problem. Therefore, as shown in FIG. 2 and the like, the uppermost portion of the element isolation insulating film 31 is preferably positioned higher than the lower surface of the floating gate 22a.

  Further, when the uppermost position of the element isolation insulating film 31 is higher than the upper surface of the floating gate 22a, the entire side surface of the floating gate 22a is covered with the element isolation insulating film 31, so that the exposed area of the floating gate 22a is reduced. It is difficult to increase the capacitance between the floating gate 22a and the control gate line 26. Therefore, as shown in FIG. 2 and the like, the uppermost part of the element isolation insulating film 31 is preferably positioned lower than the upper surface of the floating gate 22a.

  If the lowermost position of the control gate line 26 is higher than the lower surface of the floating gate 22a, the capacitive coupling between the adjacent floating gates 22a may not be sufficiently suppressed by the control gate line 26. Therefore, as shown in FIG. 2 and the like, it is preferable that the lowermost portion of the control gate line 26 (corresponding substantially to the bottom of the recess 35 formed in the element isolation insulating film 31) be positioned lower than the lower surface of the floating gate 22a. .

  In the present embodiment, since the recess 35 is formed by selective etching of the upper insulating film 32 with respect to the lower insulating film (element isolation insulating film) 31, the desired positional relationship as described above is adjusted by adjusting the conditions of selective etching and the like. It is possible to obtain

  Further, in the above-described embodiment, as shown in FIG. 2 and the like, the entire recess 35 is filled with the control gate line 26, but even if the control gate line 26 is formed along the surface of the recess 35, It is possible to suppress capacitive coupling between adjacent floating gates 22a. However, from the viewpoint of preventing disconnection of the control gate line 26, it is preferable that the entire recess 35 is filled with the control gate line 26.

  Further, the lower insulating film 31 and the upper insulating film 32 may be those having an etching rate of the upper insulating film 32 higher than that of the lower insulating film 31, but a CVD insulating film is used as the lower insulating film 31. By using the coating film for the upper insulating film 32, the etching selectivity can be increased, and the selective etching of the upper insulating film 32 can be easily performed.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if several constituent requirements are deleted from the disclosed constituent requirements, the invention can be extracted as an invention as long as a predetermined effect can be obtained.

It is the top view which showed typically the structure of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically the structure of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on a prior art. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on a prior art. It is sectional drawing which showed typically a part of manufacturing process of the semiconductor device which concerns on a prior art.

Explanation of symbols

ST ... select transistor MC ... memory cell 11 ... semiconductor substrate 12 ... element forming portion 13 ... element isolation trenches 14a, 14b, 14c ... source / drain diffusion layer 21 ... lower gate insulating film 22 ... floating gate material film 22a ... floating gate 23 ... Upper gate insulating film 24, 24a ... Polysilicon film 25, 25a ... Tungsten silicide film 26 ... Control gate line 27 ... Silicon nitride film 28 ... Photoresist pattern 30 ... Pattern part 31 ... Lower insulating film (element isolation insulating film) 32 ... Upper insulating film 33 ... Groove 34, 35 ... Recess 41 ... Interlayer insulating film 42 ... Bit line contact 43 ... Bit line 44 ... Mask pattern

Claims (2)

A semiconductor substrate having first and second element forming portions defined by element isolation grooves;
First and second lower gate insulating films respectively formed on the first and second element forming portions;
First and second floating gates formed on the first and second lower gate insulating layers, respectively;
An element formed in the element isolation trench and protruding from the surface of the semiconductor substrate so as to cover a part of the side surfaces of the first and second lower gate insulating films and the side surfaces of the first and second floating gates The isolation insulating film has a recess formed in an upper portion, the bottom of the recess is located below the surface of the semiconductor substrate, and the height of the upper end contacting the side surfaces of the first and second floating gates Are respectively element isolation insulating films formed lower than the height of the upper surfaces of the first and second floating gates;
An upper gate insulating film formed on the surfaces of the first and second floating gates and on the surface of the element isolation insulating film;
A control gate line formed on the upper gate insulating film, the first and second floating gates through the upper gate insulating film and through the upper gate insulating film and the element isolation insulating film; A control gate line formed to be opposed to the entire top surface and side surface of the recess and embedded to the bottom of the recess,
With
The entire side surface of the first floating gate facing the second floating gate is aligned with the side surface defined by the element isolation groove of the first element forming portion, and the second floating gate has the first side. 1. The semiconductor device according to claim 1, wherein the entire side surface facing the one floating gate is aligned with the side surface delimited by the element isolation groove of the second element formation portion. 2. The semiconductor device according to claim 1, wherein a lowermost portion of the control gate line in the recess is positioned lower than lower surfaces of the first and second floating gates.

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