JP4489784B2 - Semiconductor memory - Google Patents

Description

  The present invention relates to a semiconductor memory having a volatile memory cell having a capacitor and having an SRAM interface.

In recent years, mobile devices such as mobile phones have advanced service functions, and the amount of data handled is steadily increasing. Along with this, it is required to increase the capacity of work memory installed in mobile devices.
Conventionally, an SRAM having a simple system configuration has been used as a work memory for mobile devices. However, SRAM is disadvantageous for increasing the capacity because the number of elements constituting a 1-bit cell is larger than that of DRAM. For this reason, a semiconductor memory called a pseudo SRAM has been developed which has both a large capacity of DRAM and ease of use of SRAM.

In addition, mobile devices are considered to have more advanced service functions such as the development of third-generation mobile phone terminals. As mobile devices have higher functions, work memories are required to have higher capacities and higher speeds.
JP-A-9-180437

  A conventional pseudo SRAM has a function called a page mode in which column addresses are continuously supplied and a read operation is executed. The read operation in the page mode is executed by supplying column addresses continuously. Generally, an address has a large number of bits and is supplied to a chip other than a memory in the system, so that skew tends to increase. For this reason, as the access cycle becomes shorter, the ratio of the address skew to the access cycle tends to increase. The greater the address skew, the greater the address setup and hold times for the captured signal. For this reason, the address skew hinders shortening of the access cycle and has a problem that the data transfer rate cannot be improved.

An object of the present invention is to improve the data transfer rate of a semiconductor memory having both the large capacity of DRAM and the ease of use of SRAM.
Another object of the present invention is to enable a system equipped with a semiconductor memory to easily control the semiconductor memory and to simplify the system configuration.

  In the semiconductor memory of the present invention, the memory cell array is composed of volatile memory cells having capacitors. The refresh control circuit generates a refresh request for refreshing the memory cells at a predetermined cycle. When receiving an access command, the semiconductor memory performs a burst access operation for continuously operating the memory cell array. The first burst control circuit outputs a predetermined number of strobe signals in response to the access command. The data input / output circuit continuously inputs data to the memory cell array or outputs data from the memory cell array in synchronization with the strobe signal.

  The arbitration circuit determines which of the refresh operation and the burst access operation is executed first when the refresh request and the access command conflict. For example, when the access command has priority, the refresh operation is executed after the burst access operation. When the refresh request has priority, the burst access operation is executed after the refresh operation. Therefore, in the semiconductor memory that automatically executes the refresh operation, the refresh operation and the burst access operation can be sequentially executed without overlapping.

Further, in a semiconductor memory that automatically executes a refresh operation, the burst access operation can be executed without competing with the refresh operation, so that read data can be output at high speed and write data can be input at high speed. That is, the data transfer rate can be improved.
In the semiconductor memory of the present invention, the arbitration circuit has a refresh holding unit that holds a refresh request during a burst access operation. For this reason, it is possible to prevent the refresh request from being lost when the burst access operation is executed with priority over the refresh operation.

  In the semiconductor memory of the present invention, the second burst control circuit outputs a burst signal corresponding to the output period of a predetermined number of strobe signals. The refresh holding unit holding the refresh request outputs a refresh start signal for starting the refresh operation in response to the completion of the output of the burst signal. For this reason, when the burst access operation is executed with priority, the period from the burst access operation to the start of the refresh operation can be shortened. As a result, the next access command can be supplied quickly, and the data transfer rate can be improved.

  In the semiconductor memory of the present invention, the refresh holding unit holding the refresh request does not wait for the completion of the output of data from the data input / output circuit after the operation of the memory cell array, after the operation of the memory cell array. Output to. In the refresh operation, no data is input / output from / to the outside of the semiconductor memory. Therefore, when the burst access operation is executed with priority, the refresh operation can be started during the burst operation. That is, the period from the burst access operation to the start of the refresh operation can be further shortened. As a result, the next access command can be supplied quickly, and the data transfer rate can be further improved.

  In the semiconductor memory of the present invention, a plurality of word lines are respectively connected to a predetermined number of memory cells. The semiconductor memory has a full burst operation function of sequentially selecting a plurality of word lines and sequentially accessing memory cells in response to an access command. The refresh holding unit holding the refresh request during the full burst operation outputs a refresh start signal for starting the refresh operation when the word line is switched. In the full burst operation, the selection of the word line must be switched, and the memory cell array is temporarily deactivated when the word line is switched. By executing the refresh operation in accordance with the switching of the word lines, the influence of the refresh operation that hinders external access can be minimized. As a result, it is possible to prevent the data transfer rate from decreasing even when the refresh operation is interrupted during the full burst operation.

  In the semiconductor memory of the present invention, the address counter receives an external address supplied in response to an access command, and sequentially generates internal addresses that are continuous with the external address. For this reason, the burst access operation can be executed only by receiving the external command once, and it is difficult to be affected by the skew of the external address. Therefore, the operation cycle can be shortened without depending on the address skew. As a result, the data transfer rate can be further improved.

  In the semiconductor memory of the present invention, a wait signal indicating that the data input / output terminal is invalid is output from the wait terminal during the period from the reception of the access command to the output of the read data. Therefore, a system equipped with a semiconductor memory can access the semiconductor memory at an optimal timing according to the wait signal. For example, a CPU or the like that manages the system can access another device while outputting a wait signal. As a result, the use efficiency of the system bus can be improved.

  In the semiconductor memory of the present invention, data is input / output via a plurality of data input / output terminals. A plurality of data terminal groups are configured by a predetermined number of data input / output terminals. A data valid signal supplied to a data valid terminal corresponding to each data terminal group indicates whether data transmitted to each data terminal group is valid. For this reason, even when the bit width of data is large, a system equipped with a semiconductor memory can efficiently perform data writing and reading.

In the semiconductor memory of the present invention, the mode setting control circuit receives a signal of a predetermined logic value at the external input terminal a plurality of times continuously, and then sends the signal supplied to at least one of the external input terminals to the operation mode. Received as a setting signal to be set. Usually, since an operation mode can be set using a combination of an address signal and a command signal that cannot occur, a dedicated terminal for setting the operation mode can be eliminated. For example, the latency that is the number of clocks from the reception of the access command to the start of the output of read data is set as the operation mode. Alternatively, as an operation mode, a burst length that is the number of times data is continuously input or output is set.
In the semiconductor memory of the present invention, the first burst control circuit outputs a predetermined number of strobe signals in response to an access command for continuously burst-accessing the memory cell array. At this time, the level detection circuit of the first burst control circuit detects that one of the command signals supplied as the access command has changed to the active level. The command signal is, for example, a chip enable signal, an output enable signal, a write enable signal, or the like. The output control circuit of the first burst control circuit starts outputting the strobe signal after measuring a predetermined time from the detection by the level detection circuit. The data input / output circuit continuously inputs data to the memory cell array or outputs data from the memory cell array in synchronization with the strobe signal.
Since the output of read data or the input of write data is started after a predetermined time since the change of the predetermined command signal, a system equipped with a semiconductor memory can easily control the semiconductor memory. That is, the system configuration can be simplified. The semiconductor memory starts a data input / output operation triggered by a change in the command signal. Therefore, the present invention can be applied to both a clock synchronous semiconductor memory and a clock asynchronous semiconductor memory.

In the semiconductor memory of the present invention, the refresh operation and the burst access operation can be sequentially executed without overlapping in the semiconductor memory that automatically executes the refresh operation. Since the burst access operation can be executed without competing with the refresh operation, read data can be output at high speed and write data can be input at high speed. That is, the data transfer rate can be improved.
In the semiconductor memory of the present invention, it is possible to prevent the refresh request from being lost when the burst access operation is executed with priority over the refresh operation.
In the semiconductor memory of the present invention, when the burst access operation is executed with priority, the period from the burst access operation to the start of the refresh operation can be shortened. As a result, the next access command can be supplied quickly, and the data transfer rate can be improved.
In the semiconductor memory of the present invention, the influence of the refresh operation that hinders external access can be minimized by executing the refresh operation in accordance with the switching of the word lines.
In the semiconductor memory of the present invention, the operation cycle can be shortened without depending on the address skew, and the data transfer rate can be further improved.
In the semiconductor memory of the present invention, a system in which the semiconductor memory is mounted can access the semiconductor memory at an optimal timing according to the wait signal. For this reason, the use efficiency of the system bus can be improved.
In the semiconductor memory of the present invention, even when the data bit width is large, a system equipped with a semiconductor memory can efficiently execute data writing and reading.
In the semiconductor memory of the present invention, a dedicated terminal for setting the operation mode can be eliminated.
In the semiconductor memory of the present invention, a system equipped with a semiconductor memory can easily control the semiconductor memory. That is, the system configuration can be simplified.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a first embodiment of the semiconductor memory of the present invention. In the figure, a signal line indicated by a bold line is composed of a plurality of bits. Double circles on the left side of the figure indicate external input terminals. A signal preceded by “/” indicates negative logic. A signal with “Z” at the end indicates positive logic. In the following description, the signal name may be abbreviated, such as “external clock signal CLK” as “CLK signal” and “chip enable signal / CE” as “/ CE signal”.

  This semiconductor memory has DRAM memory cells and is formed as a pseudo SRAM having an SRAM interface. The pseudo SRAM includes a refresh control circuit 10, an arbitration circuit 12, a command decoder 14, a burst control circuit 16, a mode setting control circuit 18, a burst address counter 20, a timing control circuit 22, an address latch 24, an address decoder 26, a memory cell array 28, A read / write amplifier 30, a burst transfer register 32, a data output control circuit 34, and a data input control circuit 36 are provided.

The refresh control circuit 10 includes a timer and outputs a refresh request signal REFZ for refreshing the memory cells MC of the memory cell array 28 at a predetermined cycle.
The arbitration circuit 12 determines first arrival or later arrival of the refresh request signal REFZ and the access command, and outputs a control signal corresponding to the first arrival signal. The access command is supplied from outside the pseudo SRAM when the memory cell array 28 is continuously accessed (burst access) and the read operation or the write operation is continuously executed. The access command is recognized when both the chip enable signal / CE and the address status signal / ADS are at a low level. In burst access, a plurality of data is output or input by one access command (burst access operation).

  The arbitration circuit 12 outputs the refresh activation signal REFS1 and the active signal ACTZ when determining the first arrival of the refresh request signal REFZ, and outputs the active signal ACTZ when determining the first arrival of the access command. The chip enable signal / CE and the address status signal / ADS are supplied via a chip enable terminal and an address status terminal, respectively. The pseudo SRAM validates the address signal ADD supplied when the address status signal / ADS is low, and invalidates the address signal ADD supplied when the address status signal / ADS is high. Since the pseudo SRAM has an SRAM interface, a row address and a column address are supplied simultaneously to the address signal ADD.

  The command decoder 14 decodes the chip enable signal / CE, the output enable signal / OE, and the write enable signal / WE (hereinafter collectively referred to as the command signal CMD) when the address status signal / ADS is at a low level, and according to the decoding result The control signal is output to the timing control circuit 22, the data output control circuit 34, the data input control circuit 36, and the like. The output enable signal / OE and the write enable signal / WE are supplied via the output enable terminal and the write enable terminal, respectively. The chip enable terminal, the output enable terminal, and the write enable terminal are also referred to as command terminals.

  The burst control circuit 16 receives the external clock signal CLK, the chip enable signal / CE, the burst address advance signal / ADV, and the latency signal LTC from the mode setting control circuit 18, and receives the burst signal BSTZ, the burst clock signal BCLK (strobe signal), A timing signal and a wait signal WAIT are output to the timing control circuit 22. The external clock signal CLK and the burst address advance signal / ADV are supplied via the external clock terminal and the burst address advance terminal, respectively. The wait signal WAIT is output to the outside of the pseudo SRAM via the wait terminal. The burst control circuit 16 operates as a first burst control circuit that outputs a burst clock signal BCLK and a second burst control circuit that outputs a burst signal BSTZ.

The mode setting control circuit 18 includes a chip enable signal / CE, an output enable signal / OE, a write enable signal / WE, an upper byte signal / UB (first data valid signal), and a lower byte signal / LB (second data valid signal). In response to the address signal ADD, the latency signal LTC and the burst length signal BL are output. The / UB signal and the / LB signal are supplied via an upper byte terminal (first data valid terminal) and a lower byte terminal (second data valid terminal), respectively. The / UB and / LB signals are signals for masking part of the read data and write data. The mode setting control circuit 18 is a circuit for setting the operation mode of the pseudo SRAM and can be set from the outside. It has a mode register. Latency LTC and burst length BL can be set as operation modes. The set latency LTC and burst length BL are output as latency signal LTC and burst length signal BL. Latency LTC is the number of clocks from when an access command (read command) is supplied until the first data is output. The burst length BL is the number of data outputs or the number of data inputs corresponding to one access command.

  The burst address counter 20 generates an internal address signal IADD continuous with the address signal ADD in synchronization with the timing signal from the timing control circuit 22. The burst address counter 20 generates the internal address signal IADD by one less than the burst length indicated by the burst length signal BL. The burst address counter 20 stops the count-up operation while receiving the high level of the burst address advance signal / ADV. The address signal ADD is supplied via an address terminal.

The timing control circuit 22 receives control signals from the arbitration circuit 12, the command decoder 14, the burst control circuit 16, and the like, and controls operations of the burst address counter 20, the address latch 24, the address decoder 26, the read / write amplifier 30, and the like. Output timing signal.
The address latch 24 latches the address signal ADD in synchronization with the address latch signal ELAT, latches the internal address signal IADD in synchronization with the address latch signal ILAT, and outputs the latched signal to the address decoder 26.

  The address decoder 26 decodes the address signal latched by the address latch 24 and outputs a signal for selecting the memory cell MC in the memory cell array 28. Specifically, the address decoder 26 outputs a word line signal for selecting a word line WL, which will be described later, and a column line signal for turning on a column switch SW, which will be described later, according to the address signal.

  The memory cell array 28 includes a plurality of volatile memory cells MC arranged in a matrix, a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells MC, and a plurality of bits connected to the bit lines BL. A sense amplifier SA and a plurality of column switches SW for connecting the bit lines BL to the read / write amplifier 30 are provided. The memory cell MC is the same as a memory cell of a general DRAM, and includes a capacitor for holding data as a charge and a transfer transistor arranged between the capacitor and the bit line BL. The gate of the transfer transistor is connected to the word line WL.

  The column switches SW are classified into a first column switch group corresponding to the / UB signal and a second column switch group corresponding to the / LB signal. During the burst write operation, the first column switch group is turned on according to the address signal only when the / UB signal is at a low level. During the burst write operation, the second column switch group is turned on according to the address signal only when the / LB signal is at a low level. That is, the write data is masked by controlling the column switch SW.

  Actually, the timing control circuit 22 operates the address decoder in accordance with the / UB and / LB signals and outputs the column selection signal CL, whereby the operations of the first and second column switch groups are controlled. The mask control of the write data may be performed until the write data received at the data input / output terminal DQ is transmitted to the column switch SW. Therefore, mask control of write data can be easily performed.

  The read / write amplifier 30 outputs parallel read data from the memory cell array 28 to the data bus DB in synchronization with the read amplifier enable signal RAEN. The read / write amplifier 30 outputs the parallel write data from the burst transfer register 32 to the memory cell array 28 in synchronization with the write amplifier enable signal WAEN.

  The burst transfer register 32 has a plurality of data registers (DT0, DT1, etc.) that hold data. The burst transfer register 32 converts parallel read data from the read / write amplifier 30 into serial data, and outputs it to the common data bus CDB in synchronization with the burst clock signal BCLK. The burst transfer register 32 converts serial write data from the common data bus CDB into parallel data, and outputs the parallel data to the read / write amplifier 30 in synchronization with the burst clock signal BCLK.

  The data output control circuit 34 is activated during a read operation and outputs read data on the data bus DB to the data input / output terminal DQ. The data input / output terminal DQ is composed of 16 bits. The data output control circuit 34 outputs the upper 8 bits of the 16-bit read data when the upper byte signal / UB is at a low level, and outputs the 16-bit read data when the lower byte signal / LB is at a low level. The lower 8 bits are output. The data input / output terminal DQ includes an 8-bit first data terminal group corresponding to the / UB signal and an 8-bit second data terminal group corresponding to the / LB signal.

  The data input control circuit 36 is activated during a write operation, receives write data via the data input / output terminal DQ, and outputs the received data to the common data bus CDB. The burst transfer register 32, the data output control circuit 34, and the data input control circuit 36 operate as a data input / output circuit for continuously inputting or outputting a plurality of data.

FIG. 2 shows details of the arbitration circuit 12 shown in FIG.
The arbitration circuit 12 includes a refresh determination unit 12a, a refresh holding unit 12b, a command generation unit 12c, and an access holding unit 12d.
The refresh determination unit 12a has an RS flip-flop. The refresh determination unit 12a operates during a period in which the active signal ACTZ is at a low level, and determines first arrival of the refresh request signal REFZ and the access signal ACSZ. The access signal ACSZ is a signal indicating the OR logic (negative logic) of the / CE signal and the / ADS signal. That is, when the / CE signal or the / ADS signal changes to a low level, the supply of the access command is detected and the ACSZ signal is output. The refresh determination unit 12a changes the refresh enable signal REFENZ to a high level when determining the first arrival of the REFZ signal, and holds the refresh enable signal REFENZ at a low level when determining the first arrival of the ACSZ signal.

  The refresh holding unit 12b holds the refresh request signal REFZ when the refresh enable signal REFENZ is low or the burst signal BSTZ is high. The held refresh request signal REFZ is output as refresh activation signals REFS1 and REFS2 in synchronization with the falling edge of the burst signal BSTZ. The refresh holding unit 12b outputs refresh activation signals REFS1 and REFS2 in response to the refresh request signal REFZ when the refresh enable signal REFENZ is high and the burst signal BSTZ is low. In addition, the refresh holding unit 12b stops outputting the refresh activation signal REFS1 in synchronization with the refresh stop signal RSTPZ that is output when the refresh operation is completed.

  The burst signal BSTZ is a signal output during a burst access operation (during burst reading or burst writing). That is, according to the present invention, during the burst operation, the refresh request is held without disappearing, and the refresh operation corresponding to the held refresh request is performed after the burst operation of the memory cell array 28 (before the completion of the burst operation of the pseudo SRAM). Executed. For this reason, the period from the burst operation to the start of the refresh operation can be shortened, and the data transfer rate can be improved.

The command generator 12c outputs an active signal ACTZ in response to the refresh activation signal REFS2 or the access activation signal ACSS. The burst access operation or the refresh operation is executed by the output of the active signal ACTZ.
The access holding unit 12d outputs an access activation signal ACSS in response to the access signal ACSZ when the active signal ACTZ is at a low level. When the access holding unit 12d receives the access signal ACSZ when the active signal ACTZ is at a high level, the access holding unit 12d holds the access signal ACSZ without disappearing, and synchronizes the held signal ACSZ with the falling edge of the active signal ACTZ. Output as access activation signal ACSS. In general, during a burst access operation, an access request for the memory cell array 28 by a new access command is not supplied during the operation of the memory cell array 28. Therefore, the access signal ACSZ is held when the active signal ACTZ is output along with the refresh operation.

FIG. 3 shows the operation of the arbitration circuit 12 shown in FIG. FIG. 3 shows a case where a refresh request is generated immediately after receiving an access command. That is, the refresh operation is executed after the burst read operation. In this example, the read latency is set to “4”, and the burst length is set to “4”.
First, the address signal ADD (A0), / ADS signal, / CE signal, and / OE signal are supplied in synchronization with the rising edge of the 0th CLK signal (FIG. 3A). That is, a read command is supplied. The arbitration circuit 12 outputs the access signal ACSZ in response to the / ADS signal and the / CE signal (FIG. 3B).

  After the access signal ACSZ is output, the refresh request signal REFZ is output (FIG. 3 (c)). The refresh determination unit 12a determines the arrival of the ACSZ signal and holds the refresh enable signal REFENZ at a low level. The refresh holding unit 12b receives the low-level REFENZ signal, and holds the refresh request signal REFZ until the refresh operation is started as shown by a broken line in the drawing (FIG. 3 (d)).

The access holding unit 12d receives the ACSZ signal and outputs an access activation signal ACSS. The command generator 12c receives the ACSS signal and outputs an active signal ACTZ (FIG. 3 (e)). Due to the change of the ACTZ signal to the high level, the state of the memory cell array 28 changes from the standby state STBY to the active state ACTV.
The burst control circuit 16 shown in FIG. 1 receives the access command and outputs the burst signal BSTZ and the wait signal WAIT (FIGS. 3 (f) and 3 (g)). A system equipped with a pseudo SRAM receives a wait signal WAIT, detects that read data is not output from the pseudo SRAM, and accesses another device, for example. For this reason, the use efficiency of the system bus is improved.

Thereafter, the burst read operation is started, and the first read data D0 and D1 are output to the data bus DB (FIG. 3 (h)). Thereafter, the read operation of the memory cell array 28 is completed, and read data D2 and D3 are output. The burst control circuit 16 changes the burst signal BSTZ to a low level (FIG. 3 (i)).
The memory cell array 28 is deactivated after the read data D2 and D3 are output. The refresh holding unit 12b of the arbitration circuit 12 outputs refresh activation signals REFS1 and REFS2 for starting the refresh operation in synchronization with the falling edge of the burst signal BSTZ (FIG. 3 (j)). In this way, the refresh activation signals REFS1 and REFS2 are output without waiting for the completion of the output of the read data D2 and D3 from the burst transfer register 32 after the operation of the memory cell array 28. Since the refresh operation not using the data bus DB is started before the output of the read data is completed, the use efficiency of the data bus DB can be improved. Specifically, the next access command can be received at an early timing.

The active signal ACTZ changes to the high level again in response to the refresh activation signal REFS2, and the refresh operation is executed (FIG. 3 (k)). That is, the state of the memory cell array 28 changes to the refresh state REF while the read data D2 and D3 are being transferred to the data input / output terminal DQ.
In synchronization with the completion of the refresh operation, the refresh stop signal RSTPZ is output, and the refresh activation signal REFS1 and the active signal ACTZ change to low level (FIGS. 3 (l) and 3 (m)). Then, the state of the memory cell array 28 changes to the standby state STBY. Thereafter, the / CE signal and the / OE signal are set to the high level, and the burst read operation is completed (FIG. 3 (n)).

  FIG. 4 is a timing chart showing another operation of the arbitration circuit 12. Detailed description of the same operation as in FIG. 3 is omitted. FIG. 4 shows a case where a refresh request is generated immediately before receiving an access command. That is, the refresh operation is executed with priority over the burst read operation. In this example, the read latency is set to “4”, and the burst length is set to “4”.

  First, the refresh request signal REFZ is output (FIG. 4 (a)). The refresh determination unit 12a determines the arrival of the refresh request signal REFZ, and changes the refresh enable signal REFENZ to a high level (FIG. 4B). At this time, since the memory cell array 28 is in the standby state STBY, the burst signal BSTZ is not output. Therefore, the refresh holding unit 12b receives the REFENZ signal and outputs refresh activation signals REFS1 and REFS2 (FIG. 4C).

  Thereafter, in synchronization with the rising edge of the 0th CLK signal, the address signal ADD (A0), the / ADS signal, the / CE signal, and the / OE signal are supplied, and the access ACSZ changes to the high level (FIG. 4 ( d)). The command generator 12c outputs an active signal ACTZ in response to the refresh activation signal REFS2 (FIG. 4 (e)). Then, a refresh operation is executed. The wait signal WAIT changes to a high level during the refresh and at the beginning of the active period (FIG. 4 (f)). Details of the wait signal WAIT will be described later with reference to FIG.

  The access holding unit 12d receives the high-level ACTZ signal and holds the ACSZ signal (FIG. 4 (g)). The access holding unit 12d outputs the ACTZ signal in synchronization with the falling edge of the ACTZ signal accompanying the completion of the refresh operation (FIG. 4 (h)). Due to the change of the ACTZ signal to the high level, the state of the memory cell array 28 directly changes from the refresh state REF to the active state ACTV without going through the standby state STBY. For this reason, the burst read operation can be started early.

Thereafter, a burst read operation is executed as in FIG. 3, and read data D0-D4 are output (FIG. 4 (i)).
FIG. 5 is a timing chart showing another operation of the arbitration circuit 12. Detailed description of the same operation as in FIG. 3 is omitted. FIG. 5 shows a case where a refresh request is generated immediately after receiving an access command when the full burst mode is set as the operation mode. The full burst mode is an operation mode in which data is continuously output (or input) while the / CE signal is at a low level in response to one access command.

  In the full burst mode, the burst address counter shown in FIG. 1 sequentially generates the internal address signal IADD while the / CE signal is at a low level. More specifically, after the internal address signal IADD corresponding to the selected word line WL is sequentially generated, the internal address signal IADD corresponding to the adjacent word line WL is sequentially generated. That is, the selection switching of the word line WL is performed during the full burst operation.

  In the figure, word lines WL corresponding to read data Dn-3, Dn-2, Dn-1, and Dn are different from word lines WL corresponding to read data D0, D1, D2, and D3. That is, the selection switching of the word line WL is performed in the eighth clock period. Then, a refresh operation is executed when the word line WL is switched. The operations of reference numerals (a) to (m) in the figure are the same as those in FIG.

A wait signal WAIT is output during a period in which read data cannot be output due to the switching operation of the word line WL (FIG. 5 (n)).
In order to switch the word line WL, the arbitration circuit 12 and the burst control circuit 16 shown in FIG. 1 reactivate the once deactivated burst signal BSTZ and active signal ACTZ (FIG. 5 (o)). Then, the burst read operation of the memory cell MC connected to the newly selected word line WL is executed.

FIG. 6 shows details of the burst control circuit 16 shown in FIG.
The burst control circuit 16 includes a 7-bit shift register 16a, a combinational circuit 16b that outputs the burst clock signal BCLK for the number of times corresponding to the burst length BL, and a flip-flop that outputs the wait signal WAIT1 until the burst clock signal BCLK is output. A circuit 16c and a weight control circuit 16d are provided. "DLY" and "PLS" in the figure indicate a delay circuit and a pulse generation circuit, respectively.

  The wait control circuit 16d outputs a wait signal WAIT2 when data is not input / output to / from the data input / output terminal DQ during the burst access operation. For example, the wait signal WAIT2 is output when the selection of the word line is switched during the full burst operation. The wait signal WAIT output to the wait terminal is the OR logic of the wait signals WAIT1 and WAIT2.

  FIG. 7 shows the operation of the burst control circuit 16 shown in FIG. In this example, a case where latency = “4” is set in the mode register of the mode setting control circuit 18 shown in FIG. 1 will be described. At this time, only the NAND gate receiving the count signal BCNT3 among the NAND gates receiving the LTC signal shown in FIG. 6 operates as an inverting circuit, and the other NAND gates output a high level.

  First, an access command is supplied (in this example, the / OE signal is a low level, so a read command), and the burst control circuit 16 shown in FIG. 1 changes the burst signal BSTZ to a high level (FIG. 7 (a)). . The reset of the shift register 16a is released by the high level burst signal BSTZ. The shift register 16a sequentially changes the count signals BCNT1-4 to a high level in synchronization with the external clock signal CLK (FIG. 7 (b)).

The flip-flop circuit 16c is set in synchronization with the rising edge of the count signal BCNT1, and the wait signal WAIT1 changes to high level (FIG. 7 (c)).
The enable signal BCNTEN changes to a high level in synchronization with the rising edge of the count signal BCNT3 (FIG. 7 (d)). The flip-flop circuit 16c is reset by the high level enable signal BCNTEN, and the wait signal WAIT1 changes to the low level (FIG. 7 (e)).

  The burst clock signal BCLK is output in synchronization with the external clock signal CLK by the high level enable signal BCNTEN (FIG. 7 (f)). The burst clock signal BCLK (strobe signal) is output the number of times corresponding to the burst length BL set in the mode register. Then, read data is output to the data input / output terminal DQ in synchronization with the burst clock signal BCLK.

  The burst control circuit 16 changes the burst signal BSTZ to a low level in synchronization with the sixth external clock signal CLK (FIG. 7 (g)). That is, the burst signal BSTZ is output corresponding to a period during which the burst clock signal BCLK is output. The shift register 16 is reset by the low level burst signal BSTZ, and the count signals BCNT1-4 change to the low level (FIG. 7 (h)).

  Due to the low level of the count signal BCNT3, the enable signal BCNTEN changes to a low level, and the output of the burst clock signal BCLK is stopped (FIG. 7 (i)). As a result, the output of the read data is started corresponding to the latency LTC set in the mode register, and the read data is output the number of times corresponding to the burst length BL (FIG. 7 (j)).

FIG. 8 shows a mode register setting method in the mode setting control circuit 18 shown in FIG.
The mode register is supplied with a predetermined command CMD (CMD1, CMD2, CMD3, CMD4) and a predetermined address ADD (CODE1, CODE2, CODE3, CODE4) four times in succession, and then a predetermined code CODE5, Set when CODE6 is supplied. The burst length BL is set according to the code CODE5, and the latency LTC is set according to the code CODE6. That is, the mode register receives the codes CODE5 and CODE6 as setting signals for setting the operation mode. For example, the operation mode is set to the 8-word burst mode when the code CODE5 is hexadecimal “0”, and is set to the full burst mode when the code CODE5 is hexadecimal “3”.

FIG. 9 shows a read operation in the full burst mode in the above-described pseudo SRAM.
First, the address signal ADD (An), the / ADS signal, the / CE signal, and the / OE signal are supplied in synchronization with the rising edge of the 0th CLK signal (FIG. 9A). The timing control circuit 22 shown in FIG. 1 outputs an address latch signal ELAT that latches an external address signal ADD (FIG. 9B). The address latch 24 latches the address signal ADD (An) in synchronization with the address latch signal ELAT (FIG. 9 (c)).

  Next, the timing control circuit 22 outputs a read amplifier enable signal RAEN (FIG. 9 (d)). The read / write amplifier 30 is operated by the read amplifier enable signal RAEN, and parallel read data D0 and D1 are output to the data buses DB0 and DB1 (FIG. 9 (e)). The read data D0 and D1 are converted in series by the data register of the burst transfer register 32 in synchronization with the burst clock signal BCLK, and sequentially output to the common data bus CDB. The read data D0 and D1 are output from the data input / output terminal DQ in synchronization with the clock signal CLK (FIG. 9 (f)).

Next, the timing control circuit 22 outputs an address latch signal ILAT (FIG. 9 (g)). The address latch 24 latches the internal address signal IADD (An + 1) in synchronization with the address latch signal ILAT (FIG. 9 (h)). As described above, read data D2 and D3 corresponding to the internal address signal IADD are output (FIG. 9 (i)).
Thereafter, the timing control circuit 22 sequentially outputs the address latch signal ILAT (FIG. 9 (j)), and the read data is sequentially output in accordance with the internal address signal IADD generated by the burst address counter 20 (FIG. 9). 9 (k)).

FIG. 10 shows a write operation in the full burst mode in the above-described pseudo SRAM.
First, in synchronization with the rising edge of the 0th CLK signal, the address signal ADD (An), / ADS signal, / CE signal, and / WE signal are supplied (FIG. 10A). The timing control circuit 22 shown in FIG. 1 outputs an address latch signal ELAT that latches an external address signal ADD (FIG. 10B). The address latch 24 latches the address signal ADD (An) in synchronization with the address latch signal ELAT (FIG. 10 (c)).

  In the write operation, write data is sequentially supplied in synchronization with the rising edge of the CLK signal that receives the access command (FIG. 10 (d)). The data register of the burst transfer register 32 sequentially holds the write data on the common data bus CDB in synchronization with the burst clock signal BCLK, and transfers the held data to the data buses DB0 and DB1, respectively. That is, the serial write data on the common data bus CDB is converted into parallel write data (FIG. 10E).

The read / write amplifier 30 writes the write data on the data buses DB0 and DB1 to the memory cell array 28 in synchronization with the write amplifier enable signal WAEN (FIG. 10 (f)).
Thereafter, as in FIG. 9, the internal address signal IADD is latched in synchronization with the address latch signal ILAT (FIG. 10 (g)). The write data D3, D4, D5,... Are sequentially written in the memory cells MC corresponding to the internal address signal IADD (FIG. 10 (h)).

FIG. 11 shows the function of the burst address advance signal / ADV.
The / ADV signal is supplied to suspend the burst access operation and maintain the output of read data. For example, when a high level / ADV signal is supplied in synchronization with the rising edge of the fourth clock signal CLK, the burst access operation is suspended, and the read data D1 output in synchronization with the next clock cycle is It is maintained not only in the fourth clock cycle but also in the fifth clock cycle. That is, by supplying the / ADV signal, the internal operation of the pseudo SRAM is shifted after one clock cycle.

FIG. 12 shows the functions of the lower byte signal / LB and the upper byte signal / UB during the burst read operation. In the figure, for easy understanding, the common data bus CDB is divided into LCDB corresponding to the / LB signal and UCDB corresponding to / UB.
The / LB signal is a signal supplied to validate the lower 8 bits of data. The / UB signal is a signal supplied to validate the upper 8 bits of data. In this embodiment, in a read operation, when a high level / LB signal (or / UB signal) is supplied in synchronization with the rising edge of the clock signal CLK, read data output in synchronization with the next clock cycle. Output is prohibited. That is, an output buffer (not shown) in the data output control circuit 34 shown in FIG. 1 is deactivated, and the data input / output terminal DQ is in a high impedance state.

  FIG. 13 shows the functions of the lower byte signal / LB and the upper byte signal / UB during the burst write operation. In the figure, for easy understanding, the common data bus CDB is divided into LCDB corresponding to the / LB signal and UCDB corresponding to / UB. Further, the data buses DB0 and DB1 are described separately as LDB0 and LDB1 corresponding to the / LB signal and UDB0 and UDB1 corresponding to / UB.

  In this embodiment, when a high level / LB signal (or / UB signal) is supplied in synchronization with the rising edge of the clock signal CLK in the write operation, the write supplied in synchronization with the clock signal CLK is performed. The data becomes invalid. More specifically, when the / LB signal (or / UB signal) is at a high level, the corresponding column selection signal CL (LCL0, UCL0, LCL1, UCL1) is not output, and the column switch SW is not turned on. Therefore, the write data corresponding to the high level / LB signal (or / UB signal) is not written to the memory cell MC.

For example, the / UB signal synchronized with the 0th clock signal CLK is at a high level (B1). The / LB signal synchronized with the first clock signal CLK is at a high level (C1). Therefore, the corresponding column selection signals UCL0 and LCL1 are not output, and the write data transmitted to the data buses LDB1 and UDB0 is not written to the memory cell MC.
As described above, in the first embodiment, when the refresh request signal REFZ competes with the supply of the access command, the arbitration circuit 12 determines which one of the refresh operation and the burst access operation is executed first. Therefore, in the pseudo SRAM, the refresh operation and the burst access operation can be sequentially executed without overlapping. Since the burst access operation can be executed without competing with the refresh operation, read data can be output at high speed and write data can be input at high speed. That is, the data transfer rate can be improved.

  Since the refresh holding unit 12b that holds the refresh request signal REFZ during the burst access operation is formed in the arbitration circuit 12, it is possible to prevent the refresh request signal REFZ from being lost when the burst access operation is performed with priority over the refresh operation. Since the access holding unit 12d that holds the access command during the refresh operation is formed in the arbitration circuit 12, it is possible to prevent the access request from being lost when the refresh operation is performed with priority over the burst access operation.

  The refresh holding unit 12b outputs the refresh activation signals REFS1 and REFS2 in response to the completion of the output of the burst signal BSTZ. For this reason, when the burst access operation is executed with priority, the period from the burst access operation to the start of the refresh operation can be shortened. As a result, the next access command can be supplied quickly, and the data transfer rate can be improved.

Similarly, the refresh holding unit 12b outputs the refresh activation signals REFS1 and REFS2 without waiting for the completion of the output of the read data from the burst transfer register 32. Therefore, the refresh operation can be started during the burst operation, and the data transfer rate can be further improved.
During the full burst operation, the refresh holding unit 12b outputs the refresh activation signals REFS1 and REFS2 when the word line WL is switched. By executing the refresh operation in accordance with the interruption period of the burst operation (when the word line is switched), the influence of the refresh operation that hinders external access can be minimized. As a result, it is possible to prevent the data transfer rate from decreasing even when the refresh operation is interrupted during the full burst operation.

  The burst address counter 20 sequentially generates the internal address signal IADD necessary for the burst operation in response to the address signal ADD supplied corresponding to the access command. By generating the address signal necessary for the burst operation inside the pseudo SRAM, it is possible to reduce the influence of the address signal skew. Therefore, the operation cycle can be shortened without depending on the address skew, and the data transfer rate can be further improved.

  A wait terminal that outputs a wait signal WAIT indicating that the data input / output terminal DQ is invalid is formed. Therefore, a system equipped with a pseudo SRAM can access the pseudo SRAM at an optimum timing in accordance with the wait signal WAIT. For example, a CPU or the like that manages the system can access another device while the wait signal WAIT is being output. As a result, the use efficiency of the system bus can be improved.

Since the input of write data and the output of read data are masked according to the / UB and / LB signals, even if the bit width of the data signal DQ is large, the system equipped with pseudo SRAM efficiently uses the data signal DQ. Write and read efficiently.
Since the write data is masked by turning off the column switch that operates at a relatively late timing in the write operation period, the mask control of the write data can be facilitated.

The mode setting control circuit receives a signal of a predetermined logical value at the address terminal and the command terminal four times in succession, then sets the read latency LTC and burst length BL to the signals CODE5 and CODE6 supplied to the command terminal. Received as a setting signal. This eliminates the need for a dedicated terminal for setting the operation mode.
During the burst operation, after the read data is transferred to the data register of the burst transfer register 32, the memory cell array 28 is deactivated. By quickly deactivating the memory cell array 28 at the time of burst reading, the operation for the refresh request or the next access request can be started quickly. As a result, the data transfer rate can be improved.

FIG. 14 shows a second embodiment of the semiconductor memory of the present invention. The same elements as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
In this embodiment, a timing control circuit 38, a read / write amplifier 40 and a burst transfer register 42 are formed instead of the timing control circuit 22, the read / write amplifier 30 and the burst transfer register 32 of the first embodiment. . The bit width of the data bus DB connecting the read / write amplifier 40 and the burst transfer register 42 is the same as the bit width of the common data bus CDB. Other configurations are the same as those of the first embodiment.

  The timing control circuit 38 outputs the read amplifier enable signal RAEN or the write amplifier enable signal WAEN in synchronization with each rising edge of the clock signal CLK during the burst operation. The burst transfer register 42 directly transfers read data from the read / write amplifier 40 to the data output control circuit 34 via the common data bus CDB. That is, the read data is not subjected to parallel / serial conversion. The burst transfer register 42 directly outputs the write data from the data input control circuit 36 to the read / write amplifier 40 via the data bus DB. That is, write data is not serial-parallel converted.

FIG. 15 shows a full burst read operation of the pseudo SRAM shown in FIG. Detailed description of the same operation as that of the first embodiment (FIG. 5) is omitted.
In FIG. 15, a refresh request is generated immediately after receiving an access command. That is, the refresh operation is performed after the read operation. In this example, the read latency LTC is set to “4”.

  First, a read command is supplied in synchronization with the rising edge of the 0th CLK signal, and the arbitration circuit 12 shown in FIG. 2 outputs the access signal ACSZ (FIG. 15 (a)). The refresh determination unit 12a of the arbitration circuit 12 receives the refresh request signal REFZ after the read command is supplied. For this reason, the refresh enable signal REFENZ is held at a low level (FIG. 15B). The command generator 12c outputs an active signal ACTZ in response to the access signal ACSZ (FIG. 15 (c)). Due to the change of the active signal ACTZ to the high level, the state of the memory cell array 28 changes from the standby state STBY to the active state ACTV.

  Next, the burst signal BSTZ changes to a high level, and the wait signal WAIT changes to a high level for a predetermined period. The timing control circuit 38 outputs the read amplifier enable signal RAEN in synchronization with the rising edges of the 3-6th clock signal CLK (FIG. 15 (d)). The latency control circuit 16 outputs the burst clock signal BCLK in synchronization with the rising edge of the 3-6th clock signal CLK (FIG. 15 (e)). Then, a read operation is executed, and read data Dn-3, Dn-2, Dn-1, and Dn are sequentially output to the data bus DB (FIG. 15 (f)).

  In this embodiment, the read / write amplifier 40 outputs read data Dn-3, Dn-2, Dn-1, and Dn for each clock signal CLK. For this reason, the memory cell array 28 needs to operate until the fourth read data Dn is transferred to the read / write amplifier 40. For this reason, the period of the active state ACTV is one clock cycle longer than that of the first embodiment (FIG. 5) (FIG. 15G).

After the read operation is completed, a refresh operation is executed (FIG. 15 (h)). The refresh operation is executed with a delay of one clock cycle from the first embodiment (FIG. 5). For this reason, the start of the next read operation in the full burst operation is also delayed by one clock cycle. Therefore, the data transfer rate is lower than that in FIG.
However, by enabling a burst operation in the pseudo SRAM and performing a refresh operation between burst operations, the data transfer rate becomes higher than the conventional one.
Also in this embodiment, the same effect as that of the first embodiment described above can be obtained.

FIG. 16 shows a third embodiment of the semiconductor memory of the present invention. The same elements as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
In this embodiment, instead of the command decoder 14, the burst control circuit 16, the mode setting control circuit 18 and the burst transfer register 32 of the first embodiment, a command decoder 44, a burst control circuit 46 (first burst control circuit). A mode setting control circuit 48 and a burst transfer register 50 are formed. Other configurations are the same as those of the first embodiment.

  When the command decoder 44 receives a read command and a write command via the command terminal, the command decoder 44 outputs a read control signal RDZ and a write control signal WRZ, respectively. The burst control circuit 46 receives the read control signal RDZ during the read operation, counts the number of clocks according to the number of times corresponding to the read latency signal RLTC, and then outputs the read burst clock signal RBCLK as many times as according to the burst length BL. The burst control circuit 46 receives the write control signal WRZ during the write operation, counts the number of clocks according to the write latency signal WLTC, and then outputs the write burst clock signal WBCLK as many times as the burst length BL. .

The mode setting control circuit 48 has a mode register that can be set from the outside. A burst length BL, a read latency RLTC, and a write latency WLTC are set in the mode register. The set values are output to the burst control circuit 46 as a burst length signal BL, a read latency signal RLTC, and a write latency signal WLTC. The read latency RLTC is the number of clocks from when the read command is supplied until the first data is output. More specifically, the read latency RLTC indicates the number of clocks until the first data is output from the falling edge of the chip enable signal / CE during the read operation.
The write latency WLTC is the number of clocks from when a write command is supplied until the first data is input. More specifically, the write latency WLTC indicates the number of clocks from the falling edge of the chip enable signal / CE until the first data is input during the write operation. As described above, this embodiment is characterized in that the latency can be set for each of the read operation and the write operation.

  The burst transfer register 50 has a plurality of data registers (DT0, DT1, etc.) that hold data. The burst transfer register 50 converts parallel read data from the read / write amplifier 30 into serial data, and outputs the serial data to the common data bus CDB in synchronization with the read burst clock signal RBCLK. The burst transfer register 50 converts serial write data from the common data bus CDB into parallel data, and outputs the parallel data to the read / write amplifier 30 in synchronization with the write burst clock signal WBCLK.

17 and 18 show details of the burst control circuit 46 shown in FIG. FIG. 17 shows a circuit for generating the read burst clock signal RBCLK and the wait signal WAIT during the read operation in the burst control circuit 46. FIG. 18 shows a circuit for generating the write burst clock signal WBCLK during the write operation in the burst control circuit 46.
In FIG. 17, a burst control circuit 46 includes a clock generation circuit 46a, a 7-bit shift register 46b, a combinational circuit 46c that outputs a read burst clock signal RBCLK, a flip-flop circuit 16c that outputs a wait signal WAIT1, a wait control circuit 16d, It has a delay circuit DLY and a pulse generation circuit PLS. The clock generation circuit 46a operates when the chip enable signal / CE is at a low level, and outputs the clock signal CLK as the internal clock signal RCLK1. The clock generation circuit 46a operates as a detection circuit that detects that a chip enable signal / CE (command signal) supplied as an access command has changed to an active level (low level).

The shift register 46b and the combination circuit 46c are substantially the same circuits as the shift register 16a and the combination circuit 16b (FIG. 6) of the first embodiment. For this reason, the basic operations of the shift register 46b and the combinational circuit 46c are the same as those in the first embodiment (FIG. 7). The numbers given to the 2-input NAND gate and the inverter of the combinational circuit 46c correspond to the value of the read latency RLTC. For example, when the read latency RLTC is set to “4”, only NAND gates marked with “4” are activated.
When the output enable signal / OE is at a low level (= RDZ signal is at a high level), the combinational circuit 46c is delayed by the number of clocks corresponding to the read latency RLTC from the supply of the chip enable signal / CE (supply of the read command). The read burst clock signal RBCLK is output the number of times corresponding to the burst length BL. That is, the shift register 46b and the combinational circuit 46c operate as an output control circuit that starts outputting the read burst clock signal RBCLK after measuring a predetermined time after the chip enable signal / CE changes to the active level.
Since the circuit for generating the wait signal WAIT is the same as that in the first embodiment, description thereof is omitted.

  In FIG. 18, the burst control circuit 46 includes a clock generation circuit 46d, an 8-bit shift register 46e, and a combinational circuit 46f that outputs a write burst clock signal WBCLK. The clock generation circuit 46d operates when the chip enable signal / CE is at a low level, and outputs the clock signal CLK as the internal clock signal WCLK1. The clock generation circuit 46d operates as a detection circuit that detects that a chip enable signal / CE (command signal) supplied as an access command has changed to an active level.

The shift register 46e and the combination circuit 46f are the same as the shift register 46b and the combination circuit 46c shown in FIG. The numbers given to the 2-input NAND gate and the inverter of the combinational circuit 46f correspond to the value of the write latency WLTC. For example, when the write latency WLTC is set to “4”, only NAND gates marked with “4” are activated.
The combinational circuit 46f is delayed by the number of clocks corresponding to the write latency WLTC from the supply of the chip enable signal / CE (supply of the write command) when the write enable signal / WE is at a low level (= WRZ signal is at a high level). The write burst clock signal WBCLK is output the number of times corresponding to the burst length BL. That is, the shift register 46e and the combinational circuit 46f operate as an output control circuit that starts outputting the write burst clock signal WBCLK after measuring a predetermined time after the chip enable signal / CE changes to the active level. The basic operations of the shift register 46e and the combinational circuit 46f are the same as those in the first embodiment (FIG. 7).

FIG. 19 shows a method for setting the mode register in the mode setting control circuit 48 shown in FIG.
The mode register is supplied with a predetermined command CMD (CMD1, CMD2, CMD3, CMD4) and a predetermined address ADD (CODE1, CODE2, CODE3, CODE4) four times in succession, and then a predetermined code CODE5 is supplied to the address terminal. It is set by being supplied. That is, the mode register receives the code CODE5 as a setting signal for setting the operation mode. The number of clock cycles for setting the mode register is one less than that in the first embodiment.

  In this embodiment, the burst length BL is set by the lower 2 bits of the 1-byte address A7-A0 supplied as the code CODE5, the read latency RLTC is set by the next 3 bits, and the upper 3 bits. Write latency WLTC is set. The read latency RLTC can be set in eight ways from “1” to “8”. The write latency WLTC can be set in eight ways from “0” to “7”. Thus, the latency can be set independently between the read operation and the write operation. In other words, the burst control circuit 46 shown in FIG. 16 can generate burst clock signals RBCLK and WBCLK at independent timings during the read operation and the write operation. As a result, usability of a system equipped with pseudo SRAM is improved.

FIG. 20 shows a read operation in the burst mode in the pseudo SRAM of the third embodiment. Since the basic timing of the read operation is the same as that of the first embodiment (FIGS. 7 and 9), description of the same operation as that of the first embodiment is omitted. In this example, the read latency RLTC is set to “4”.
First, the clock generation circuit 46a shown in FIG. 17 is activated by the low level of the chip enable signal / CE and starts outputting the internal clock signal RCLK1 (FIG. 20 (a)). The read control signal RDZ is output by the low level of the chip enable signal / CE and the low level of the output enable signal / OE (FIG. 20B). The shift register 46b changes the count signal BCNT3 to high level in synchronization with the second clock signal CLK (FIG. 20 (c)).

The combinational circuit 46c is activated by the high level read control signal RDZ and the count signal BCNT3, and outputs the clock signal CLK as the read burst clock signal RBCLK (FIG. 20 (d)). That is, output of the read burst clock signal RBCLK is started in synchronization with the third clock signal CLK.
Thereafter, read data is sequentially output in synchronization with the read burst clock signal RBCLK in the same manner as in the first embodiment. The system equipped with the pseudo SRAM receives the first read data in synchronization with the rising edge of the fourth clock signal CLK (FIG. 20 (e)).

The burst address counter 20 shown in FIG. 16 is incremented by receiving a control signal output from the burst control circuit 46 via the timing control circuit 22 in synchronization with the output start of the read burst clock signal RBCLK. The value is output as the internal address signal IADD (FIG. 20 (f)).
Although not shown, the combinational circuit 46c is always activated when the read latency RLTC is set to “1”. Therefore, the first read burst clock signal RBCLK is output in synchronization with the zeroth clock signal CLK. The read data is output at a timing that can be received by the system in synchronization with the first clock signal CLK.

FIG. 21 shows a write operation in the burst mode in the pseudo SRAM of the third embodiment. The description of the same operation as that of the first embodiment (FIG. 10) is omitted. In this example, the write latency WLTC is set to “4”.
First, the clock generation circuit 46d shown in FIG. 18 is activated by the output of the write control signal WRZ and starts outputting the internal clock signal WCLK1 (FIG. 21A). The write control signal WRZ is output by the low level of the chip enable signal / CE and the low level of the write enable signal / WE (FIG. 21B). The shift register 46e changes the count signal BCNT4 to high level in synchronization with the third clock signal CLK (FIG. 21 (c)).

The combinational circuit 46f is activated by the high level write control signal WRZ and the count signal BCNT4, and outputs the clock signal CLK as the write burst clock signal WBCLK (FIG. 21 (d)). That is, the output of the write burst clock signal WBCLK is started in synchronization with the fourth clock signal CLK.
Also, a system equipped with a pseudo SRAM outputs first write data to the pseudo SRAM in synchronization with the falling edge of the third clock signal CLK (FIG. 21 (e)). The pseudo SRAM receives this write data in synchronization with the rising edge of the fourth clock signal and transfers it to the common data bus CDB (FIG. 21 (f)). Write data on the common data bus CDB is transferred to the data bus DB (DB0 or DB1) in synchronization with the write burst clock signal WBCLK.

The burst address counter 20 shown in FIG. 16 is counted up by receiving the control signal output from the burst control circuit 46 via the timing control circuit 22 in synchronization with the output start of the write burst clock signal WBCLK. The value is generated as the internal address signal IADD (FIG. 21 (g)). Thereafter, the sequentially supplied write data is transferred to the data bus DB in synchronization with the write burst clock signal WBCLK and written into the memory cell MC.
Although not shown, the combinational circuit 46f is always activated when the write latency WLTC is set to “0”. Therefore, the first write burst clock signal WBCLK is output in synchronization with the 0th clock signal CLK. At this time, the system equipped with the pseudo SRAM outputs the write data at a timing at which the pseudo SRAM can be received in synchronization with the 0th clock signal CLK.

  As described above, also in this embodiment, the same effect as in the first embodiment described above can be obtained. Furthermore, since the output of read data or the input of write data is started after predetermined latencies RLTC and WLTC after the chip enable signal / CE changes, a system equipped with a pseudo SRAM can easily control the pseudo SRAM. That is, the system configuration can be simplified. The pseudo SRAM starts a data input / output operation triggered by a change in the chip enable signal / CE. Therefore, the present invention can be applied to both a clock synchronous pseudo SRAM and a clock asynchronous pseudo SRAM.

The read data output start timing and write data input start timing can be set in accordance with the latencies RLTC and WLTC held in an externally settable mode register. Therefore, the latencies RLTC and WLTC can be optimally set according to the system performance.
The mode register can independently set the read latency RLTC and the write latency WLTC. For this reason, the latency RLTC and WLTC can be freely set according to the system characteristics, and the system performance can be improved.

FIG. 22 shows a fourth embodiment of the semiconductor memory of the present invention. The same elements as those in the first and third embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.
In this embodiment, instead of the command decoder 14, the burst control circuit 16, the mode setting control circuit 18 and the burst transfer register 32 of the first embodiment, a command decoder 44, a burst control circuit 52, a mode setting control circuit 54 and A burst transfer register 50 is formed. Other configurations are the same as those of the first embodiment. The command decoder 44 and the burst transfer register 50 are the same circuits as those in the second embodiment.

The burst control circuit 52 generates a read burst clock signal RBCLK according to the read control signal RDZ and the output enable signal / OE during a read operation. The burst control circuit 52 generates a write burst clock signal WBCLK according to the write control signal WRZ and the write enable signal / WE during the write operation.
The mode setting register 50 outputs a predetermined read latency signal RLTC and a write latency signal WLTC.

23 and 24 show details of the burst control circuit 52 shown in FIG. FIG. 23 shows a circuit for generating the read burst clock signal RBCLK and the wait signal WAIT during the read operation in the burst control circuit 52. FIG. 24 shows a circuit for generating the write burst clock signal WBCLK during the write operation in the burst control circuit 52.
The burst control circuit 52 shown in FIG. 23 is the same as that of the third embodiment (FIG. 17) except that the clock enable circuit 46a is supplied with the output enable signal / OE instead of the chip enable signal / CE. The shift register 46b and the combinational circuit 46c of the burst control circuit 52 operate as an output control circuit that starts outputting the read burst clock signal RBCLK after measuring a predetermined time after the output enable signal / OE changes to the active level.

  The burst control circuit 52 shown in FIG. 24 is the same as that of the third embodiment (FIG. 18) except that the clock generation circuit 46d is supplied with the write enable signal / WE instead of the chip enable signal / CE. is there. The shift register 46e and the combination circuit 46f of the burst control circuit 52 operate as an output control circuit that starts outputting the write burst clock signal WBCLK after measuring a predetermined time after the write enable signal / WE changes to the active level.

FIG. 25 shows details of the mode setting control circuit 54 shown in FIG.
The mode setting control circuit 54 has a mode register 54a and a switch circuit 54b connected to the 8-bit outputs A0-A7 of the mode register 54a. The mode register 54a is the same as the mode register of the third embodiment, and the burst length BL, read latency RLTC, and write latency WLTC can be set by the method described in FIG.
Each switch circuit 54b has a switch SW1 connected to the power supply voltage VDD, a switch SW2 connected to the ground voltage VSS, and a switch SW3 connected to one of the outputs of the mode register 54a. Any one of the switches SW1, SW2, and SW3 is turned on in the pseudo SRAM manufacturing process (wiring process).

More specifically, two photomasks used in the wiring process are manufactured in advance. One photomask is provided with a wiring pattern for conducting the switches SW3 of all the switch circuits 54b. On the other photomask, a wiring pattern is formed to conduct the switch SW1 or the switch SW2 in all the switch circuits 54b. A product in which the burst length BL and the latency RLTC, WLTC can be changed according to the value of the mode register 54a in accordance with the photomask used in the manufacturing process, and a product in which the burst length BL and the latency RLTC, WLTC are fixed to a predetermined value And are manufactured.
The mode setting control circuit 54 outputs a burst length BL and latencies RLTC and WLTC in accordance with a switch (any one of SW1, SW2 and SW3) formed on the pseudo SRAM substrate corresponding to the photomask wiring pattern. The burst control circuit 52 outputs a burst clock signal RBCLK (or WBCLK) at a timing corresponding to the burst length BL and the latencies RLTC and WLTC output from the mode setting control circuit 54. In other words, the burst control circuit 52 measures the time corresponding to the latency RLTC (or WLTC) corresponding to the voltage value of the connection destination of the conductive pattern of the switch circuit 54b, and after the measurement, the burst clock signal RBCLK (or WBCLK) Start output.

FIG. 26 shows a read operation in the burst mode in the pseudo SRAM of the fourth embodiment. In this example, the read latency RLTC is set to “2”. The read latency RLTC is the number of clocks from when the output enable signal / OE is activated until the first read data is output.
The burst control circuit 52 starts outputting the internal clock signal RCLK1 in response to the activation of the output enable signal / OE during the read operation (FIG. 26 (a)). Since the basic timing of the subsequent burst read operation is the same as that of the third embodiment (FIG. 20), description thereof is omitted.

FIG. 27 shows a write operation in the burst mode in the pseudo SRAM of the fourth embodiment. In this example, the write latency WLTC is set to “2”. The write latency WLTC is the number of clocks from when the write enable signal / WE is activated until the first write data is input.
The burst control circuit 52 starts outputting the internal clock signal WCLK1 in response to the activation of the write enable signal / WE during the write operation (FIG. 27 (a)). Since the basic timing of the subsequent burst write operation is the same as that of the third embodiment (FIG. 21), description thereof is omitted.

  As described above, also in this embodiment, the same effects as those of the first and third embodiments described above can be obtained. Furthermore, since the latency RLTC and WLTC can be set by switching the photomask, the latency RLTC and WLTC can be set according to the product specifications (such as operating frequency) of the semiconductor memory to be shipped. This is particularly effective when a pseudo SRAM manufactured using the same manufacturing process and having a sufficient operating frequency is shipped as a plurality of products corresponding to the operating frequency by switching the photomask.

FIG. 28 shows a fifth embodiment of the semiconductor memory of the present invention. The same elements as those in the first and third embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.
In this embodiment, instead of the command decoder 14, the burst control circuit 16, the mode setting control circuit 18 and the burst transfer register 32 of the first embodiment, a command decoder 44, a burst control circuit 46, a mode setting control circuit 56 and A burst transfer register 50 is formed. Other configurations are the same as those of the first embodiment. The command decoder 44, burst control circuit 46, and burst transfer register 50 are the same circuits as in the second embodiment.

FIG. 29 shows details of the mode setting control circuit 56.
The mode setting control circuit 56 includes a mode register 56a and a mode setting circuit 56b that receives 8-bit outputs A0 to A7 of the mode register 56a. The mode register 56a is the same as the mode register of the third embodiment, and the burst length BL, read latency RLTC, and write latency WLTC can be set by the method described in FIG.
Each mode setting circuit 56b has two fuse circuits 56c each programmed with 1-bit data. The fuse circuit 56c is initialized by a starter signal STTZ (power-on reset signal) that temporarily becomes a high level when the pseudo SRAM is turned on, and outputs a logical value corresponding to the program state of the fuses FS1 and FS2. When the fuse FS1 is programmed (blown state), the signal V1 changes to low level and the signal / V1 changes to high level. When the fuse FS1 is not programmed (unblown state), the signal V1 changes to high level and the signal / V1 changes to low level. Similarly, when the fuse FS2 is programmed (blown state), the signal V2 changes to a low level and the signal / V2 changes to a high level. When the fuse FS2 is not programmed (unblown state), the signal V2 changes to high level and the signal / V2 changes to low level.

In this embodiment, when manufacturing a product in which the burst length BL and the latencies RLTC and WLTC can be changed according to the value of the mode register 56a, the fuses FS1 and FS2 of all the mode setting circuits 56b are not blown in the test process. Put into a state. At this time, the NAND gate at the bottom of the figure outputs a low level, and the CMOS transmission gate is turned on. Then, the values set in the mode register 56a are output as the burst length BL and the latencies RLTC and WLTC.
In the manufacturing process, when the burst length BL and the latencies RLTC and WLTC are fixed to predetermined values, the fuse F1 or the fuse F2 is blown in all the mode setting circuits 56b. At this time, the CMOS transmission gate is turned off, and the output of the mode register 56a is masked. When the fuse F1 is blown and the fuse F2 is not blown, the ground voltage VSS is output. When the fuse F2 is blown and the fuse F1 is not blown, the power supply voltage VDD is output. That is, the mode setting circuit 56b outputs a high level or a low level according to the program state of the fuses F1 and F2. That is, a product in which the burst length BL and the latencies RLTC and WLTC are fixed to predetermined values is manufactured.

As described above, the mode setting control circuit 56 outputs the burst length BL and the latencies RLTC and WLTC to the burst control circuit 46 in accordance with the program states of the fuses FS1 and FS2. In other words, the burst control circuit 46 measures the time corresponding to the latency RLTC (or WLTC) corresponding to the program state of the fuses FS1 and FS2, and starts outputting the burst clock signal RBCLK (or WBCLK) after the measurement.
Since the burst read operation and the burst write operation are the same as those in the third embodiment, description thereof is omitted.

  As described above, also in this embodiment, the same effects as those of the first and third embodiments described above can be obtained. In addition, the RLTC and WLTC latency can be set by programming the fuses FS1 and FS2. By programming the fuses FS1 and FS2 according to the maximum operating frequency evaluated in the probe test, the ability of the manufactured pseudo SRAM is improved The predetermined time can be set accordingly. In particular, it is effective when a pseudo SRAM manufactured using the same photomask and manufacturing process is classified into a plurality of products and shipped according to the capability of the operating frequency.

In the first and second embodiments described above, the example in which the latency LTC during the burst read operation is set to “4” has been described. The present invention is not limited to this. The latency LTC may be set to an optimum value according to the clock cycle.
An example has been described in which the codes CODE5 and CODE6 for setting the burst length BL and latency LTC in the mode register are received at the address terminals. The present invention is not limited to this. For example, it may be received at a command terminal or a data terminal.
In the third to fifth embodiments described above, the example in which the read latency RLTC and the write latency WLTC are set independently has been described. The present invention is not limited to this. For example, as shown in FIG. 30, the bits A4-A2 of the mode register may be shared by the read latency RLTC and the write latency WLTC. Alternatively, the write latency WLTC may always be set to be “1” smaller than the read latency RLTC. In this case, the number of bits of the mode register can be reduced.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Supplementary note 1) a memory cell array composed of volatile memory cells having capacitors;
A refresh control circuit for generating a refresh request for refreshing the memory cells at a predetermined period;
A first burst control circuit for outputting a predetermined number of strobe signals in response to an access command for continuously burst-accessing the memory cell array;
A data input / output circuit that continuously inputs data to the memory cell array or outputs data from the memory cell array in synchronization with each of the strobe signals;
A semiconductor memory comprising: an arbitration circuit that determines which one of a refresh operation and a burst access operation is to be executed first when the refresh request and the access command compete with each other.

(Appendix 2) In the semiconductor memory described in Appendix 1,
The arbitration circuit is:
A semiconductor memory, comprising: a refresh holding unit that holds the refresh request during the burst access operation when priority is given to the burst access operation.

(Appendix 3) In the semiconductor memory described in Appendix 2,
A second burst control circuit for outputting a burst signal corresponding to an output period of the predetermined number of strobe signals;
The semiconductor memory according to claim 1, wherein the refresh holding unit that holds the refresh request outputs a refresh start signal for starting the refresh operation in response to completion of output of the burst signal.

(Appendix 4) In the semiconductor memory described in Appendix 2,
The refresh holding unit that holds the refresh request outputs a refresh start signal for starting the refresh operation without waiting for completion of data output from the data input / output circuit after the operation of the memory cell array. A semiconductor memory characterized by:

(Appendix 5) In the semiconductor memory described in Appendix 2,
A plurality of word lines respectively connected to a predetermined number of the memory cells;
In response to the access command, a full burst operation function for sequentially selecting the plurality of word lines and sequentially accessing the memory cells,
The semiconductor memory, wherein the refresh holding unit that holds the refresh request during the full burst operation outputs a refresh start signal for starting the refresh operation when the word line is switched.

(Appendix 6) In the semiconductor memory described in Appendix 2,
The data input / output circuit includes a data register for converting parallel read data from the memory cell array into serial data,
The semiconductor memory, wherein the refresh holding unit holding the refresh request outputs a refresh start signal for starting the refresh operation before the data register completes the output of serial data.

(Appendix 7) In the semiconductor memory described in Appendix 1,
The arbitration circuit is:
A semiconductor memory comprising: an access holding unit for holding the access command during the refresh operation when the refresh operation is prioritized.

(Appendix 8) In the semiconductor memory described in Appendix 1,
A semiconductor memory comprising an address counter that receives an external address supplied in response to the access command and sequentially generates an internal address continuous to the external address.
(Supplementary note 9) In the semiconductor memory according to supplementary note 8,
The data input / output circuit holds read data output from the memory cell selected by the external address and the internal address, and sequentially outputs the held read data to a common data bus in synchronization with the strobe signal. A semiconductor memory comprising a data register.

(Supplementary note 10) In the semiconductor memory according to supplementary note 9,
The semiconductor memory, wherein the memory cell array is deactivated after the read data is transferred to the data register.
(Appendix 11) In the semiconductor memory described in Appendix 8,
The data input / output circuit sequentially holds write data to the memory cell selected by the external address and the internal address in synchronization with the strobe signal, and outputs the held write data to the memory cell array A semiconductor memory comprising a register.

(Supplementary note 12) In the semiconductor memory according to supplementary note 1,
The semiconductor memory according to claim 1, wherein the burst control circuit outputs the strobe signal in synchronization with an external clock signal.
(Supplementary note 13) In the semiconductor memory according to supplementary note 1,
A chip enable terminal for receiving a chip enable signal for activating an internal circuit;
An address status terminal for receiving an address status signal indicating that the external address is valid;
The arbitration circuit detects supply of the access command when at least one of the chip enable signal and the address status signal is input.

(Supplementary note 14) In the semiconductor memory according to supplementary note 1,
A semiconductor memory comprising a wait terminal for outputting a wait signal indicating that a data input / output terminal is invalid during a period from reception of the access command to output of read data.
(Supplementary note 15) In the semiconductor memory according to supplementary note 1,
A semiconductor memory comprising an address status terminal for receiving an address status signal indicating that the external address is valid.

(Supplementary note 16) In the semiconductor memory according to supplementary note 1,
A plurality of data input / output terminals for inputting / outputting data;
A plurality of data terminal groups each configured by a predetermined number of the data input / output terminals; and
A semiconductor memory comprising a plurality of data valid terminals for receiving a data valid signal indicating that data transmitted to each of the data terminal groups is valid.

(Supplementary note 17) In the semiconductor memory according to supplementary note 16,
The semiconductor memory according to claim 1, wherein the data input / output circuit includes an output buffer corresponding to the data terminal group, which prohibits the output of read data from the memory cell array when the data valid signal is invalid.
(Supplementary note 18) In the semiconductor memory according to supplementary note 16,
A column switch connecting the memory cell and the data input / output circuit;
A column switch group corresponding to the data terminal group, each configured by a predetermined number of the column switches;
And a control circuit for turning off the column switch of the corresponding column switch group when the data valid signal is invalid.

(Supplementary note 19) In the semiconductor memory according to supplementary note 1,
A semiconductor memory comprising a burst advance terminal for temporarily stopping the progress of the burst access operation and receiving a burst advance signal for maintaining the output of read data.
(Supplementary note 20) In the semiconductor memory according to supplementary note 1,
A mode setting control circuit for receiving a signal supplied to at least one of the external input terminals as a setting signal for setting an operation mode after receiving a signal having a predetermined logical value at the external input terminal continuously a plurality of times; A semiconductor memory characterized by comprising:

(Supplementary note 21) In the semiconductor memory according to supplementary note 20,
2. The semiconductor memory according to claim 1, wherein the mode setting control circuit includes a mode register that sets a latency that is the number of clocks from the reception of the access command to the start of output of read data.
(Supplementary note 22) In the semiconductor memory according to supplementary note 20,
The semiconductor memory according to claim 1, wherein the mode setting control circuit includes a mode register for setting a burst length, which is the number of times data is continuously input or output.

(Supplementary note 23) In the semiconductor memory according to supplementary note 1,
The first burst control circuit includes:
A level detection circuit for detecting that one of the command signals supplied as the access command has changed to an active level;
A semiconductor memory, comprising: an output control circuit that starts outputting the strobe signal after measuring a predetermined time from detection by the level detection circuit.

(Supplementary Note 24) A memory cell array having memory cells;
A first burst control circuit for outputting a predetermined number of strobe signals in response to an access command for continuously burst-accessing the memory cell array;
A data input / output circuit that continuously inputs data to the memory cell array or outputs data from the memory cell array in synchronization with the strobe signal,
The first burst control circuit includes:
A level detection circuit for detecting that one of the command signals supplied as the access command has changed to an active level;
A semiconductor memory, comprising: an output control circuit that starts outputting the strobe signal after measuring a predetermined time from detection by the level detection circuit.

(Supplementary Note 25) In the semiconductor memory described in the supplementary note 24,
The first burst circuit detects a strobe signal for outputting data from the memory cell array after a predetermined time after detecting an active level of a chip enable signal which is one of the command signals during a read operation. A semiconductor memory characterized by starting output.
(Supplementary note 26) In the semiconductor memory according to supplementary note 24,
The first burst circuit detects a strobe signal for outputting data from the memory cell array after a predetermined time after detecting an active level of an output enable signal which is one of the command signals during a read operation. A semiconductor memory characterized by starting output.

(Supplementary note 27) In the semiconductor memory described in the supplementary note 24,
The first burst circuit detects a strobe signal for inputting data to the memory cell array after a predetermined time after detecting an active level of a chip enable signal which is one of the command signals during a write operation. A semiconductor memory characterized by starting output.
(Supplementary note 28) In the semiconductor memory according to supplementary note 24,
The first burst circuit detects a strobe signal for inputting data to the memory cell array after a predetermined time after detecting an active level of a write enable signal which is one of the command signals during a write operation. A semiconductor memory characterized by starting output.

(Supplementary note 29) In the semiconductor memory according to supplementary note 24,
The semiconductor memory according to claim 1, wherein the output control circuit measures the predetermined time independently during a read operation and during a write operation.
(Supplementary note 30) In the semiconductor memory according to supplementary note 24,
The semiconductor memory according to claim 1, wherein the output control circuit measures the predetermined time common to a read operation and a write operation.

(Supplementary Note 31) In the semiconductor memory described in the supplementary note 24,
An address counter that receives an external address supplied in response to the access command and sequentially generates an internal address continuous to the external address;
The semiconductor memory according to claim 1, wherein the address counter is counted up to generate the internal address in response to the start of output of the strobe signal.
(Supplementary Note 32) In the semiconductor memory described in the supplementary note 24,
A mode register capable of setting the predetermined time from the outside,
The semiconductor memory according to claim 1, wherein the first burst circuit measures the predetermined time according to a value set in the mode register.

(Supplementary note 33) In the semiconductor memory according to supplementary note 24,
A switch constituted by a conductive pattern formed on a semiconductor substrate corresponding to the pattern shape of a photomask used in a semiconductor manufacturing process,
The semiconductor memory according to claim 1, wherein the first burst circuit measures the predetermined time according to a voltage value of a connection destination of the conductive pattern.
(Supplementary Note 34) In the semiconductor memory described in the supplementary note 24,
A fuse programmed with information indicating the predetermined time,
The semiconductor memory according to claim 1, wherein the first burst circuit measures the predetermined time according to information programmed in the fuse.

In the semiconductor memory according to appendix 7, the arbitration circuit includes an access holding unit that holds an access command during the refresh operation when priority is given to the refresh operation. For this reason, it is possible to prevent the access request from being lost when the refresh operation is executed with priority over the burst access operation.
In the semiconductor memory of appendix 10, the memory cell array is deactivated after the read data is transferred to the data register. By quickly deactivating the memory cell array at the time of burst reading, the operation for the refresh request or the next access request can be started quickly. As a result, the data transfer rate can be improved.

In the semiconductor memory of appendix 12, the burst control circuit outputs the strobe signal in synchronization with the external clock signal. That is, the data transfer rate can be improved even in a clock-synchronized semiconductor memory that automatically executes refresh.
In the semiconductor memory of appendix 18, the column switch connects the memory cell and the data input / output circuit. A column switch group corresponding to the data terminal group is configured by a predetermined number of column switches. The control circuit turns off the column switch of the corresponding column switch group when the data valid signal is invalid. In the write operation period, the column switch operates at a relatively late timing. For this reason, masking of the write data can be facilitated by masking the write data with the column switch.

In the semiconductor memory of appendix 32, the first burst circuit measures a predetermined time according to the value set in the mode register.
In the semiconductor memory of appendix 33, the predetermined time is changed according to the voltage value of the connection destination of the conductive pattern formed on the semiconductor substrate corresponding to the pattern shape of the photomask used in the semiconductor manufacturing process. The predetermined time can be set according to the product specifications (operating frequency, etc.) of the semiconductor memory to be shipped. This is particularly effective when semiconductor memories manufactured using the same manufacturing process and having a sufficient operating frequency are shipped as a plurality of products corresponding to the operating frequency by switching the photomask.

In the semiconductor memory of appendix 34, the predetermined time is changed according to the fuse program. Therefore, for example, by programming the fuse according to the maximum operating frequency evaluated in the probe test, the predetermined time can be set according to the ability of the manufactured semiconductor memory. In particular, it is effective when semiconductor memories manufactured using the same photomask and manufacturing process are classified into a plurality of products and shipped according to the ability of the operating frequency.
As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

  The present invention is applicable to a semiconductor memory having a volatile memory cell having a capacitor and having an SRAM interface.

It is a block diagram which shows the 1st Embodiment of this invention. It is a block diagram which shows the detail of the arbitration circuit of FIG. FIG. 3 is a timing diagram illustrating an operation of the arbitration circuit of FIG. 2. FIG. 3 is a timing diagram illustrating another operation of the arbitration circuit of FIG. 2. FIG. 3 is a timing diagram illustrating another operation of the arbitration circuit of FIG. 2. FIG. 2 is a block diagram showing details of the burst control circuit of FIG. 1. FIG. 7 is a timing diagram showing an operation of the burst control circuit of FIG. 6. It is explanatory drawing which shows the setting method of the mode register of FIG. FIG. 6 is a timing chart showing a burst read operation in the first embodiment. FIG. 5 is a timing chart showing a burst write operation in the first embodiment. It is a timing diagram which shows the function of / ADV signal. FIG. 5 is a timing diagram showing functions of / LB and / UB signals in a burst read operation. FIG. 5 is a timing diagram showing functions of / LB and / UB signals in a burst write operation. It is a block diagram which shows the 2nd Embodiment of this invention. FIG. 10 is a timing chart showing a burst read operation in the second embodiment. It is a block diagram which shows the 1st Embodiment of this invention. It is a block diagram which shows the principal part of the burst control circuit of FIG. It is a block diagram which shows another principal part of the burst control circuit of FIG. It is explanatory drawing which shows the setting method of the mode register of FIG. FIG. 10 is a timing chart showing a burst read operation in the third embodiment. FIG. 10 is a timing diagram showing a burst write operation in the third embodiment. It is a block diagram which shows the 4th Embodiment of this invention. It is a block diagram which shows the principal part of the burst control circuit of FIG. It is a block diagram which shows another principal part of the burst control circuit of FIG. It is a block diagram which shows the principal part of the mode setting control circuit of FIG. FIG. 10 is a timing chart showing a burst read operation in the fourth embodiment. FIG. 10 is a timing chart showing a burst write operation in the fourth embodiment. It is a block diagram which shows the 5th Embodiment of this invention. It is a block diagram which shows the principal part of the mode setting control circuit of FIG. It is explanatory drawing which shows another example of a mode register.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Refresh control circuit; 12 ... Arbitration circuit; 14 ... Command decoder; 16 ... Burst control circuit; 18 ... Mode setting control circuit; 20 ... Burst address counter; 22 ... Timing control circuit; 28 ... Memory cell array; 30 ... Read / write amplifier; 32 ... Burst transfer register; 34 ... Data output control circuit; 36 ... Data input control circuit; 38 ... Timing control circuit; 40 ... Read / write amplifier; Register 44 44 Command decoder 46 Burst control circuit 48 Mode setting control circuit 50 Burst transfer register 52 Burst control circuit 54, 56 Mode setting control circuit ACSS Access activation signal ACSZ Access Signal: ACTZ: Active signal; ADD: Address Signal: / ADS ... Address status signal; / ADV ... Burst address advance signal; BCLK ... Burst clock signal; BL ... Burst length signal; BSTZ ... Burst signal; CDB ... Common data bus; / CE ... Chip enable signal; Clock signal: CMD Command signal DB DB Data address IADD Internal address signal LTC Latency signal LAT Address latch signal / LB Lower byte signal / OE Output enable signal RAEN Read amplifier enable signal RBCLK Read burst clock signal RDZ Read control signal REFENZ Refresh enable signal REFS1, REFS2 Refresh start signal REFZ Refresh request RLTC Read latency read latency signal RSTPZ Refresh stop signal / UB · · · Upper byte signal; WAEN · Write amplifier enable No.; WAIT ‥ wait signal; WBCLK ‥ write burst clock signal; / WE ‥ write enable signal; WLTC ‥ write latency, write latency signal; WRZ ‥ write control signal

Claims (10)

A memory cell array composed of a plurality of memory cells;
A refresh control circuit for generating a refresh request for refreshing the memory cells at a predetermined period;
A burst control circuit for activating a burst signal indicating that a burst access operation is being performed based on a signal instructing burst access to the memory cell array;
A data input / output circuit for continuously inputting data to the memory cell array or outputting data from the memory cell array in synchronization with a strobe signal ;
An arbitration circuit that determines which of a refresh operation and a burst access operation is to be executed first when the refresh request and an access command compete with each other;
The arbitration circuit holds the refresh request based on activation of the burst signal, and outputs the refresh request to initiate refresh based on deactivation of the burst signal.
A semiconductor memory characterized by the above. A memory cell array composed of a plurality of memory cells;
A refresh control circuit for generating a refresh request for refreshing the memory cells at a predetermined period;
A burst control circuit for activating a burst signal indicating that a burst access operation is being performed based on a signal instructing burst access to the memory cell array;
A data input / output circuit for continuously inputting data to the memory cell array or outputting data from the memory cell array in synchronization with a strobe signal ;
When the refresh request and the access command compete with each other, a determination signal is generated by determining which one of a refresh operation and a burst access operation is executed first, and the refresh signal is generated based on the burst signal and the determination signal. And an arbitration circuit that holds the request and outputs the held refresh request after the burst access operation is finished to start the refresh.
A semiconductor memory characterized by the above. The semiconductor memory according to claim 1 or 2,
The burst control circuit, to output the strobe signal in a predetermined number for burst access successively the memory cell array
A semiconductor memory characterized by the above. The semiconductor memory according to any one of claims 1 to 3,
The arbitration circuit is:
A refresh holding unit for holding the refresh request when priority is given to the burst access operation;
A semiconductor memory characterized by the above. The semiconductor memory according to any one of claims 1 to 4,
The output of the refresh request for initiating refresh is performed without waiting for completion of data output from the data input / output circuit after the operation of the memory cell array.
A semiconductor memory characterized by the above. The semiconductor memory according to any one of claims 1 to 5,
It has an address counter that receives an external address supplied in response to a signal for instructing burst access and sequentially generates an internal address continuous to the external address.
A semiconductor memory characterized by the above. The semiconductor memory according to any one of claims 1 to 6,
Output a wait signal indicating that the data input / output terminal is invalid during the period from the reception of the signal indicating burst access until the read data is output.
A semiconductor memory characterized by the above. The semiconductor memory according to any one of claims 1 to 7,
It has a mode setting circuit that reads the burst length from the mode register and outputs it to the burst control circuit.
A semiconductor memory characterized by the above. A memory cell array composed of a plurality of memory cells;
A refresh control circuit for generating a refresh request for refreshing the memory cells at a predetermined period;
A burst control circuit for activating a burst signal indicating that a burst access operation is being performed based on a signal instructing burst access to the memory cell array;
A data input / output circuit for continuously inputting data to the memory cell array or outputting data from the memory cell array in synchronization with a strobe signal ;
When the refresh request and the access command compete with each other, it is determined which one of the refresh operation and the burst access operation is executed first, and the refresh request is held based on the activation of the burst signal. Semiconductor memory that outputs the refresh request to activate refresh based on deactivation of the memory
With
The semiconductor memory outputs a wait signal indicating that no data is output from the semiconductor memory during burst access to another device.
A semiconductor memory system. The semiconductor memory system according to claim 9.
The semiconductor memory includes a mode register,
The mode register can be written from outside the semiconductor memory.
A semiconductor memory system.

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