CN113900580A

CN113900580A - Memory device, electronic device and reading method related to memory device

Info

Publication number: CN113900580A
Application number: CN202010638862.2A
Authority: CN
Inventors: 吴圣伦; 苏俊联
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2020-07-06
Filing date: 2020-07-06
Publication date: 2022-01-07
Anticipated expiration: 2040-07-06
Also published as: CN113900580B

Abstract

The invention discloses a memory device and an electronic device capable of synchronously reading a plurality of memory modules and a reading method related to the electronic device. The electronic device comprises a main control device, a first memory module and a second memory module. The main control device executes reading operation on the first memory module and the second memory module simultaneously. When the first memory module generates an update conflict during a read operation, the first memory module reports the update conflict to the host. After the synchronous data preparation period, the first memory module and the second memory module respectively transmit the first synchronous read data and the second synchronous read data to the master control device during the synchronous data read period. Wherein the synchronous data preparation period is greater than the default read delay.

Description

Memory device, electronic device and reading method related to memory device

Technical Field

The present invention relates to a memory device, an electronic device and a reading method thereof, and more particularly, to a memory device, an electronic device and a reading method thereof capable of reading a plurality of memory modules synchronously.

Background

Portable electronic devices are increasingly popular, and the demand of memory modules is increasing due to the trend of video and audio applications. And therefore the storage capacity of the memory modules is increasing. However, some electronic devices do not require the use of a memory module with a large capacity depending on the application. In addition, the large-capacity memory module occupies a large number of pins (pin number), which is a limitation in designing the embedded system.

Please refer to fig. 1, which is a schematic diagram of a memory module in an electronic device using a dynamic random access memory DRAM. The electronic device 10a includes a master device 13a and a memory module 11 a. The main control device 13a may be a controller (controller) or a Digital Signal Processor (DSP) in an embedded system, and the Memory module (DRAM)11a adopts a Dynamic Random Access Memory (DRAM) technology. The master 13a selects the memory module (DRAM)11a by using the chip select signal CS # and transmits the control signal CTL to the memory module (DRAM)11 a. According to the control signal CTL and the system clock signal SCLK, the memory address and the read data DATm are transmitted between the master control device 13a and the memory module (DRAM)11a through the 64-bit system input/output signal lines SIO [64:1 ]. The memory address includes a column address ADRr and a row address ADRc of the memory module (DRAM)11 a.

As memory technology develops, the capacity of the memory module (DRAM)11a adopting the DRAM technology may be excessively large, and the number of wirings may be excessively large. Therefore, a Memory module using a Pseudo Static Random Access Memory (PSRAM) is currently developed.

Please refer to fig. 2, which is a schematic diagram of a memory module in an electronic device using a PSRAM. The electronic device 10b includes a main control device 13b and a memory module (PSRAM)11 b. The memory module (PSRAM)11b employs a virtual static random access memory PSRAM technology. The master control device 13b selects the memory module (PSRAM)11b using the chip select signal CS #, and then transmits the control signal CTL to the memory module (PSRAM)11 b. According to the control signal CTL, the system clock signal SCLK, and the Data strobe Mask signal (DQSM), the memory address and the Read Data are transmitted between the main control device 13 and the memory module (PSRAM)11b through the 8-bit system input/output signal lines SIO [8:1 ]. For convenience of explanation, the present invention uses the same reference symbols to represent the signal lines and the signals transmitted by the signal lines. For example, the control signal CTL is transmitted using the control signal line CTL.

As can be seen from comparing fig. 1 and fig. 2, the number of the system input/output signal lines SIO in the two drawings is greatly different. In addition, the number of control signals CTL required by the master 13a in fig. 1 is larger than that required by the master 13b in fig. 2. Therefore, the main control device 13 requires fewer pins when using the memory module (PSRAM)11 b. In conjunction, the trend is for the memory module using the PSRAM technology (PSRAM)11b to be an embedded system.

With PSRAM technology, the memory module needs to be continually updated (refresh) to maintain the stored data. If the memory module receives a read command from the host device during the update, the memory module cannot immediately perform the read operation because the memory module is updating. This phenomenon, in which the memory module is updating and cannot immediately perform a read operation, is called refresh collision (refresh collision).

When the memory module (PSRAM)11b adopts the PSRAM technology, the following two situations may occur when the master device 13b performs a read operation (read operation) on the memory module (PSRAM)11b because the state of the memory module (PSRAM)11b itself is different: a read operation in general, or a read operation in update conflict. Hereinafter, waveforms of a read operation of the memory module (PSRAM)11B in a normal case (when no update conflict occurs) will be described with reference to fig. 3A, and waveforms of a read operation of the memory module (PSRAM)11B in which an update conflict occurs will be described with reference to fig. 3B.

In FIG. 3A and FIG. 3B, the chip selection signal CS #, the system clock signal SCLK, the data strobe shielding signal DQSM, and the system input/output signal line SIO [8:1] are from top to bottom, respectively. In the present invention, the horizontal axis of the waveform diagram is time.

Please refer to fig. 3A, which is a waveform diagram of a general read operation performed by the master device using the PSRAM memory module. First, the master 13b pulls down the chip select signal CS # corresponding to the memory module (PSRAM)11b from high level to low level. Then, after the memory module 11b pulls down the data strobe mask signal DQSM to a low level, the main control device 13b sequentially sends out a read command mCMDrd, a row address (row address) ADRr, and a column address (column address) ADRc to the memory module (PSRAM)11b by using the system input/output signal line SIO [8:1 ].

In the present invention, the period during which the master 13b transmits the read command mCMDrd is defined as a read command transmission period Tcmd; the period during which the master device 13b transfers the memory address is defined as an address transfer period Tadr; the period during which the master device 13b transmits the column address ADRr is defined as a column address period Tadr _ r; the period in which the master device 13b transfers the row address ADRc is defined as a row address period Tadr _ c. For convenience of illustration, the present invention uses dotted shading to represent the read instruction mCMDd; representing the column address ADRr by a horizontal shading; and, representing the row address ADRc with a vertical shading.

In the memory module (PSRAM)11b, a read Latency Count (LC) may be defined. The read latency count LC represents the time required for the memory module (PSRAM)11b to read the read data DATm from the memory array to the internal buffer after acquiring the row address (row address) from the master 13 b. The present invention assumes that the read delay count LC is three times the system clock period Tclk (LC — 3 × Tclk).

After the memory module (PSRAM)11b receives the read command mCMDrd, the column address ADRr and the row address ADRc, it needs to wait for a while to copy the read data DATm from the memory array to the internal buffer. As shown in fig. 3A, if the memory module (PSRAM)11b does not collide with an update, the period required by the memory module (PSRAM)11b to copy the read data DATm from the memory array to the internal buffer depends on a preset read delay (dftLC ═ LC × 1). The predetermined read latency (dftLC — LC × 1) is calculated after receiving the column address mADRr from the memory module (PSRAM)11b (i.e., at time t 5).

Once the preset read delay (dftLC 1) is ended (time t8), the memory module (PSRAM)11b sequentially generates two read strobe (read strobe) pulse signals mstrb1 and mstrb2 with the data strobe mask signal DQSM on the next rising edge of the system clock signal SCLK (i.e., time t 9). While the read strobe signals mstrb1, mstrb2 are asserted, the memory module 11b also transmits the read data DATm in the internal buffer to the master device 13b via the system I/O signal lines SIO [8:1 ].

Please refer to fig. 3B, which is a waveform diagram illustrating refresh conflicts occurring inside the PSRAM when the master device performs a read operation using the PSRAM memory module. Since the waveforms in fig. 3A and 3B are substantially similar, the sequence of the chip selection signal CS #, the system clock signal SCLK, the data strobe mask signal DQSM, and the system input/output signals SIO [8:1] will not be repeated here.

As can be seen from a comparison between fig. 3A and fig. 3B, in fig. 3A, the memory module (PSRAM)11B waits for a predetermined read delay (dftLC 1), and then transmits the read data DATm to the master device 13B. In fig. 3B, the memory module (PSRAM)11B has to wait for the refresh read delay rfcclc (e.g., rfcclc ═ LC × 2) before sending the read data DATm to the master device 13B. The update read latency rfcclc represents the number of read latency counts LC required for reading data after the end of an update collision when the memory module (PSRAM)11b has an update collision. For ease of explanation, the present invention assumes an updated read delay of two read delay counts (rfcLC ═ LC × 2). In practical applications, the number of the read delay counts LC included in the updated read delay rfcclc is not limited thereto.

In fig. 3A, the data strobe mask signal DQSM is raised from low to high at time t9, and is used to issue the read strobe signals m1strb1 and m1strb2 during the period from time t9 to time t 11. The memory module (PSRAM)11b can notify the master device 13b that the read data DATm is ready in the internal buffer by a change of the data strobe mask signal DQSM. Next, the memory module (PSRAM)11b transmits the read data previously stored in the internal buffer to the system I/O signal lines SIO [8:1] for access by the master 13 b. Since the read operation of the memory module (PSRAM)11b by the master 13b may be continuous, the memory module (PSRAM)11b will continue to read data from the memory array and transfer the data to the internal buffer while the memory module (PSRAM)11b transfers the read data previously stored in the internal buffer to the system I/O signal lines SIO [8:1 ].

In some applications, an electronic device may have to use multiple memory modules simultaneously using the PSRAM technology. For such an electronic device simultaneously including a plurality of PSRAM memory modules, the master control device may not be able to correctly and synchronously obtain read data from the plurality of memory modules because the memory modules themselves have different update conflict states.

Disclosure of Invention

The invention relates to a memory device capable of synchronously reading a plurality of memory modules, an electronic device and a reading method related to the electronic device. When the memory device comprises a plurality of memory modules and one of the memory modules generates an update conflict, the master control device in the electronic device can still synchronously acquire read data from the memory modules.

According to a first aspect of the present invention, a memory device electrically connected to a host device is provided. The master device performs a read operation on the first memory device during a read operation (Trd), and the memory device includes: a first memory module (PSRAM1) and a second memory module (PSRAM 2). The first memory module (PSRAM1) generates an update conflict during a read operation. The first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive a first read command (m1CMDrd) and a second read command (m2CMDrd) transmitted by the host device during a read command transmission period (Tcmd). The first memory module (PSRAM1) and the second memory module (PSRAM2) receive the first memory address (m1ADDr ) and the second memory address (m2ADDr ) respectively during the address transfer period (Tadr). The read command transfer period (Tcmd) is earlier than the address transfer period (Tadr). After the synchronous data preparing period (Tsdatpr), the first memory module (PSRAM1) and the second memory module (PSRAM2) transmit the first synchronous read data (DATm1) and the second synchronous read data (DATm2) to the host device simultaneously during the synchronous data reading period (Tdar _ sync), wherein the synchronous data preparing period (Tsdatpr) is greater than a predetermined read latency (dftLC 1).

According to a second aspect of the present invention, an electronic device is provided. The electronic device includes: the memory device and a master device. The memory device includes: a first memory module (PSRAM1) and a second memory module (PSRAM 2). The first memory module (PSRAM1) generates an update conflict during a read operation. The first memory module (PSRAM1) and the second memory module (PSRAM2) respectively receive a first read command (m1CMDrd) and a second read command (m2CMDrd) transmitted by the host device during a read command transmission period (Tcmd). The first memory module (PSRAM1) and the second memory module (PSRAM2) receive the first memory address (m1ADDr ) and the second memory address (m2ADDr, m1 ADDr) respectively during the address transfer period (Tadr). The read command transfer period (Tcmd) is earlier than the address transfer period (Tadr). After the synchronous data preparing period (Tsdatpr), the first memory module (PSRAM1) and the second memory module (PSRAM2) transmit the first synchronous read data (DATm1) and the second synchronous read data (DATm2) to the host device simultaneously during the synchronous data reading period (Tdat _ sync), wherein the synchronous data preparing period (Tsdatpr) is greater than a predetermined read latency (dftLC 1).

According to a third aspect of the present invention, a reading method applied to an electronic device is provided. The electronic device comprises a master control device, a first memory module (PSRAM1) and a second memory module (PSRAM 2). The master device performs a read operation on the first memory module (PSRAM1) and the second memory module (PSRAM2) during the read operation (Trd). The first memory module (PSRAM1) generates an update conflict during a read operation, and the read method includes the following steps. First, the first memory module (PSRAM1) and the second memory module (PSRAM2) receive a first read command (m1CMDrd) and a second read command (m2CMDrd) transmitted by the host device during a read command transmission period, respectively. Next, the first memory module (PSRAM1) and the second memory module (PSRAM2) receive the first memory address (m1ADRr, ADRc) and the second memory address (m2ADRr, m2ADRc) respectively during the address transfer period (Tadr). The read command transfer period (Tcmd) is earlier than the address transfer period (Tadr). After the synchronous data preparing period (Tsdatpr), the first memory module (PSRAM1) and the second memory module (PSRAM2) transmit the first synchronous read data (DATm1) and the second synchronous read data (DATm2) to the host device simultaneously during the synchronous data reading period (Tdat _ sync), wherein the synchronous data preparing period (Tsdatpr) is greater than a predetermined read latency (dftLC 1).

In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:

drawings

FIG. 1 is a diagram of a memory module in an electronic device using DRAM.

FIG. 2 is a diagram of a memory module in an electronic device using a PSRAM.

FIG. 3A is a waveform diagram of a general read operation performed by the master device using the PSRAM memory module.

FIG. 3B is a waveform diagram illustrating refresh conflicts occurring inside the memory module when the master device performs a read operation using the PSRAM memory module.

FIG. 4 is a schematic diagram of an electronic device including two memory modules using a PSRAM.

FIG. 5 is a schematic diagram of the master device performing a read operation on the

PSRAMs

1 and 2 in a default data synchronization manner.

FIG. 6 is a flowchart illustrating a synchronous read operation performed by the host device to the

PSRAMs

1 and 2 of the electronic device according to an embodiment of the present invention.

FIG. 7A is a flow chart illustrating the memory module PSRAM1 notifying the host device in an immediate reporting mode (mode A) and performing a synchronous read operation when a conflict occurs in the update according to the present invention.

FIG. 7B is a flowchart illustrating the memory module PSRAM1 notifying the host device in a delayed reporting mode (mode B) and performing a synchronous read operation when a conflict occurs in updating according to the present invention.

FIG. 8A is a waveform diagram illustrating an embodiment of a synchronous read operation between the memory module PSRAM1 and a host using the DQSM mask signal in conjunction with a mode A according to the present invention.

FIG. 8B is a waveform diagram illustrating an embodiment of a synchronous read operation between the memory module PSRAM1 and a host using the DQSM mask signal in conjunction with a delayed-reward mode (mode B) according to the present invention.

FIG. 9A is a schematic diagram of a memory bank busy signal line BRBB driven by the host device and disposed between the memory modules PSRAM1, PSRAM2, and the host device.

FIG. 9B is a schematic diagram of a memory bank busy signal line BRBB driven by the memory module PSRAM1 and disposed between the memory modules PSRAM1, PSRAM2 and the host.

FIG. 10 is a waveform diagram illustrating an embodiment of a synchronous read operation between the memory modules PSRAM1, PSRAM2 and a host using a bank busy signal line BRBB in conjunction with a mode A.

FIG. 11 is a waveform diagram illustrating another embodiment of a synchronous read operation between the memory modules PSRAM1, PSRAM2 and a master device in a mode A mode according to the present invention.

Fig. 12A is a schematic diagram of the memory modules PSRAM1, PSRAM2 and the host device using the chip select signal CS # as a communication interface for update conflicts, and the chip select signal CS # is driven by the host device.

Fig. 12B is a schematic diagram of the memory modules PSRAM1, PSRAM2 and the host device using the chip select signal CS # as a communication interface for update conflicts, and the chip select signal CS # is driven by the memory module PSRAM 1.

Fig. 13 is a waveform diagram of an embodiment in which the memory modules PSRAM1, PSRAM2 and the host utilize the chip select signal CS # as a communication interface for update conflicts, and the memory module PSRAM1 performs a synchronous read operation after notifying the host according to the immediate reporting mode (mode a).

Fig. 14 is a waveform diagram of an embodiment of performing a synchronous read operation between the memory modules PSRAM1, PSRAM2 and the host according to the immediate reporting mode (mode a) by using the chip select signal CS # and the system clock signal SCLK.

FIG. 15 is a waveform diagram of an embodiment in which clock ignore signals ICK1 and ICK2 are provided between the host and memory blocks PSRAM1 and PSRAM2, and a synchronous read operation is performed in the event of a refresh conflict in memory block PSRAM 1.

Fig. 16 is a schematic diagram illustrating that the master device stops generating the system clock signal SCLK to enable the memory modules PSRAM1 and PSRAM2 to perform synchronous read operations after the master device knows that the memory module PSRAM1 has a conflict of update.

FIG. 17 is a schematic diagram of the main control device issuing a repeat read command to synchronize the memory modules PSRAM1 and PSRAM2 to perform a read operation.

Fig. 18 is a waveform diagram of an embodiment of how to perform a synchronous read operation after determining that the memory module PSRAM1 has an update collision according to the time difference between the pilot pulse signals m1pre and m2pre by using the chip select signal CS # and the system clock signal SCLK between the memory modules PSRAM1 and PSRAM2 and the main control device.

[ notation ] to show

11a, DRAM, 11b, 21, 22, PSRAM1, PSRAM2, 51, 52, 41, 42: memory module

13a, 13b, 23, 53, 43: master control device

CS #: chip selection signal (wire)

SCLK: system frequency signal (line)

SIO [64:1], SIO [8:1], SIO [16:9 ]: system input/output signal line

DQSM, DQSM [2:1], DQSM [1], DQSM [2 ]: data flash control shielding signal (wire)

CTL: control signals (lines)

10a, 10b, 20, 50, 40: electronic device

t 1-t 21: time point

Trd: during read operation

Tcs: during chip select period

Tset: set period

LC: read latency count

Tclk, Tclk 1-Tclk 10: system frequency period

Tend: end period

Tadr _ r: during column address

Tadr _ c: during row address

mstrb1, mstrb2, m1strb1, m1strb2, m2strb1, m2strb2, m2strb1 ', m2strb 2': reading strobe signals

mCMrd: read instruction

ADRr, m1ADRr, m2 ADRr: column address

ADRc, m1ADRc, m2 ADRc: row address

DATm: synchronous reading data

Tcmd: during read command transfer

Tadr: during address transfer

25: memory device

Tsdatpr: synchronous data preparation period

Tdat _ sync: during synchronous data read

DATm1, DATm 2: synchronous reading data

m1CMDrd, m2 CMDrd: read instruction

Trdnm: during normal read

S51, S53, S55, S57, S59, S301a, S302a, S303a, S305a, S307a, S101a, S103a, S105a, S107a, S201a, S203a, S301b, S303b, S305b, S307b, S309b, S101b, S103b, S105b, S107b, S201b, S203 b: step (ii) of

Trdrf: update conflict read period

Trfrp: update conflict notification period

Taddwt: extra waiting period

drpDAtm 2: discarding data

Tdrp 2: during data discard

m1CMDrd _ sp, m2CMDrd _ sp: special read instruction

m2 CMDext: extended read instruction

Tcmdext: extending read instruction time

501, 511, 521, 401, 421, 411: bidirectional interface circuit

501a, 521a, 511a, 401a, 421a, 411 a: output inverter

501b, 521b, 511b, 401b, 421b, 411 b: input reverser

BRBBh, BRBBm1, BRBBm 2: memory bank busy signal (wire)

50a, 40 a: pull-up resistor

Vcc: supply voltage

Tstp: suspend read notification period

And (3) Tick: during frequency neglect

ICK1, ICK 2: frequency neglecting signal

m1CMDrtry, m2 CMDrtry: repeat read instruction

Tcmd _ rtry: during repeat read instruction

T2 rd: during repeated reading

Tint: chip select pitch

mlpre, m2 pre: pilot pulse signal

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

FIG. 4 is a schematic diagram of an electronic device including two PSRAM memory modules. The electronic device 20 includes a master device 23 and a memory device 25, and the memory device 25 includes a memory module (PSRAM1)21, (PSRAM2) 22.

The system input/output signal lines SIO [16:1] of the master control device 23 comprise 16 bits, and 8 system input/output signal lines SIO [8:1] of the 16 bits are connected with the memory module (PSRAM1) 21; the other 8 system I/O signal lines SIO [16:9] are connected to the memory module (PSRAM2) 22. The main control device 23 has two data strobe shielding signal lines DQSM [2:1], wherein the data strobe shielding signal line DQSM [1] is connected with the memory module (PSRAM1)21, and the data strobe shielding signal line DQSM [2] is connected with the memory module (PSRAM2) 22.

The master control device 23 selects the memory module (PSRAM1)21 and (PSRAM2)22 by using the chip select signal CS #. According to the system clock signal SCLK, the master control device 23 transmits the memory addresses corresponding to the memory modules (PSRAM1)21 and (PSRAM2)22 to the memory modules (PSRAM1)21 and (PSRAM2)22 through the system input/output signal lines SIO [8:1] and SIO [16:9], respectively, and the memory modules (PSRAM1)21 and (PSRAM2)22 transmit the read data DATm1 and DATm2 to the master control device 23 through the system input/output signal lines SIO [8:1] and SIO [16:9], respectively. The memory addresses of the memory module (PSRAM1)21 include a column address m1ADRr and a row address m1ADRc, and the memory addresses of the memory module (PSRAM2)22 include a column address m2ADRr and a row address m2 ADRc.

Referring to fig. 5, the main control device reads the memory modules PSRAM1 and PSRAM2 in a default data synchronization manner. The waveforms of FIG. 5 are from top to bottom, respectively, the chip select signal CS # and the system clock signal SCLK transmitted to the memory module (PSRAM1)21 and (PSRAM2)22, the data strobe mask signal DQSM [1] and the system input/output signal SIO [8:1] transmitted to the memory module (PSRAM1)21, and the data strobe mask signal DQSM [2] and the system input/output signal SIO [16:9] transmitted to the memory module (PSRAM2) 22. The data strobe mask signals DQSM [1], DQSM [2] may be in a floating state when not being driven. Alternatively, the undriven data strobe mask signals DQSM [1], DQSM [2] may be maintained at a high level by a pull-up resistor, or the undriven data strobe mask signals DQSM [1], DQSM [2] may be maintained at a low level by a pull-down resistor. The present invention assumes that the undriven data strobe mask signals DQSM [1], DQSM [2] remain low.

For simplicity of illustration, in the waveform diagrams below, several time parameters are defined. These time parameters include: a read operation period Trd, a chip select period Tcs, a set period Tset, a read command transfer period Tcmd, an address transfer period Tadr, a synchronous data preparation period Tsdatpr, and a synchronous data read period Tdat _ sync. Next, the definition of these time parameters is briefly described.

The read operation period Trd is the time taken for the master 23 to perform a read operation on the memory module (PSRAM1)21 and the (PSRAM2) 22. The chip select period Tcs is a period during which the master 23 pulls down the chip select signal CS # when performing a read operation on the memory modules (PSRAM1)21 and (PSRAM2) 22. The set period Tset is the time difference between when the master control device 23 pulls down the chip select signal CS # and before the master control device 23 starts to transmit the read commands m1 CMDre and m2 CMDre. The read command transfer period Tcmd is a time required for the master 23 to transfer the read commands m1CMDrd and m2CMDre to the memory modules (PSRAM1)21 and (PSRAM2) 22.

The address transfer period Tadr is a time required for the master 23 to transfer the memory address (including the column address m1ADRr and the row address m1ADRc) corresponding to the memory module (PSRAM1)21 to the memory module (PSRAM1)21 and to transfer the memory address (including the column address m2ADRr and the row address m2ADRc) corresponding to the memory module (PSRAM2)22 to the memory module (PSRAM2)22 in synchronization. The address transfer period Tadr further includes a column address period Tadr _ r and a row address period Tadr _ c. During the column address period Tadr _ r, the master 23 transfers the column address m1ADRr corresponding to the memory module (PSRAM1)21 to the memory module (PSRAM1)21, and synchronously transfers the column address m2ADRr corresponding to the memory module (PSRAM2)22 to the memory module (PSRAM2) 22. During the row address period Tadr _ c, the master 23 transfers the row address m1ADRc corresponding to the memory module (PSRAM1)21 to the memory module (PSRAM1)21, and synchronously transfers the row address m2ADRc corresponding to the memory module (PSRAM2)22 to the memory module (PSRAM2) 22.

In addition, the period Tsdatpr is a period of time after the master 23 transmits the memory address to the memory module (PSRAM1)21 and (PSRAM2)22 and before the synchronous data read period Tdat _ sync starts. The length of the Tsdatpr period may vary significantly from embodiment to embodiment. The synchronous data read period Tdat _ sync is a period in which the memory module (PSRAM1)21 transmits synchronous read data DATm1 from the internal buffer to the master 23 via the system input/output signal lines SIO [8:1], and the memory module (PSRAM2)22 transmits synchronous read data DATm2 from the internal buffer to the master via the system input/output signal lines SIO [16:9 ]. The end period Tend is a time difference between the end point of the chip select period Tcs and the end point of the read operation period Trd.

In FIG. 5, the time t1 to the time t11 are the read operation period Trd; the time t1 to the time t10 are chip selection periods Tcs; the set period Tset is set from time t1 to time t 2; time t2 to time t3 are the read command transfer period Tcmd; the time t4 to the time t7 are address transfer periods Tadr; the time t7 to the time t9 are the synchronization data preparation period Tsdatpr; time t9 to time t11 are the synchronous data reading period Tdat _ sync; the end period Tend is from time t10 to time t 11. Wherein the synchronous data read period Tdat _ sync is less than 1 read delay count LC. In the default data synchronization mode, the memory modules (PSRAM1)21 and (PSRAM2)22 only need to spend the time period from t5 to t9 to start transferring data from the internal memory to the system I/O signal lines SIO [16:1 ]. Therefore, the period from the time point t5 to the time point t9 can be defined as the normal reading period Trdnm.

Since the memory modules (PSRAM1)21 and (PSRAM2)22 do not frequently have update conflicts, the memory modules (PSRAM1)21 and (PSRAM2)22 usually perform normal read operations as shown in fig. 5. However, in the partial case, a situation in which one of the memory modules (PSRAM1)21 and (PSRAM2)22 may have an update conflict occurs, resulting in a situation in which the master 23 cannot correctly read the data stored in the memory module (PSRAM1)21 and (PSRAM2)22 due to inconsistency in the reading speed.

Therefore, the present invention proposes a method for flexibly responding to the occurrence of the update conflict in the memory module (PSRAM1)21 and (PSRAM2)22 and dynamically adjusting the reading of the data in the memory module (PSRAM1)21 and (PSRAM2)22 by 1 read latency count LC or 2 read latency counts LC. For convenience of explanation, the following assumes a case where an update conflict occurs inside the memory module (PSRAM1)21, and a case where the memory module (PSRAM2)22 can perform a normal read operation.

When no update conflict occurs in all the memory modules (PSRAM1)21, (PSRAM2)22, data is read by 1 read latency count LC. On the contrary, if any memory module (for example, the memory module (PSRAM1)21) has a conflict in updating, the master 23 can still synchronously read data from the memory module (PSRAM1)21 and (PSRAM2)22 by the reporting and notifying mechanism. The present invention provides various embodiments, the basic flow of which is shown in fig. 6.

Please refer to fig. 6, which is a flowchart illustrating a synchronous read operation performed by the master device on the PSRAMs 1 and the PSRAM2 in the electronic device according to an embodiment of the present invention. First, the host 23 pulls down the level of the chip select signal CS # and sends a read command to the memory module (PSRAM1)21 and (PSRAM2)22 (step S51). Next, it is determined whether any of the memory modules (PSRAM1)21 and (PSRAM2)22 generates an update conflict (step S53). The manner of step S53 may be determined by the detection of the master 23 or reported back by the memory module with conflicting updates (PSRAM1) 21. With regard to the manner of determination in step S53, different embodiments will be described later.

If the determination result in the step S53 is negative, it represents that all the memory modules (PSRAM1)21 and (PSRAM2)22 can complete the read operation in the normal data read manner as shown in fig. 5. Therefore, the memory module (PSRAM1)21 and (PSRAM2)22 prepare read data in the default data synchronization manner (tsdappr < LC) during the synchronization data preparation period tsdappr (step S55), and then transmit the synchronization read data DATm1 and DATm2 to the master device 23 during the synchronization data read period Tdat _ sync (step S59).

On the other hand, the affirmative decision at step S53 represents that there are one or more memory modules (PSRAM1)21 that have generated an update conflict. At this time, the one or more memory modules (PSRAM1)21 that generate the update conflict cannot complete data extraction within the preset read latency (dftLC ═ LC × 1). Since the memory module (PSRAM1)21 that generates the update conflict takes a long read period, the read data can be copied from the memory array to the internal buffer. Therefore, the memory module (PSRAM2)22 in which no update conflict occurs must defer its read operation speed to match the read speed of the memory module (PSRAM1) 21. Therefore, the master 23 needs to notify the memory module (PSRAM2)22 in which no update conflict occurs that the data is to be prepared for reading in a special data synchronization manner. When data is read in the special data synchronization mode, the memory modules (PSRAM1)21 and (PSRAM2)22 both have to wait for a long synchronization data preparation period Tsdatpr (Tsdatpr > LC) (step S57), and then transmit the synchronization read data DATm1 and DATm2 to the host 23 during the synchronization data read period Tdat _ sync.

According to the present invention, the master device 23 can automatically sense the occurrence of the update conflict of the memory module (PSRAM1) 21. Alternatively, when the memory module (PSRAM1)21 has an update conflict, it may actively report this back to the master 23. The memory module (PSRAM1)21 can notify the master 23 of the conflicting updates through two reporting modes, namely, an immediate reporting mode (mode a) and a delayed reporting mode (mode B). The immediate reporting mode (mode a) is to notify the master 23 that an internal refresh collision occurs in the memory module (PSRAM1)21 immediately after the chip select signal CS # is pulled low when the memory module (PSRAM1)21 has an internal refresh collision. The delayed report back mode (mode B) is a situation where the memory module (PSRAM1)21 notifies the master 23 that an internal update conflict occurs in the memory module (PSRAM1)21 after the memory module (PSRAM1)21 receives the column address m1ADRr from the master 23 when the internal update conflict occurs in the memory module (PSRAM1) 21.

Next, a read process when the memory module (PSRAM1)21 notifies the host 23 of the conflict situation of update occurred inside it in the immediate report mode (mode A) is described with reference to FIG. 7A; and, the read flow when the memory module (PSRAM1)21 notifies the master 23 of the conflict situation of the update occurred therein in the delayed report mode (mode B) is illustrated in fig. 7B. In fig. 7A and 7B, the sequence of the flow is from top to bottom, and the flows performed by the master control device 23, the memory module (PSRAM1)21, and the memory module (PSRAM2)22 are from left to right. In fig. 7A and 7B, the arrow direction represents the transmission direction of the signal, and the dashed arrow direction represents the direction that can be selectively performed according to different embodiments.

Referring to FIG. 7A, a flow chart of the memory module PSRAM1 notifying the host device in a mode A (mode A) for synchronous read operation when a refresh conflict occurs according to the present invention is shown. First, the master 23 pulls down the chip select signal CS # corresponding to the memory modules (PSRAM1)21 and (PSRAM2)22 (S301 a). Next, the memory module (PSRAM1)21 confirms that the update conflict is generated (step S101 a). The memory module (PSRAM1)21 then notifies the master 23 of the situation where the update conflict is internally generated (step S103 a). The details of how the memory module (PSRAM1)21 informs the master device 23 of the update conflict generated therein may vary from one embodiment to another, as will be further described below.

Thereafter, the master control device 23 transmits the read commands m1CMDrd, m2CMDrd to the memory module (PSRAM1)21, (PSRAM2)22 (step S302a), and notifies the memory module (PSRAM1)21, (PSRAM2)22 that the read command should be performed in a special data synchronization manner (step S303 a). Depending on the embodiment, the steps S302a and S303a may be performed together, or the steps S302a and S303a may be performed separately.

The manner by which the master 23 notifies the memory module (PSRAM1)21 and (PSRAM2)22 that the data needs to be read in a special data synchronization manner may vary from one embodiment to another, and will be further described below. Please note that, although the step S303a should be performed after the step S103a is completed. However, step S303a is not limited to being performed immediately after step S103a is completed. For example, the step S303a may be executed after the step S307a is finished.

Then, the master device 23 transfers the column addresses m1ADRr and m2ADRr and the row addresses m1ADRc and m2ADRc of the memory modules (PSRAM1)21 and (PSRAM2)22 in sequence by using the system input/output signals SIO [16:1] (steps S305a and S307 a). Wherein the system I/O signals SIO [8:1] are used to convey the column address m1ADRr and row address m1ADRc corresponding to the memory module (PSRAM1) 21; the system input output signals SIO [16:9] are used to convey the column address m2ADRr and row address m2ADRc corresponding to the memory module (PSRAM2) 22.

After the memory module (PSRAM1)21 waits for the update conflict to complete (step S105a), it transmits the synchronous read data DATm1 to the host 21 using the system I/O signals SIO [8:1] (step S107 a). While the memory module (PSRAM1)21 is transferring the read data DATm1, the memory module (PSRAM2)22 waits for the synchronous data preparation period Tsdatpr to end (step S201a), and then transfers the synchronous read data DATm2 to the master control apparatus 23 by using the system input/output signals SIO [16:9] (step S203 a).

Referring to FIG. 7B, a flow chart of the memory module PSRAM1 notifying the host device in a delayed reporting mode (mode B) and performing a synchronous read operation when a conflict occurs in updating according to the present invention is shown. First, the master 23 pulls down the chip select signal CS # of the memory modules (PSRAM1)21 and (PSRAM2)22 (S301 b). Next, the master 23 issues read commands m1CMDrd, m2CMDrd and column addresses m1ADRr, m2ADRr to the memory module (PSRAM1)21, (PSRAM2)22 (steps S303b, S305 b).

After the memory module (PSRAM1)21 confirms that the update conflict is generated (step S101b), the memory module (PSRAM1)21 notifies the master 23 of the internally generated update conflict (step S103 b). At the same time, the master device 23 transmits the row addresses m1ADRc, m2ADRc to the memory module (PSRAM1)21 and (PSRAM2)22 via the system i/o signal lines SIO [16:1] (step S307 b). Thereafter, the master 23 notifies the memory modules (PSRAM1)21 and (PSRAM2)22 that they need to be read in the special data synchronization manner (step S309 a).

After the memory module (PSRAM1)21 waits for the update conflict to end (step S105b), the synchronous read data DATm1 of the internal buffer is transmitted to the master device 21 using the system I/O signals SIO [8:1] (step S107 b). On the other hand, after the memory module (PSRAM2)22 waits for the synchronous data preparation period Tsdatpr to end (step S201b), the synchronous read data DATm2 of the internal buffer is transmitted to the master device 21 by the system input/output signals SIO [16:9] (step S203 b).

Please refer to fig. 7A and fig. 7B. It can be seen that the steps required in the two flowcharts are substantially similar, and the main difference between the two flowcharts is that the memory module (PSRAM1)21 notifies the master control device 23 of the update conflict (step S103a in fig. 7A, step S103B in fig. 7B), and the time at which the master control device 23 notifies the memory module (PSRAM1)21 and (PSRAM2)22 that the read operation needs to be performed in a special data synchronization manner (step S303a in fig. 7A, step S309B in fig. 7B) is different. In the immediate reward mode (mode a) (fig. 7A), the memory module (PSRAM1)21 notifies the master 23 that an update conflict has occurred before the master 23 transmits the read commands m1CMDrd, m2CMDrd and the column addresses m1ADRr, m2 ADRr. In the delayed reward mode (mode B) (FIG. 7B), the memory module (PSRAM1)21 notifies the master 23 of a conflict between updates after the master 23 transmits the read commands m1CMDrd, m2CMDrd and the column addresses m1ADRr, m2 ADRr.

The memory modules can be divided into single memory banks (single bank) and multi-bank (multi-bank). The memory module of the single memory bank can know whether the internal memory module generates update conflict at the moment when the chip selection signal CS # is pulled down. On the other hand, the memory module of the multi-bank must wait for the column addresses m1ADRr and m2ADRr to be received before determining whether the update conflict occurs. Therefore, the immediate return Mode (Mode A) can be applied to the memory module with a single bank, and the delayed return Mode (Mode B) can be applied to the memory modules with a single bank and multiple banks. The following embodiments will describe the way in which the memory module (PSRAM1)21 reports the update conflict using the immediate reporting Mode (Mode a) and the delayed reporting Mode (Mode B), respectively.

According to the embodiment of the present invention, when the memory module (PSRAM1)21 reports the conflict situation to the host 23, the reporting time may vary according to the embodiment, and the media and means for the memory module (PSRAM1)21 to notify the host 23 may also be different. For example, the memory module (PSRAM1)21 may notify the master device 23 using different signal lines, and various combinations of control waveforms to the signal lines.

Next, the present invention will explain corresponding waveform diagrams of embodiments that can be adopted based on the reading method contemplated by the present invention. First, fig. 8A and 8B illustrate the conventional data strobe mask signal DQSM as the transmission medium, respectively, in the method of using the immediate reporting mode (mode a) and the delayed reporting mode (mode B). Related embodiments using different signal lines as transmission media will be provided later.

Please refer to fig. 8A, which is a waveform diagram illustrating an embodiment of a synchronous read operation between a memory module and a host device using a data strobe mask signal DQSM in conjunction with a mode a according to the present invention. In the figure, the time t1 to the time t15 are the read operation period Trd; the time t1 to the time t14 are chip selection periods Tcs; the set period Tset is set from time t1 to time t 3; time t3 to time t4 are the read command transfer period Tcmd; the time t4 to the time t8 are address transfer periods Tadr; the time t8 to the time t13 are the synchronization data preparation period Tsdatpr; time t13 to time t15 are the synchronous data reading period Tdat _ sync; the end period Tend is from time t14 to time t 15.

After the master control device 23 pulls the chip select signal CS # low at time t1, the memory module (PSRAM1)21 starts at time t2, and notifies the master control device 23 that an update collision occurs therein by pulling the level of the data strobe mask signal DQSM [1] high. The memory module (PSRAM1)21 maintains the data strobe mask signal DQSM [1] at a high level during time t2 to time t7, and starts to pull the data strobe mask signal DQSM [1] low at time t 7. The period from the time point t2 to the time point t7 may be defined as an update conflict notification period Trfrp during which the memory module (PSRAM1)21 having an update conflict will notify the master 23 of the update conflict.

On the other hand, the memory module (PSRAM2)22 maintains the data strobe mask signal DQSM [2] at a low level until time t 10. At time t2, the master control device 23 has already learned the states of the memory modules (PSRAM1)21 and (PSRAM2)22 through the high-level data strobe mask signal DQSM [1] and the low-level data strobe mask signal DQSM [2], respectively. The high level data strobe mask signal DQSM [1] indicates that the memory module PSRAM1 has an update conflict, and the low level data strobe mask signal DQSM [2] indicates that the memory module (PSRAM2)22 has no update conflict.

Then, during the period from time t3 to time t4 (the read command transmission period Tcmd), the master control device 23 issues the special read command m1CMDrd _ sp to the memory module (PSRAM1)21 by using the system input/output signals SIO [8:1], and issues the special read command m2CMDrd _ sp to the memory module (PSRAM2)22 by using the system input/output signals SIO [16:9 ]. Once the memory module (PSRAM2)22 receives the special read command m2CMDrd _ sp, it knows that the read operation should be slowed. Here, the special read instructions m1CMDrd _ sp, m2CMDrd _ sp are represented by dotted shading with thick outlines. Accordingly, at time t4, the memory module (PSRAM2)22 already knows that it should not proceed at the speed of the normal read operation through the special read command m2CMDrd _ sp issued by the host 23, and needs to additionally wait for the memory module (PSRAM1)21 to complete its refresh conflict.

As described earlier, the memory module (PSRAM1)21, (PSRAM2)22 counts the read delay count from the receipt of the column addresses m1ADRr, m2 ADRr. Therefore, as can be seen from fig. 8A, the memory modules (PSRAM1)21 and (PSRAM2)22 each count the read delay count from time t 5. The memory module (PSRAM1)21 takes two read latency counts (LC × 2) until time t12 to retrieve read data from the internal memory array to the internal buffer, while the memory module (PSRAM2)22 only needs one read latency count (LC × 1) and begins at time t9 to retrieve read data from the internal memory array to the internal buffer. Next, how the memory modules (PSRAM1)21, (PSRAM2)22 read data DATm1, DATm2, respectively, in synchronization with when they are transferred from the internal buffer will be described.

The conflict of the updates of the memory module (PSRAM1)21 ends at the time point t12, and generates the read strobe signals m1strb1 and m1strb2 with the data strobe mask signal DQSM [1] sequentially at the rising edge of the next system clock signal SCLK (i.e., at the time point t 13). The time t5 to the time t13 are defined as the update collision read period Trdrf. The refresh collision read period Trdrf represents the read delay count (LC × 2) required for the memory module to wait for the completion of the refresh, plus the period required for waiting for the rising edge of the next system clock signal SCLK. That is, Trdrf ═ LC × 2+ (time t12 to time t 13). In fig. 8A, the memory module (PSRAM1)21 starts transmitting synchronous read data DATm1 from time t 13.

Since the memory module (PSRAM2)22 can prepare the internal buffer for reading data when one read latency count is over (i.e., time t9), and transmit the read strobe signals m2strb1 ', m2strb 2' to the master device 23 by using the data strobe mask signal DQSM [2] at the next rising edge of the system clock signal SCLK (i.e., time t 10). Therefore, the memory module (PSRAM2)22 starts transferring read data from the internal buffer to the system input/output signal SIO [16:9] at time t 10. Since the read data transmitted by the memory module (PSRAM2)22 from time t10 to time t11 is not used by the master control device 23, the read data transmitted by the memory module (PSRAM2)22 from time t10 to time t11 can be referred to as discarded data drpDATm2, and the period of time during which the memory module (PSRAM2)22 transmits the discarded data drpDATm2 can be defined as a data discard period Tdrp 2.

Thereafter, the memory module (PSRAM2)22 remains idle for a period of time (time t11 to time t13), and then generates and transmits the read strobe signals m2strb1 and m2strb2 with the data strobe mask signal DQSM [2] from time t 13. In addition, the memory module (PSRAM2)22 will again transfer the read data from the internal buffer to the system input/output signal SIO [16:9] from the time t 13. According to the idea of the present invention, the read data transferred from the time point t13 by the memory module (PSRAM2)22 is synchronized with the time point of the read data transferred from the time point t13 by the memory module (PSRAM1)21, and therefore, the read data transferred from the time point t13 by the memory module (PSRAM1)21 and (PSRAM2)22 are referred to as synchronous read data DATm1 and DATm 2.

According to the idea of the present invention, the master device 23 does not use the discarded data drpDATm2 transmitted by the memory module (PSRAM2)22 from time t10 to time t11, but uses the synchronous read data DATm2 transmitted by the memory module (PSRAM2)22 from time t13 to time t 15. Therefore, the period from time t10 to t11 is defined as a data discard period Tdrp 2. The contents of the discarded data drpDATm2 transferred after the strobe signals m2strbl ', m2strb 2' are read by the internal buffer of the memory module (PSRAM2)22 using the system input/output signal SIO [16:9], and the contents of the synchronized read data DATm2 transferred after the strobe signals m2strb1, m2strb2 are read are identical.

Even if the memory module (PSRAM2)22 transmits the read data from the time point t10 to the time point t11, the read data needs to be retransmitted from the time point t 13. Therefore, the time t9 to the time t13 correspond to a period of time required for the memory module (PSRAM2)22 to wait for the update conflict of the memory module (PSRAM1)21 to end. In the period from the time point t9 to the time point t13, the memory module (PSRAM2)22 (in which no update conflict occurs) is not the period required for executing the read operation itself, but the period for waiting for the read operation is suspended in response to the end of the update conflict of the memory module (PSRAM1)21 (in which the update conflict actually occurs). Therefore, the time t9 to the time t13 are defined as the extra waiting period taddwt (additional waiting duration) of the memory module (PSRAM2)22 (in which no update conflict occurs).

As shown in fig. 8A, the memory module (PSRAM1)21 transfers read data from time t13 to time t15, and the memory module (PSRAM2)22 transfers read data from time t13 to time t 15. Therefore, the period from time t13 to time t15 can be referred to as a synchronous data read period Tdat _ sync, and the read data transmitted by the memory modules (PSRAM1)21 and (PSRAM2)22 can be referred to as synchronous read data DATm1 and DATm 2.

In some applications, the memory module (PSRAM2)22 may be designed to suspend the transfer of read data from the internal buffer to the system I/O signal SIO [16:9] upon learning of an update conflict at the memory module (PSRAM1)21, and wait until time t13 before the memory module (PSRAM2)22 starts to transmit the read strobe signals m2strb1, m2strb2 and the synchronous read data DATm 2. That is, the data strobe mask signal DQSM [2] corresponding to the memory module (PSRAM2)22 is maintained at a low level during the period from time t2 to time t13, and the system input/output signals SIO [16:9] corresponding to the memory module (PSRAM2)22 are suspended from being outputted during the period from time t8 to time t 13.

Please refer to fig. 8B, which is a waveform diagram illustrating an embodiment of a synchronous read operation between the memory modules PSRAM1, PSRAM2 and the host device using the data strobe mask signal DQSM in combination with a delayed-reward mode (mode B) according to the present invention. In the figure, the time t1 to the time t17 are the read operation period Trd; the time t1 to the time t16 are chip selection periods Tcs; the set period Tset is set from time t1 to time t 3; time t3 to time t4 are the read command transfer period Tcmd; the time t4 to the time t9 are address transfer periods Tadr; the time t9 to the time t15 are the synchronization data preparation period Tsdatpr; time t15 to time t17 are the synchronous data reading period Tdat _ sync; the end period Tend is from time t16 to time t 17.

After the master control device 23 pulls down the chip select signal CS # to a low level at time t1, the memory modules (PSRAM1)21 and (PSRAM2)22 keep the data strobe mask signals DQSM [1] and DQSM [2] at a low level at time t 2. Then, during the period from the time point t3 to the time point t4, the master control device 23 issues the read commands m1CMDrd, m2CMDrd to the memory modules (PSRAM1)21 and (PSRAM2)22 through the system input/output signal lines SIO [16:1 ]. Then, during the period from time t4 to time t6, the master 23 transmits the column address m1ADRr corresponding to the memory module (PSRAM1)21 using the system input/output signals SIO [8:1], and transmits the column address m2ADRr corresponding to the memory module (PSRAM2)22 using the system input/output signals SIO [16:9 ]. During the period from time t6 to time t9, the master 23 transmits the row address m1ADRc corresponding to the memory module (PSRAM1)21 using the system input/output signals SIO [8:1], and transmits the row address m2ADRc corresponding to the memory module (PSRAM2)22 using the system input/output signals SIO [16:9 ].

As mentioned above, when the memory module (PSRAM1)21 adopts the delayed reporting mode (mode B), it is required to wait for the memory module (PSRAM1)21 to receive the column address m1ADRr before notifying the master 23. Therefore, the memory module (PSRAM1)21 notifies the master device 23 that an update collision has occurred therein by pulling the level of the data strobe mask signal DQSM [1] high during the period between time t7 and time t 8. The period from the time point t7 to the time point t8 may be defined as a new conflict notification period Trfrp required for the memory module (PSRAM1)21 with an update conflict to notify the master 23 of the update conflict.

Then, during the period from time t9 to time t10 (extended read command period Tcmdext), the host 23 transmits the extended read command m1CMDext to the memory module (PSRAM1)21 by using the data strobe mask signal DQSM [1], and transmits the extended read command m2CMDext to the memory module (PSRAM2)22 by using the data strobe mask signal DQSM [2], respectively. Accordingly, at time t10, the memory module (PSRAM2)22 already knows that the current read operation should not be performed at the speed of the normal read operation by the host 23, and additionally waits for the internal refresh collision of the memory module (PSRAM1) 21.

As described above, the memory module (PSRAM1)21 and (PSRAM2)22 receive the column addresses m1ADRr and m2ADRr and then count the read delay count LC. Therefore, as can be seen from fig. 8B, the memory modules (PSRAM1)21 and (PSRAM2)22 each count the read delay count from time t 5. The memory module (PSRAM1)21 takes two read latency counts (LC × 2) to get read data from the internal memory array to the internal buffer, while the memory module (PSRAM2)22 only needs one read Latency Count (LC) to get read data from the internal memory array to the internal buffer. Next, how the memory modules (PSRAM1)21, (PSRAM2)22 transfer the read data datem 1, datem 2 in synchronization with when, respectively, they are described.

The memory module (PSRAM1)21 ends its update conflict at time t14, and generates the read strobe signals m1strb1, m1strb2 with the data strobe mask signal DQSM [1] sequentially at the next rising edge of the system clock signal SCLK (i.e., time t 15). Therefore, the internal buffer of the memory module (PSRAM1)21 starts transferring the synchronous read data DATm1 by the system I/O signals SIO [16:9] at time t 15. The time t5 to the time t15 are defined as the update collision read period Trdrf.

Since the memory module (PSRAM2)22 can complete reading at the end of one reading delay count (i.e., time t11), and generate the reading strobe signals m2strb1 'and m2strb 2' with the data strobe mask signal DQSM [2] successively at the next rising edge of the system clock signal SCLK (i.e., time t 12). Therefore, the memory module (PSRAM2)22 will transfer the read data from the internal buffer from time t12 to time t 13.

After that, the memory module (PSRAM2)22 remains idle for a period (time t13 to time t15), and then generates the read strobe signals m2strb1 and m2strb2 with the data strobe mask signal DQSM [2] from time t 15. In addition, the memory module (PSRAM2)22 will also transmit the synchronous read data DATm2 again with the system input/output signals SIO [16:9] from time t 15.

Similar to fig. 8A, the master device 23 does not use the read data transmitted by the memory module (PSRAM2)22 from time t12 to time t13, but uses the synchronous read data DATm2 transmitted by the memory module (PSRAM2)22 from time t15 to time t 17. Also, therefore, the read data transferred by the memory module (PSRAM2)22 during the time point t12 to the time point t13 may be referred to as discarded data drpDATm2, and the period during which the memory module (PSRAM2)22 transfers the discarded data drpDATm2 may be defined as a data discard period Tdrp 2. The discarded data drpDATm2 transmitted from the time point t12 to the time point t13 and the synchronous read data DATm2 transmitted from the time point t15 to the time point t17 of the system io signal SIO [16:9] are provided by the internal buffer of the memory module (PSRAM2)22, and the contents of the two are identical.

The time t11 to the time t15 correspond to the extra waiting period for the memory module (PSRAM2)22 to wait for the update conflict of the memory module (PSRAM1)21 to end. In the period from the time point t11 to the time point t15, the memory module (PSRAM2)22 (in which no update conflict occurs) is not the period required for executing the read operation itself, but the period for waiting for the read operation is suspended in response to the end of the update conflict of the memory module (PSRAM1)21 (in which the update conflict actually occurs). Therefore, the time t11 to the time t15 are defined herein as the extra waiting period Taddwt of the memory module (PSRAM2)22 (in which no update conflict occurs).

As shown in fig. 8B, the memory module (PSRAM1)21 transmits the synchronous read data DATm1 from time t15 to time t17, and the memory module (PSRAM2)22 transmits the synchronous read data DATm2 from time t15 to time t 17. Therefore, the period from the time point t15 to the time point t17 is the synchronous data reading period Tdat _ sync. During the synchronous data read period Tdat _ sync, the internal buffers of the memory modules (PSRAM1)21, (PSRAM2)22 can synchronously transfer read data to the master 23 via the system input/output signals SIO [8:1], SIO [16:9 ].

Please note that, in practical applications, the method shown in FIG. 8B may be combined with other variations. For example, due to the update conflict occurring with the memory module (PSRAM1)21 itself, the master 23 need only notify the memory module (PSRAM2)22 that no update conflict has occurred. Therefore, in some applications, the master 23 may issue the extended read instruction m2CMDext to the memory module (PSRAM2)22, but not issue the extended read instruction m1CMDext to the memory module (PSRAM1) 21.

Furthermore, in some applications, the memory module (PSRAM2)22 may only transmit the synchronous read data DATm2 and not the discard data drpDAtm2 using the system input output signals SIO [16:9 ]. Therefore, the memory module PSRAM2 stops transmitting any data during the time period from t10 to t15, and the data strobe mask signal DQSM [2] is maintained at a low level during the time period from t2 to t 15. Variations on these applications are not detailed here.

Please refer to fig. 8A and fig. 8B. Since the immediate reporting mode (mode a) described in fig. 8A reports back to the master 23 that a conflict occurs earlier than the delayed reporting mode (mode B) described in fig. 8B, the conflict notification period Trfrp in fig. 8A is shorter than the conflict notification period Trfrp in fig. 8B. In addition, the lengths of the extra waiting period Taddwt and the update collision read period Trdrf are not different according to the reporting mode used. Moreover, in practical applications, different memory modules may be matched with different reporting modes.

In the embodiment shown in FIGS. 8A and 8B, the existing data strobe mask signal lines DQSM [1] and DQSM [2] are used as the medium for the memory modules PSRAM1 and PSRAM2 to report whether a refresh collision occurs or not. In some applications, the additional signal lines may be used as a medium for the memory modules PSRAM1 and PSRAM2 to report whether update conflicts occur or not. Fig. 9A, 9B, and 10 show examples in which bank busy signal lines (BRBB for short) are provided in the memory modules (PSRAM1)51, the (PSRAM2)52, and the master 53, and the bank busy signal lines BRBB are used as the memory modules (PSRAM1)51, the (PSRAM2)52, and update conflicts are reported to the master 53. Fig. 9A and 9B show the situation where the connection of the bank busy signal line BRBB between the host 53 and the memory module (PSRAM1)51 and (PSRAM2)52 changes the driving side according to the state of the read operation.

In fig. 9A and 9B, an electronic device 50 includes a host 53 and

memory modules

51 and 52. The master control device 53 is electrically connected to the memory module (PSRAM1)51 and the (PSRAM2)52 through the CS # and the system clock signal SCLK. In addition, the master device 53 is electrically connected to the memory module 51 via the system input/output signals SIO [8:1] and the data strobe mask signal DQSM [1], and is electrically connected to the memory module (PSRAM2)52 via the system input/output signals SIO [16:9] and the data strobe mask signal DQSM [2 ]. Further, the bank busy signal line BRBBh of the master 53, the bank busy signal line BRBBm1 of the memory module (PSRAM1)51, and the bank busy signal line BRBBm2 of the memory module (PSRAM2)52 are electrically connected in common. According to an embodiment of the present invention, the bank busy signal lines BRBBh, BRBBm1, BRBBm2 may be connected to each other using a general wiring. Alternatively, the bank busy signal lines BRBBh, BRBBm1, and BRBBm2 may be used in combination with the

bidirectional interface circuits

501, 511, 521 and the pull-up resistor 50a, as shown in fig. 9A and 9B. The pull-up resistor 50a is electrically connected between the supply voltage Vcc and the bank busy signal line BRBBh. In fig. 9A and 9B, the driving directions of signals on the bank busy signal lines BRBBh, BRBBm1 and BRBBm2 are indicated by dotted lines.

When the bank busy signal lines BRBBh, BRBBm1, BRBBm2 are used in combination with the

bidirectional interface circuits

501, 511, 521 and the pull-up resistor 50a, the memory module (e.g., the memory module (PSRAM1)51) with the conflict of update can simultaneously notify the master control device 53 of the conflict of update with other memory modules (e.g., the memory module (PSRAM2)52) without the conflict of update based on the wired-OR (wired-OR) connection. In fig. 9A and 9B, the bidirectional interface circuit 501 of the master 53 includes an output inverter 501a and an input inverter 501B connected in opposite ways; the bidirectional interface circuit 511 of the memory module (PSRAM1)51 includes an output inverter 511a and an input inverter 511b connected in opposite ways; the bidirectional interface circuit 521 of the memory module (PSRAM2)52 includes an output inverter 521a and an input inverter 521b connected in opposite ways.

Please refer to fig. 9A, which illustrates a memory busy signal line BRBB disposed between the memory module and the host device and driven by the host device. When the bank busy signal line is driven by the master 53, the driving signal from the master 53 is first transmitted from the output inverter 501a of the bi-directional interface circuit 501 to the bank busy signal line BRBBh, then transmitted to the memory module (PSRAM1)51 via the bank busy signal line BRBBm1 and the input inverter 511b of the bi-directional interface circuit 511, and transmitted to the memory module (PSRAM2)52 via the bank busy signal line BRBBm2 and the input inverter 521b of the bi-directional interface circuit 521.

Please refer to fig. 9B, which illustrates a memory module driven by a bank busy signal line BRBB disposed between the memory module and the host. When the bank busy signal line uses the memory module (PSRAM1)51 as the driving end, the memory module (PSRAM1)51 firstly transmits the driving signal from the output inverter 511a of the bidirectional interface circuit 511 to the bank busy signal line BRBBm1, then transmits the driving signal to the host 53 via the bank busy signal line BRBBh and the input inverter 501b of the bidirectional interface circuit 501, and transmits the driving signal to the memory module (PSRAM2)52 via the bank busy signal line BRBBm2 and the input inverter 521b of the bidirectional interface circuit 521.

In a default condition, if neither the master 53 nor the memory modules (PSRAM1)51, 52 (PSRAM2) generate driving signals, the pull-up resistor 50a is used to keep the bank busy signals BRBBh, BRBBm1, BRBBm2 at a high level. In the present invention, it is assumed that the driving capability of the memory module (PSRAM1)51 and (PSRAM2)52 for the bank busy signals BRBBm1 and BRBBm2 is greater than the driving capability of the master 53 for the bank busy signal BRBBh. The driving capability of the bank busy signal BRBBh sent by the master 53 is greater than that of the pull-up resistor 50 a.

Next, an example of the memory module reporting whether an update conflict occurs to the master 53 by using the bank busy signals BRBB (PSRAM1)51 and (PSRAM2)52 will be described with reference to fig. 10 by using the wiring diagrams shown in fig. 9A and 9B.

Referring to fig. 10, a waveform diagram of an embodiment of a synchronous read operation between a memory module and a host using a bank busy signal line BRBB in conjunction with a mode a is shown. In the figure, the time t1 to the time t15 are the read operation period Trd; the time t1 to the time t14 are chip selection periods Tcs; the set period Tset is set from time t1 to time t 3; time t3 to time t4 are the read command transfer period Tcmd; the time t4 to the time t8 are address transfer periods Tadr; the time t8 to the time t13 are the synchronization data preparation period Tsdatpr; time t13 to time t15 are the synchronous data reading period Tdat _ sync; the end period Tend is from time t14 to time t 15.

After the master 53 pulls the chip select signal CS # low at time t1, the memory module (PSRAM1)51 notifies the master 53 that an update conflict occurs inside it by pulling the level of the bank busy signal BRBBm1 low at time t 2. The memory module (PSRAM1)51 maintains the bank busy signal BRBBm1 at a low level from time t2 to time t7, and starts to pull the bank busy signal BRBBm1 at time t7 to a high level. The time period from the time point t2 to the time point t7 may be defined as an update conflict notification period Trfrp.

On the other hand, during the period from the time t1 to the time t7, the memory module PSRAM2 maintains the bank busy signal BRBBm2 at a high level. At this time, the driving of signals between the bank busy signal lines BRBBh, BRBBm1, and BRBBm2 is shown in fig. 9B. Namely, the bank busy signal BRBBm1 sent by the memory module (PSRAM1)51, the bank busy signal BRBBh driving the master, and the bank busy signal BRBBm2 corresponding to the memory module (PSRAM2) 22.

Although the bank busy signal BRBBm2 sent from the memory block (PSRAM2)52 is high in fig. 10, the level of the bank busy signal line BRBBm2 of the memory block PSRAM2 is lowered since the memory block (PSSRAM1)51 is actively driven from the time t2 at the time t 2. In conjunction, the memory module (PSRAM2)52 can immediately know that the other memory module (i.e., the memory module (PSRAM1)51) has a conflict in updating by the level decrease of the bank busy signal BRBBm 2.

In fig. 10, the memory module PSRAM2 is notified by the hardware connection shown in fig. 9A and 9B. Therefore, in fig. 10, the master 53 does not need to notify the memory module PSRAM2 in the form of an instruction in the manner shown in fig. 8A and 8B.

In some applications, the bank busy signal lines BRBBh, BRBBm1, and BRBBm2 may be used without the bidirectional interface circuit and the pull-up circuit. For these applications, the master 53 may notify the memory module (PSRAM2)52 as shown in fig. 8A and 8B.

As previously described, the memory module (PSRAM1)51, (PSRAM2)52 counts the read delay count from receiving the column addresses m1ADRr, m2 ADRr. Therefore, as can be seen from fig. 10, the memory modules (PSRAM1)51 and (PSRAM2)52 each count the read delay count from time t 5. The memory module (PSRAM1)51 requires two read latency counts (LC × 2) to be ready for the internal buffer, while the memory module PSRAM2 requires only one read Latency Count (LC) to be ready for the internal buffer. Next, how the memory modules PSRAM1, PSRAM2 transfer the synchronous read data DATm1, DATm2, respectively, will be described.

The conflict of the updates of the memory module (PSRAM1)51 ends at the time point t12, and at the next rising edge of the system clock signal SCLK (i.e., at the time point t13), the read strobe signals m1strb1, m1strb2 are sequentially generated with the data strobe mask signal DQSM [1 ]. Therefore, the memory module (PSRAM1)51 starts to transmit the synchronous read data DATm1 by the system I/O signals SIO [8:1] at time t 13.

Since the memory module (PSRAM2)52 can complete reading at the end of one reading delay count (i.e., time t9), and generate the reading strobe signals m2strb1 'and m2strb 2' successively with the data strobe mask signal DQSM [2] at the next rising edge of the system clock signal SCLK (i.e., time t 10). Therefore, the memory module (PSRAM2)52 starts transferring the discard data drpDAtm2 by using the system input/output signals SIO [16:9] from time t 10. The period during which the memory module (PSRAM2)52 transfers the discard data drpDATm2 is defined as a data discard period Tdrp 2.

After that, the memory module (PSRAM2)52 remains idle for a period (time t11 to time t13), and then generates the read strobe signals m2strb1 and m2strb2 with the data strobe mask signal DQSM [2] from time t 13. The time t9 to the time t13 may be defined as the additional waiting period Taddwt that the memory module (PSRAM2)22 takes to wait for the update conflict of the memory module (PSRAM1)51 to end. The memory module (PSRAM2)52 will also transmit the synchronous read data DATm2 again from time t 13.

According to the idea of the present invention, the master device 53 does not use the discarded data drpDATm2 transmitted by the memory module (PSRAM2)52 from time t9 to time t10, but uses the synchronous read data DATm2 transmitted by the memory module (PSRAM2)52 from time t13 to time t 15. The discard data drpDAtm2 and the synchronous read data DATm2 transmitted via the system I/O signals SIO [16:9] are both provided by the memory module (PSRAM2)22, and the contents of both are identical.

The time points t5 to t13 are defined as the update conflict read period Trdrf required for waiting for the memory module (PSRAM1)51 to copy the read data to the internal buffer in response to the update conflict occurred in the memory module (PSRAM1) 51. As can be seen from fig. 10, the memory module (PSRAM1)51 transmits synchronous read data DATm1 during the period from time t13 to time t15, and the memory module (PSRAM2)52 transmits synchronous read data DATm2 during the period from time t13 to time t15 (synchronous data read period Tdat _ sync). Therefore, the memory module (PSRAM1)51, (PSRAM2)52 can synchronously transfer read data to the master 53.

Fig. 10 shows waveforms of an immediate reporting mode (mode a) and delayed reporting modes (mode B) between the memory modules (PSRAM1)51, PSRAM2)52 and the host 53, using the bank busy signal lines BRBBh, BRBBm1 and BRBBm 2. The operation of incorporating the delayed reporting mode (mode B) can be generalized to the description of FIGS. 8B and 10 and is not described in detail.

Furthermore, the present invention may also be configured with the existing signal lines (e.g., the chip select signal CS #, the system clock signal SCLK, the data strobe mask signal DQSM, etc.) between the main control device and the memory modules PSRAM1 and PSRAM2, and the additional signal lines, so as to generate specific waveform changes, which are used to report the states of the memory modules (PSRAM1)51 and (PSRAM2) 52. For example, in FIG. 11, assume that the change of the bank busy signals BRBBm1, BRBBh is collocated with the data strobe mask signal DQSM [1 ].

Referring now to FIG. 11, a waveform diagram of another embodiment of a synchronous read operation between the memory module PSRAM1 and a master device in a mode A mode is shown, according to the present invention. In the figure, the time t1 to the time t13 are the read operation period Trd; the time t1 to the time t12 are chip selection periods Tcs; the set period Tset is set from time t1 to time t 3; time t3 to time t4 are the read command transfer period Tcmd; the time t4 to the time t8 are address transfer periods Tadr; the time t8 to the time t11 are the synchronization data preparation period Tsdatpr; time t11 to time t13 are the synchronous data reading period Tdat _ sync; the end period Tend is from time t12 to time t 13.

After the master device 53 pulls the chip select signal CS # low at time t1, the memory module (PSRAM1)51 notifies the master device 53 that an update conflict is generated therein by pulling the level of the bank busy signal BRBBm1 low and the level of the data strobe mask signal DQSM [1] high at time t 2. The memory module (PSRAM1)51 maintains the bank busy signal BRBBm1 at a low level and the data strobe mask signal DQSM [1] at a high level during the time point t2 to the time point t7 (update conflict notification period Trfrp).

Since the memory module (PSRAM1)51 maintains the bank busy signal BRBBm1 at a low level during the update conflict notification by Trfrp, the bank busy signal BRBBh will be affected by the bank busy signal BRBBm1 from the memory module (PSRAM1)51 and maintained at a low level during the update conflict notification by Trfrp, as shown in fig. 9B. Memory module (PSRAM1)51 stops pulling bank busy signal BRBBm1 high at time t7 and begins pulling data strobe mask signal DQSM [1] low.

On the other hand, during the time t1 to the time t7, the memory module (PSRAM2)52 maintains the bank busy signal BRBBm2 at a high level and the data strobe mask signal DQSM [2] at a low level. Although the memory module (PSRAM2)52 maintains the bank busy signal BRBBm2 at a high level during the period from time t2 to time t7, the memory module (PSRAM1)51 reflects the change of pulling the bank busy signal BRBBm1 to a low level during the period from time t2 to time t7 to the bank busy signal BRBBm2 due to the connection of the bank busy signals BRBBh, BRBBm1 and BRBBm2 by a wired OR (wired OR) manner, so that the level of the bank busy signal BRBBm2 fluctuates. Therefore, the memory module (PSRAM2)52 can know that the memory module (PSRAM1)51 has an update conflict through the signal fluctuation of the bank busy signal BRBBm 2.

Accordingly, the master 53 can know that the memory module (PSRAM1)51 generates an update conflict according to the bank busy signal BRBBh. In addition, as illustrated in fig. 9B, the memory module (PSRAM2)52 may directly check that the memory module (PSRAM1)51 has an update conflict through a wired OR connection. In other words, when wired-OR connection is adopted, the memory module (PSRAM2)52 can directly know that the memory module (PSRAM1)51 has an update conflict via the bank busy signal BRBBm2 without indirectly knowing through the master 53.

As previously described, the memory module (PSRAM1)51, (PSRAM2)52 counts the read delay count from receiving the column addresses m1ADRr, m2 ADRr. Therefore, as can be seen from fig. 11, the memory modules (PSRAM1)51 and (PSRAM2)52 each count the read delay count from time t 5. The memory module (PSRAM1)51 takes two read latency counts (LC × 2) to get read data from the internal memory array to the internal buffer, while the memory module (PSRAM2)52 only needs one read Latency Count (LC) to get read data from the internal memory array to the internal buffer. Next, how the memory modules (PSRAM1)51, (PSRAM2)52 transfer the read data datem 1, datem 2 in synchronization with when, respectively, they are described.

After the memory module (PSRAM1)51 starts from the time point t5 and passes through the update read delay rfcclc (e.g., rfcclc ═ LC × 2), the update collision ends at the time point t10, and the memory module (PSRAM1)51 generates the read strobe signals m1strb1 and m1strb2 with the data strobe mask signal DQSM [1] at the rising edge of the next system clock signal SCLK after the time point t10 (i.e., at the time point t 11). Therefore, the memory module (PSRAM1)51 starts transmitting the synchronous read data DATm1 at time t 11.

On the other hand, after a preset read delay (dftLC — LC × 1) from time t5, the memory module (PSRAM2)52 may prepare the read data in the internal buffer at time t 9. Because of the update collision of the memory module (PSRAM1)51, the memory module (PSRAM2) knows that after the preset read delay (dftLC ═ LC × 1) is over, the memory module (PSRAM2) cannot transmit read data immediately after the next rising edge of the system clock signal SCLK after the preset read delay (dftLC ═ LC × 1) is over (time t 9). The time t9 to the time t11 may be defined as the additional waiting period Taddwt that the memory module (PSRAM2)22 takes to wait for the update conflict of the memory module (PSRAM1)51 to end.

The time points t5 to t11 are defined as the update conflict read period Trdrf required for waiting for the memory module (PSRAM1)51 to copy the read data to the internal buffer in response to the update conflict occurred in the memory module (PSRAM1) 51. As shown in fig. 11, the memory module (PSRAM1)51 transmits the synchronous read data DATm1 from time t11 to time t13, and the memory module (PSRAM2)52 transmits the synchronous read data DATm2 from time t11 to time t 13. The period from the time point t11 to the time point t13 may be defined as a synchronous data reading period Tdat _ sync. Therefore, the memory modules (PSRAM1)51 and (PSRAM2)52 can synchronously transmit the read data in the internal buffer to the master 53 by using the system I/O signals SIO [16:1 ].

In addition to fig. 9A and 9B, the extra memory bank busy signal BRBB is used with the bidirectional interface circuit and the pull-up resistor 50a, and the chip select signal CS # can also be used with the bidirectional interface circuit and the pull-up resistor 40a, as shown in fig. 12A and 12B.

In fig. 12A and 12B, the electronic device 40 includes a master device 43 and a memory module (PSRAM1)41 and (PSRAM2) 42. The main control device 43 is electrically connected to the memory module (PSRAM1)41 and the (PSRAM2)42 through the chip selection signal CS # and the system clock signal SCLK. In addition, the master device 43 is electrically connected to the memory module (PSRAM1)41 via the system input/output signals SIO [8:1] and the data strobe mask signal DQSM [1], and is electrically connected to the memory module (PSRAM2)42 via the system input/output signals SIO [16:9] and the data strobe mask signal DQSM [2 ]. It is assumed that the chip select signal CS # is used in conjunction with the

bi-directional interface circuits

401, 411, 421 and the pull-up resistor 40 a.

When the chip select signal CS # is used in conjunction with the

bi-directional interface circuits

401, 411, 421 and the pull-up resistor 40a, the memory module (e.g., the memory module (PSRAM1)41) with the conflict of update can achieve the effect of simultaneously notifying the master control device 43 of the conflict of update with other memory modules (e.g., the memory module (PSRAM2)42) without conflict of update based on the wired-OR (wired-OR) connection. In fig. 12A and 12B, the bidirectional interface circuit 401 of the master control device 43 includes an output inverter 401a and an input inverter 401B connected in opposite ways; the bidirectional interface circuit 411 of the memory module (PSRAM1)41 includes an output inverter 411a and an input inverter 411b connected in opposite ways; the bidirectional interface circuit 421 of the memory module (PSRAM2)42 includes an output inverter 421a and an input inverter 421b connected in opposite ways.

Please refer to fig. 12A and 12B, which are schematic diagrams illustrating a communication interface between the memory module and the host device using the chip select signal CS # as an update conflict, wherein the chip select signal CS # is driven by the host device 43 and the memory module (PSRAM1)41, respectively. The driving method of the chip select signal CS # in fig. 12A and 12B is similar to the driving method of the bank busy signal BRBB in fig. 9A and 9B, and therefore, will not be described in detail.

When the chip select signal CS # is connected by a wired OR (wired OR) as shown in fig. 12A and 12B, the memory modules (PSRAM1)41 and (PSRAM2)42 may also affect the level of the chip select signal CS #. Therefore, in some applications, the chip select signal CS # may be used for communication purposes for performing the synchronous read operation. For example, fig. 13 shows an embodiment in which the memory module (PSRAM1)41 performs a synchronous read operation according to the immediate return mode (mode a) via the chip select signal CS #.

Please refer to fig. 13, which is a waveform diagram of an embodiment in which the memory module and the host utilize the chip select signal CS # as a communication interface for update conflicts, and the memory module performs a synchronous read operation after notifying the host according to the immediate reporting mode (mode a). In the figure, the time t1 to the time t13 are the read operation period Trd; the time t1 to the time t4 are chip selection periods Tcs; the set period Tset is set from time t1 to time t 3; time t3 to time t4 are the read command transfer period Tcmd; the time t4 to the time t7 are address transfer periods Tadr; the time t7 to the time t12 are the synchronization data preparation period Tsdatpr; the time t12 to the time t13 are the synchronous data reading period Tdat _ sync. Here, the time t5 to the time t12 are the update collision read period Trdrf. The time t8 to the time t12 may be defined as the additional waiting period Taddwt that the memory module (PSRAM2)42 takes to wait for the update conflict of the memory module (PSRAM1)41 to end. Here, the time t5 to the time t12 are the update collision read period Trdrf.

Please note that, in this embodiment, if any memory module (for example, the memory module PSRAM1) has a conflict in update, the memory module with the conflict in update will pull up the chip select signal CS # to force the read operation to end. Therefore, the read operation period Trd shown in fig. 13 does not include the end period Tend, and the length of the chip picking period Tcs is much shorter than the chip picking period Tcs of the other embodiments. In fig. 13, the update collision notification period Trfrp is almost equal to the chip select period Tcs because of the use of the chip select signal CS # notification.

In this embodiment, the memory module (PSRAM1)41 senses the moment when the master device 43 pulls the chip select signal CS # low at time t1, i.e. it is known that there is an update conflict inside. Therefore, at the time t4, the memory module (PSRAM1)41 pulls up the chip select signal CS # and in this way notifies the master device 43 that there is an update conflict inside it. That is, before the time t4, the master device 43 is used as the driving terminal of the chip selection signal CS # as shown in fig. 12A. During the period from the time point t4 to the time point t13, the memory module (PSRAM2)42 is used as the driving terminal of the chip select signal CS # as shown in fig. 12B.

Since the master device 43, the memory module (PSRAM1)41, and the memory module (PSRAM2)42 are all connected to the chip select signal CS #, the memory module (PSRAM2)42 can also know that the refresh collision occurs inside the memory module (PSRAM1)41 at time t 4. Therefore, the memory module (PSRAM2)42 can know that the read data in the internal buffer cannot be immediately transferred to the master device 43 at the rising edge (time t9) of the next system clock signal SCLK after the preset read delay (dftLC ═ LC × 1) (time t 8).

As shown in fig. 13, the memory module (PSRAM2)42 immediately transmits the read data to the master device 43 during the data discard period Tdrp2 at the rising edge (time t9) of the next system clock signal SCLK after the preset read delay (dftLC — LC × 1) is finished, but the read data transmitted during the data discard period Tdrp2 is discarded by the master device 43, which is called discarded data discard drpDATm 2. Therefore, the memory module (PSRAM2)42 still needs to start at time t12, issue the read strobe signals m2strb1 and m2strb2 again by using the data strobe mask signal DQSM [2], and transmit the synchronous read data DATm2 again by using the system input/output signals SIO [16:9 ]. The discard data drpDAtm2 and the synchronous read data DATm2 transmitted via the data strobe mask signal DQSM [2] are both provided by the memory module (PSRAM2)42, and the contents of both are identical.

Fig. 13 is a waveform diagram of an immediate reporting mode (mode a) associated with a chip select signal CS # between the memory module (PSRAM1)41 and the host, and in practice, a delayed reporting mode (mode B) may be associated with the memory module (PSRAM1)41 and the host 43. The operation of incorporating the delayed reporting mode (mode B) can be generalized to the description of FIGS. 8B and 13 and is not described in detail.

Please refer to fig. 14, which is a waveform diagram of an embodiment of performing a synchronous read operation between a memory module and a host according to a mode a by using a chip select signal CS # and a system clock signal SCLK. In the figure, the time t1 to the time t12 are the read operation period Trd; the time t1 to the time t12 are chip selection periods Tcs; the set period Tset is set from time t1 to time t 3; time t3 to time t4 are the read command transfer period Tcmd; the time t4 to the time t8 are address transfer periods Tadr; the time t8 to the time t13 are the synchronization data preparation period Tsdatpr; time t13 to time t15 are the synchronous data reading period Tdat _ sync; the end period Tend is from time t14 to time t 15. Here, the time t5 to the time t13 are the update collision read period Trdrf. From time t5 to time t11, the memory module (PSRAM2)42 performs a predetermined read delay (dftLC 1) for the read operation. The time t11 to the time t13 may be defined as the additional waiting period Taddwt that the memory module (PSRAM2)42 takes to wait for the update conflict of the memory module (PSRAM1)41 to end.

In this embodiment, it is assumed that the memory device (PSRAM1)41 achieves the effect of notifying the master device 43 and the memory module (PSRAM2)42 of the update collision occurrence situation by pulling the level of the chip select signal CS # high during one complete cycle of the system clock signal SCLK. In fig. 14, it is assumed that the master 43 pulls up the level of the chip select signal CS # during the period from t9 to t10 (corresponding to the period of the entire period Tclk4 of the system clock cycle). Therefore, the period from the time point t9 to the time point t10 may be defined as a suspended read notification period Tstp for notifying the memory module (PSRAM2)42 of the suspension of the read operation by the master device 43. In this drawing, it is assumed that the update collision notification period Trfrp corresponds to the system frequency period Tclk4 of the system frequency signal SCLK.

In practical applications, the master control device 43 is not limited to notify the memory module (PSRAM2)42 of the system clock signal SCLK with the chip select signal CS #. For example, master 43 may choose to pull up the chip select signal CS # during any one of the system clock periods Tclk 1-Tclk 8. Since the preset read delay (dftLC — LC × 1) required for the memory module PSRAM2 to perform the read operation is ended at time t11, if the chip select signal CS # is pulled up by the host device 43 earlier than time t11, the memory module (PSRAM2)42 can know in real time that the read data should be temporarily stopped from being transmitted from the internal buffer after the preset read delay is ended. If the master device 43 pulls the chip select signal CS # high before the time point t11, the memory module PSRAM2 will suspend transferring the data of the internal buffer after the end of the time point t 11. Until the synchronous data preparation period Tsdatpr ends, the memory module (PSRAM2)42 resumes the transfer of the synchronous read data DATm2 from the internal buffer.

On the other hand, if the master device 43 pulls up the chip select signal CS # later than the time t 11. For example, the master 43 pulls up the chip select signal CS # during the system clock periods Tclk6, Tclk7, and Tclk 8. Then, the memory module (PSRAM2)42 needs to transfer the read data from the internal buffer twice to the system input/output signal SIO [16:9 ].

Fig. 14 shows a waveform diagram of the memory module (PSRAM1)41 notifying the master device 43 using the immediate reporting mode (mode a) and the master device 43 notifying the memory module (PSRAM2)42 using the combination of the chip select signal CS # and the system clock signal SCLK, but in practice, the combination of the chip select signal CS # and the system clock signal SCLK may be matched by using the delayed reporting mode (mode B). The operation of incorporating the delayed reporting mode (mode B) can be generalized to the description of FIG. 8B and is not described in detail.

In accordance with the present invention, the memory module PSRAM2 knows the manner in which to wait for the period Tsdatpr during which the synchronization data is to be prepared is quite flexible. For example, in practical applications, frequency override signal lines ICK1 and ICK2 may be additionally provided between the host and the memory modules PSRAM1 and PSRAM 2. The frequency ignoring signals ICK1, ICK2 are at low level most of the time, but when the master device pulls the frequency ignoring signals ICK1, ICK2 high, the memory modules PSRAM1, PSRAM2 temporarily skip the change of the system frequency signal SCLK while the frequency ignoring signals ICK1, ICK2 are pulled high.

Please refer to fig. 15, which is a waveform diagram of an embodiment of the clock ignore signal lines ICK1, ICK2 between the host and the memory modules PSRAM1, PSRAM2, and performing a synchronous read operation in case of a conflict of update in the memory module PSRAM 1. In the figure, the time t1 to the time t14 are the read operation period Trd; the time t1 to the time t13 are chip selection periods Tcs; the set period Tset is set from time t1 to time t 3; time t3 to time t4 are the read command transfer period Tcmd; the time t4 to the time t8 are address transfer periods Tadr; the time t8 to the time t12 are the synchronization data preparation period Tsdatpr; time t12 to time t14 are the synchronous data reading period Tdat _ sync; the end period Tend is from time t12 to time t 13. The period from the time point t2 to the time point t7 may be defined as an update conflict notification period Trfrp during which the memory module PSRAM1 in which an update conflict occurs notifies the host. The time t5 to the time t11 may be defined as the update conflicting read period Trdrf. The time points t5 to t9 may be defined as a predetermined read delay (dftLC ═ LC × 1) required for the memory module PSRAM2 to perform a read operation. The time t9 to the time t11 may be defined as the additional waiting period Taddwt that the memory module PSRAM2 takes to wait for the update conflict of the memory module PSRAM1 to end.

In fig. 15, the master temporarily pulls up the level of the clock ignore signal ICK2 from time t10 to time t 11. Here, the period from the time point t10 to the time point t11 may be defined as a frequency ignoring period Tick. During the frequency ignore period Tick, the memory module PSRAM2 will suspend internally receiving the system frequency signal SCLK. Also, therefore, the memory module PSRAM2 suspends operation by Tick during the frequency ignore period. After the clock ignore period Tick ends (time t11), the master device pulls down the clock ignore signal ICK2 to low level again, and the memory module PSRAM2 receives the clock of the system clock signal SCLK again and continues the read operation. Therefore, at time t12, the memory modules PSRAM, PSRAM2 start synchronously transferring read data.

In the example of fig. 15, the master device generates the clock ignore signal ICK2 to the memory module PSRAM2, thereby notifying the memory module PSRAM2 to suspend receiving the system clock signal SCLK. In the embodiment of fig. 16, it is assumed that the master device actually stops transmitting the system clock signal SCLK to the memory module PSRAM 2. Compared with fig. 15, the method of fig. 16 does not require additional wiring, and the cost is relatively low.

Please refer to fig. 16, which is a schematic diagram illustrating that after the master control device knows that the memory module PSRAM1 has an update conflict, the master control device delays the read operation by suspending providing the system clock signal SCLK to the memory modules PSRAM1 and PSRAM2, and further performs a synchronous read operation on the memory modules PSRAM1 and PSRAM 2. In the figure, the time t1 to the time t13 are the read operation period Trd; the time t1 to the time t12 are chip selection periods Tcs; the set period Tset is set from time t1 to time t 3; time t3 to time t4 are the read command transfer period Tcmd; the time t4 to the time t8 are address transfer periods Tadr; the time t8 to the time t11 are the synchronization data preparation period Tsdatpr; time t11 to time t13 are the synchronous data reading period Tdat _ sync; the end period Tend is from time t12 to time t 13. The period from the time point t2 to the time point t7 may be defined as an update conflict notification period Trfrp during which the memory module PSRAM1 in which an update conflict occurs notifies the host. The time t5 to the time t11 may be defined as the update conflicting read period Trdrf. The time points t5 to t9 may be defined as a predetermined read delay (dftLC ═ LC × 1) required for the memory module PSRAM2 to perform a read operation. The time t9 to the time t11 may be defined as the additional waiting period Taddwt that the memory module PSRAM2 takes to wait for the update conflict of the memory module PSRAM1 to end.

In fig. 16, the master device stops transmitting the system clock signal SCLK to the memory modules PSRAM1 and PSRAM2 during the period from time t9 to time t 11. During this period, because of the conflict of updates made inside the memory module PSRAM1, the operation of the memory module PSRAM1 is not affected even if it does not receive the system frequency signal SCLK. On the other hand, during the period from the time point t9 to the time point t11, the memory module PSRAM2 stops operating because the system clock signal SCLK is not received at the same frequency. When the timing t11 begins, the master device resumes transmitting the system clock signal SCLK to the memory modules PSRAM1 and PSRAM2, and the memory module PSRAM2 resumes operation again. Therefore, at time t11, the memory modules PSRAM, PSRAM2 start synchronously transferring the synchronous read data DATm1, DATm 2.

In the foregoing embodiment, it is assumed that the master device knows that the update conflict occurs inside the memory module PSRAM1 through the report of the memory module PSRAM 1. In practical applications, the master device may also actively control the occurrence of update conflicts inside the PSRAM1 by other means.

The above-mentioned embodiments all complete the synchronous read operation with one chip select period Tcs. In these embodiments, the synchronous data preparation period Tsdatpr is greater than the default read delay (dflc ═ LC × 1), and the synchronous data preparation period (Tsdatpr) is less than the update read delay (rfcLC ═ 2 × LC). In practice, the memory modules PSRAM1 and PSRAM2 may perform read operations in a synchronous manner using two (or more) chip select periods Tcs.

Referring to FIG. 17, the main control device issues the repeat read commands m1 CMDrry and m2 CMDrry to synchronize the memory modules PSRAM1 and PSRAM2 for read operations. In the figure, the time t1 to the time t21 are the read operation period Trd; the time t1 to the time t12 are chip selection periods Tcs 1; selecting a chip spacing Tint from the time point t12 to the time point t 14; the time t14 to the time t19 are chip selection periods Tcs 2; the set period Tset is set from time t1 to time t 3; time t3 to time t4 are the read command transfer period Tcmd; the time t4 to the time t6 are address transfer periods Tadr; the time t6 to the time t18 are the synchronization data preparation period Tsdatpr; time t19 to time t21 are the synchronous data reading period Tdat _ sync; the end period Tend is from time t20 to time t 21.

In this embodiment, the read operation period Trd includes a chip select period Tcs1, a chip select pitch Tint, a chip select period Tcs2, and an end period Tend, in this order. The chip select signals CS # are low during the chip select periods Tcs1 and Tcs2, and the chip select signals CS # are high during the chip select pitch Tint and the end period Tend.

During the chip selecting period Tcs1, the master control device receives the read data transmitted by the memory module PSRAM2 during the data discarding period Tdrp2 and the read data transmitted by the memory module PSRAM1 during the data discarding period Tdrp1 in sequence. If the masters find that the data from the internal buffers of the memory modules PSRAM1 and PSRAM2 are not consistent with the system I/O signals SIO [8:1] and SIO [16:9] within the chip select period Tcs1, it means that the masters cannot use the data correctly. Thus, the read data can be considered as discard data drpDATm1, drpDATm 2. Here, the time t5 to the time t11 are the update collision read period Trdrf.

As described above, in the chip select period Tcs1, the read data transmitted from the memory modules PSRAM1 and PSRAM2 to the host device, including the read data transmitted from the memory module PSRAM1 at time t11 to time t13 and the read data transmitted from the memory module PSRAM2 at time t8 to time t9, are ignored. In the chip picking period Tcs1, the read data transferred from the memory modules PSRAM1 and PSRAM2 to the host device are regarded as discarded data drpDATm1 and drpDATm 2.

The middle of the Tcs1 and Tcs2 is the chip picking pitch Tint. In the chip selection interval Tint, the master control device pulls up the chip selection signal CS # to a high level and maintains the system clock signal SCLK at a low level. In the chip select period Tcs2, during a period from time t14 to time t15 (the repeated read command period Tcmd _ rtry), the host device issues repeated read commands m1 cmdrry and m2 cmdrry to the memory modules PSRAM1 and PSRAM 2. The repeat read instructions m1 cmdrry, m2 cmdrry represent that the memory module PSRAM1, PSRAM2 again wait for the update read delay rfcclc (e.g., rfcclc ═ LC × 2) before performing the read operation. Here, the time points T14 to T19 are the periods of the memory modules PSRAM1 and PSRAM2 performing the read operation for the second degree, and thus are defined as the repeated read period T2 rd.

Since the memory modules PSRAM1 and PSRAM2 already receive the column addresses m1ADRr and m2ADRr and the row addresses m1ADRc and m2ADRc during the address transfer period Tadr (period from time t4 to time t 6) of the Tcs1 during the chip select period Tcs. Therefore, during the chip select period Tcs2, the master device does not need to transfer the column addresses m1ADRr, m2ADRr and the row addresses m1ADRc, m2ADRc to the memory modules PSRAM1, PSRAM2 again.

When the memory modules PSRAM1 and PSRAM2 receive the repeat read instructions m1CMDrtry and m2CMDrtry, they collectively wait for the update read delay rfcclc (e.g., rfcclc ═ LC × 2). After the time t18, the read strobe signals m1strb1 and m2strb1 are synchronously generated. During the period from time t18 to time t20, the memory module PSRAM1 transmits the read strobe signals m1strb1 and m1strb2 to the host device by using the data strobe mask signal DQSM [1], and transmits the synchronous read data DATm1 from the internal buffer to the host device by using the system input/output signals SIO [8:1 ]. At the same time, the memory module PSRAM2 uses the data strobe mask signal DQSM [2] to transmit the read strobe signals m2strb1, m2strb2 to the master, and uses the system input/output signals SIO [16:9] to transmit the synchronous read data DATm2 from the internal buffer to the master.

In FIG. 17, the discard data drpDAtm1 and the synchronous read data DATm1 transmitted via the system I/O signals SIO [8:1] are both transmitted from the internal buffer of the memory module PSRAM1, and therefore the contents of both are identical. Similarly, the discarded data drpDAtm2 and the synchronous read data DATm2 transmitted via the system I/O signals SIO [16:9] are both transmitted from the internal buffer of the memory module PSRAM2, so that the contents of the two are identical.

In the embodiment of fig. 17, the synchronous data preparation period Tsdatpr covers a part of both the chip picking periods Tcs1, Tcs 2. Therefore, the synchronous data preparation period Tsdatpr is longer than the update read delay rfcLC (Tsdatpr > rfcLC ═ 2 × LC). In the embodiment of fig. 18, the synchronous data preparing period Tsdatpr is slightly shorter than the refresh read delay rfcLC (Tsdatpr < rfcLC ═ 2 × LC).

When the memory module PSRAM of the PSRAM technology is used, the main control device enables a pre-pulse (pre-pulse) notification function of the pilot pulse signal mstrb of the data strobe mask signal DQSM by setting the buffer. The pilot pulse signal mstrb means that the memory module PSRAM pulls up the level of the data strobe mask signal DQSM for a short period of time during the high level of the system clock signal SCLK before the data strobe mask signal DQSM sends out the read strobe pulse signals mstrb1, mstrb 2. That is, before the actual pilot signals mstrb1 and mstrb2 are generated, the master device is notified in advance that the read data is to be transmitted.

In the embodiment of fig. 17, the master device may determine that the memory module PSRAM1 has an update conflict by active sensing. Thus, in this embodiment, the update conflict notification period Trfrp is not depicted. In practical applications, the embodiment of fig. 17 can also be implemented in combination with an immediate reporting mode (mode a) and a delayed reporting mode (mode B). That is, the master is still notified by the memory module PSRAM1 that an update conflict occurred.

FIG. 18 is another embodiment of actively sensing by a master device that an update conflict has occurred with the memory module PSRAM 1. Please refer to fig. 18, which is a waveform diagram of an embodiment of how to perform a synchronous read operation after a refresh collision occurs in the memory module PSRAM1 according to a time difference between generation timings of the pilot pulse signals m1pre and m2pre by using the chip select signal CS # and the system clock signal SCLK between the memory module and the main control device. In the figure, the time t1 to the time t15 are the read operation period Trd; the time t1 to the time t14 are chip selection periods Tcs; the set period Tset is set from time t1 to time t 3; time t3 to time t4 are the read command transfer period Tcmd; the time t4 to the time t7 are address transfer periods Tadr; the time t7 to the time t13 are the synchronization data preparation period Tsdatpr; time t13 to time t15 are the synchronous data reading period Tdat _ sync; the end period Tend is from time t14 to time t 15. Here, the time t5 to the time t13 are the update collision read period Trdrf. The time points t5 to t9 may be defined as a predetermined read delay (dftLC ═ LC × 1) required for the memory module PSRAM2 to perform a read operation. The time t9 to the time t13 may be defined as the additional waiting period Taddwt that the memory module PSRAM2 takes to wait for the update conflict of the memory module PSRAM1 to end.

In the example of fig. 18, it is assumed that the functions of the memory modules PSRAM1 and PSRAM2 for generating the pilot pulse signals m1pre and m2pre are both enabled. Because of the update collision of the memory module PSRAM1, the period during which the memory module PSRAM1 generates the pilot pulse signal m1pre is later than the period during which the memory module PSRAM2 generates the pilot pulse signal m2 pre. The memory module PSRAM1 generates the pilot pulse signal m1pre by using the data strobe mask signal DQSM [1] during the period from time t11 to time t 12; and, the memory module PSRAM2 generates the pilot pulse signal m2pre by using the data strobe mask signal DQSM [2] during the period from time t8 to time t 9.

As can be seen from FIG. 18, the master device only receives the pilot pulse signal m2pre generated by the memory module PSRAM2 through the data strobe mask signal line DQSM [2] during the period from time t8 to time t 9. The master device waits until time t11 to time t12 before receiving the pilot pulse signal m1pre generated by the memory module PSRAM1 using the data strobe mask signal line DQSM [1 ]. Accordingly, the master device can know that there is a time difference between the processes of providing the read data by the memory modules PSRAM1 and PSRAM2 based on the pilot pulse signals m1pre and m2pre generated successively (asynchronously). That is, since the master device receives the pilot pulse signal m2pre from the memory module PSRAM2, the master device can determine that the memory module PSRAM2 does not generate an update conflict; the master device receives the pilot pulse signal m1pre from the memory module PSRAM1 later, and can determine that the memory module PSRAM1 has a conflict in update. In this embodiment, the master device is not informed by the memory module PSRAM1 that the memory module PSRAM1 has an update conflict. Therefore, this embodiment does not include the update conflict notification period Trfrp.

In fig. 18, the master device can determine that the memory module PSRAM1 takes a longer time to perform a read operation according to the fact that only the pilot pulse signal m2pre corresponding to the memory module PSRAM2 is generated and the pilot pulse signal m1pre corresponding to the memory module PSRAM1 is not generated during the period from time t8 to time t9, and further determine that the memory module PSRAM1 has an update conflict. Here, during the period from time t5 to time t11, the memory module PSRAM2 has to wait for the refresh read delay rfcLC (e.g., rfcLC ═ LC × 2). The memory module PSRAM1 then issues the pilot pulse signal m1pre from time t11 to time t 12.

Therefore, in fig. 18, it is assumed that the master device pulls the chip select signal CS # high during the system clock cycle Tclk6 to notify the memory module PSRAM2 to wait for the memory module PSRAM1 to complete the update conflict. In practical applications, the master control device may also select to pull up the chip select signal CS # during the system clock periods Tclk7 and Tclk8 as a means for informing the memory module PSRAM2 that the read operation speed needs to be postponed.

Please note that, as shown in fig. 18, the master device determines that the memory module PSRAM1 is collided with a refresh by guiding the pulse signals m1pre and m2pre, although the memory module PSRAM2 is informed of delaying the read operation by pulling up the chip select signal CS # according to the system clock cycle, but the present invention is not limited thereto. Therefore, as mentioned in the other embodiments, the methods of setting the bank busy signal BRBB and the frequency ignore signal ICK may also be modified and applied to the situation where the master determines that the memory module PSRAM1 has an update collision by the pilot pulse signals m1pre and m2 pre.

Incidentally, the master device only selects to pull up the chip selection signal CS # during one of the system clock periods Tclk6, Tclk7 and Tclk8, which may cause the memory module PSRAM2 to mistakenly prepare the master device for forcibly ending the read operation if the period during which the master device pulls up the chip selection signal CS # is longer than the one system clock period Tclk. Therefore, in order to avoid the memory module PSRAM2 from malfunctioning, the embodiment assumes that the master device notifies the memory module PSRAM2 that the read operation period needs to be extended by pulling the chip select signal CS # higher by one system clock period Tclk.

The embodiments described above show that the present invention is very flexible. First, the master device can passively learn that an update conflict is generated inside the memory module PSRAM1 through the report of the memory module PSRAM1 (fig. 8A, 8B, 10, 11, 13, 14, 15, 16); the master control device can actively judge that an update conflict is generated inside the memory module PSRAM1 by comparing and reading the generation time points of the strobe pulse signals m1strb1 and m2strb1 (fig. 17); alternatively, the master device may actively determine that an update conflict occurs inside the memory module PSRAM1 by detecting the pilot pulse signals m1pre and m2pre (fig. 18). In addition, the reporting mode of the memory module PSRAM1 can be further divided into an immediate reporting mode (mode a) and a delayed reporting mode (mode B) according to the reporting time.

Furthermore, the different embodiments described above also illustrate that the memory module PSRAM1 may notify the host device through different types of signal lines if the memory module PSRAM1 has a conflict of update. For example: data strobe mask signals DQSM [1], DQSM [2], bank busy signals BRBBh, BRBBm1, BRBBm2, and chip selection signal CS #, or a waveform combination of the chip selection signal CS #, and a system frequency signal SCLK, etc. In practical applications, the memory module PSRAM1 notifies the master device of the type of signal lines and the control of the waveforms, and the like, and is not limited to the foregoing embodiments.

Further, according to various embodiments, the memory module PSRAM2 may be indirectly aware from the master that the memory module PSRAM1 generates an update conflict; alternatively, memory module PSRAM2 may learn directly from memory module PSRAM1 that there is a conflict in the updates of memory module PSRAM 1.

In the above embodiments, the way that the memory module PSRAM2 indirectly knows from the master device that the memory module PSRAM1 generates the update conflict includes: the main control device issues special read commands m1CMDrd _ sp and m2CMDrd _ sp (fig. 8A), issues extended read commands m1CMDext and m2CMDext (fig. 8B), changes the level of the chip selection signal CS # by the main control device (fig. 13), changes the combination of the chip selection signal CS # and the system clock signal SCLK by the main control device (fig. 14), sets the additionally arranged clock ignore signal lines ICK1 and ICK2 by the main control device (fig. 15), suspends the transmission of the system clock signal SCLK by the main control device (fig. 16), and repeats the read commands m1CMDrtry and m2CMDrtry (fig. 17). In the foregoing embodiments, the manner in which the memory module PSRAM2 may receive the update conflict situation for memory module PSRAM1 directly from memory module PSRAM1 includes: as shown in fig. 9A and 9B, the bank busy signal line BRBB is set in the form of a wired OR (wired OR); and, as shown in fig. 12A and 12B, the chip select signal CS # is set in a wired OR manner.

As can be seen from the foregoing description, the reading method of the present invention can be applied to electronic devices in a rather flexible manner. In practical applications, the manner in which the memory module PSRAM2 indirectly knows from the host device that the memory module PSRAM1 generates the update conflict, and the manner in which the memory module PSRAM2 directly knows from the memory module PSRAM1 that the memory module PSRAM1 generates the update conflict are not limited to the foregoing embodiments.

When the idea of the invention is adopted, the main control device can know whether the memory module generates update conflict or not, and further inform other memory modules in the system that the time point of transmitting and reading data needs to be delayed, and ensure that the main control device can synchronously receive and read data from a plurality of memory modules. The PSRAM technology of the memory module using the PSRAM technology includes, but is not limited to, OctaRAM, HyperRAM, xcela PSRAM, and the like, and the transmission protocol adopted by the PSRAM technology may be a Serial Peripheral Interface (SPI for short), a double-Serial Peripheral Interface (Dual-SPI), a quad-Serial Peripheral Interface (QSPI), and the like. In addition, although the waveform diagram of the present invention assumes that one read delay count LC corresponds to three times of the system clock period (LC-3 × Tclk), the practical application is not limited thereto.

It should be noted that although the electronic device is assumed to include only two memory modules PSRAM1 and PSRAM2 in the foregoing description, the practical application of the present invention is not limited thereto. For example, an electronic device may include four or eight memory modules. Or, the situation that a plurality of memory modules contained in the electronic device generate conflict of updating in turn occurs. Therefore, the reading method can still be based on a similar control manner, and after all the memory modules with update conflicts complete the update conflicts, all the memory modules are controlled to synchronously transmit the read data. The foregoing embodiments may be applied to these different types of electronic devices after modification.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device for electrical connection to a host device, wherein the host device performs a read operation on the memory device during a read operation, and the memory device comprises:

a first memory module that generates an update conflict during the read operation; and the number of the first and second groups,

a second memory module, wherein,

the first memory module and the second memory module respectively receive a first reading instruction and a second reading instruction transmitted by the main control device during a reading instruction transmission period;

the first memory module and the second memory module respectively receive a first memory address and a second memory address during an address transmission period at the same time, wherein the read command transmission period is earlier than the address transmission period; and the number of the first and second groups,

after a synchronous data preparation period, the first memory module and the second memory module respectively transmit a first synchronous read data and a second synchronous read data to the master control device at the same time in the synchronous data read period, wherein the synchronous data preparation period is greater than a preset read delay.

2. The memory device of claim 1,

the main control device informs the second memory module that the reading operation needs to be executed in a special data synchronization mode; or

The first memory module informs the second memory module that the read operation should be performed in the special data synchronization manner.

3. The memory device of claim 1,

the first memory module reports the update conflict to the master device before the read command transmission period begins; or

The first memory module reports the conflict situation to the master device during the address transmission period.

4. The memory device of claim 1, wherein the first memory module reports the conflict between updates to the host device via one or a combination of a chip select signal line, a data strobe mask signal line, a dedicated signal line, a system clock signal line, and a clock ignore signal line.

5. The memory device of claim 1, wherein the second memory module transmits a discard data during the synchronous data preparation period, wherein the contents of the discard data are the same as the contents of the second synchronous read data.

6. The memory device of claim 1,

the synchronous data preparation period is less than a refresh read latency, wherein the read operation period comprises:

and a chip selecting period for selecting the first memory module and the second memory module, wherein the chip selecting period includes a setting period, the read command transmitting period, the address transmitting period, the synchronous data preparing period and a part of the synchronous data reading period.

7. The memory device of claim 1, wherein the synchronous data preparation period is greater than an update read latency, wherein the read operation period comprises:

a first chip select period for selecting the first memory module and the second memory module, wherein the first chip select period includes a setup period, a read command transfer period, an address transfer period, and a part of the synchronous data preparation period;

selecting a chip spacing;

a second chip selection period for selecting the first memory module and the second memory module, wherein the second chip selection period comprises an instruction repeat transmission period, another part of the synchronous data preparation period and a part of the synchronous data reading period; and

an end period, wherein the end period includes another part of the synchronous data reading period.

8. The memory device of claim 7,

the first memory module transmits a first discard data during the synchronous data preparation period, and the second memory module transmits a second discard data during the synchronous data preparation period,

the contents of the first discarded data are the same as those of the first synchronous read data, and the contents of the second discarded data are the same as those of the second synchronous read data.

9. The memory device of claim 8,

the first chip select period includes the read command transmission period and the address transmission period, and

the second chip select period includes a command repeat transmission period, the synchronous data preparing period and the synchronous data reading period.

10. The memory device of claim 1,

the master device determines that the first memory module generates the update conflict during the preparation period of the synchronous data, and notifies the second memory module that the read operation needs to be executed in a special data synchronization manner during the preparation period of the synchronous data.

11. The memory device of claim 10,

the first memory module sends a first pilot pulse signal in response to the read operation, and the second memory module sends a second pilot pulse signal in response to the read operation,

the master device determines that the first memory module generates the update conflict according to the comparison between the first pilot pulse signal and the second pilot pulse signal.

12. The memory device of claim 1, wherein the read operation period comprises the read command transfer period, the address transfer period, the synchronous data preparation period, and the synchronous data read period.

13. An electronic device, comprising:

a memory device, comprising:

a first memory module that generates an update conflict during a read operation; and

a second memory module; and

a main control device electrically connected to the first memory module and the second memory module, wherein the main control device simultaneously executes a read operation on the first memory module and the second memory module during the read operation period,

the first memory module and the second memory module simultaneously receive a reading instruction transmitted by the main control device during a reading instruction transmission period;

the first memory module and the second memory module respectively receive a first memory address and a second memory address during an address transmission period at the same time, wherein the read command transmission period is earlier than the address transmission period; and

14. A reading method applied to an electronic device, wherein the electronic device comprises a main control device, a first memory module and a second memory module, wherein the main control device simultaneously executes a reading operation on the first memory module and the second memory module in a reading operation period, the first memory module generates an update conflict in the reading operation period, and the reading method comprises the following steps: