KR20070111062A - Memory module and memory system comprising the same - Google Patents

Abstract

A memory module and a memory system comprising the same are provided to simplify an interface structure by installing interface devices instead of installing the interface devices in memory devices. A memory module includes a plurality of memory groups for receiving packet commands and generating read data. Each of the memory groups includes an interface unit(IF) and two or more first memories(m1,m2). The interface unit generates a command signal and an address according to a packet command, generates write data included in the packet command in a write operation, transmits the write data to write/read data lines, receives read data to be transmitted to the write/read data lines in a read operation, and transmits the read data through the read data lines. The two or more first memories(m1,m2) receive the command signal and the address, receives the write data in the write operation, and transmits the read data to the write/read data lines in the read operation.

Description

Memory module and memory system comprising the same

1 is a block diagram showing a configuration of an example of a conventional memory system.

Fig. 2 is a block diagram showing the configuration of another example of a conventional memory system.

Fig. 3 is a block diagram showing the construction of the first embodiment of the memory system provided with the memory module of the present invention.

FIG. 4 is a block diagram showing the configuration of an embodiment of the interface device shown in FIG.

FIG. 5 shows the format of a packet command of the memory system shown in FIG.

6A and 6B are operation timing diagrams for explaining operations during write and read operations of the interface device of the memory system shown in FIG.

Fig. 7 is a block diagram showing the construction of a second embodiment of a memory system having a memory module of the present invention.

FIG. 8 is a block diagram showing a configuration of an embodiment of an interface device of the memory system shown in FIG.

9A and 9B are operation timing diagrams for explaining operations during write and read operations of the interface device of the memory system shown in Fig. 7, respectively.

Fig. 10 shows the construction of the third embodiment of the memory system provided with the memory module of the present invention.

Fig. 11 shows the construction of the fourth embodiment of the memory system including the memory module of the present invention.

Fig. 12 shows the construction of the fifth embodiment of the memory system including the memory module of the present invention.

FIG. 13 is a block diagram showing the construction of an embodiment of the interface device IF 'shown in FIG.

Fig. 14 shows the construction of the sixth embodiment of the memory system including the memory module of the present invention.

Figure 15 shows a configuration of an embodiment of a memory of the memory module of the present invention.

The present invention relates to a memory module, and more particularly, to a memory module for receiving a packet command and a memory system having the same.

The memory system includes a memory controller and a memory module, and a conventional memory module for receiving a packet command includes a plurality of memories, each of the plurality of memories receiving a packet command including an instruction, an address, and write data. A write operation is performed, and a read operation is performed by receiving a packet command including an instruction and an address.

FIG. 1 is a block diagram showing an example of a conventional memory system, which is composed of a memory controller 10 and a memory module 20, and the memory module 20 includes n groups of memory devices MG1 to MGn. Each of the memory devices MG1 to MGn includes a first memory M1 and a second memory M2. The first memory M1 of each of the memory devices MG1 to MGn includes a repeater R1, and the second memory M2 of each of the memory devices MG1 to MGn includes a repeater R2. It is.

In Fig. 1, c / a / wd1 and c / a / wd2 represent control signal lines, and rd1 and rd2 represent read data lines, respectively.

A data transfer method of the memory system shown in FIG. 1 will now be described.

When the memory controller 10 applies a packet command to the memory module 20 through the control signal lines c / a / wd1, the first memory M1 receives the packet command and returns the packet command to the repeater R1. Through the control signal lines (c / a / wd2) is transmitted to the second memory (M2). If the first memory M1 interprets the packet command and stores the write data included in the packet command if the write command is written to the first memory M1, and interprets the packet command, the first memory M1 reads the read command to the first memory M1. The first memory M1 performs a read operation to transfer read data to the read data lines rd1. The second memory M2 interprets the packet command applied through the control signal lines c / a / wd2, and stores the write data included in the packet command if the write command is made to the second memory M2. When the command is interpreted and the read command is applied to the first memory M1, the read data applied through the read data lines rd1 is transferred to the read data lines rd2 through the repeater R2, and the second memory ( If the read command is applied to M2, the second memory M2 performs a read operation to transmit read data to the read data lines rd2.

The first and second memories M1 and M2 of the memory system shown in FIG. 1 should each have a packet command decoder (not shown) and a repeater for interpreting the packet command. In addition, since the first and second memories M1 and M2 of the memory system shown in FIG. 1 are directly connected to the memory controller 10 to perform an operation, when the frequency of the system clock signal is increased, the first and second memories are controlled. The operating speeds of the M1 and M2 must also be fast, so that each of the first and second memories M1 and M2 of the memory system shown in FIG. 1 should have an additional configuration for interfacing with the memory controller 10. do.

Fig. 2 is a block diagram showing the configuration of another example of a conventional memory system, which is composed of a memory controller 10 and a memory module 20 ', which is a buffer 20-1 and n memories. It consists of (M1-Mn). (n / 2) memories M1 to M (n / 2) are disposed on one side of the buffer 20-1, and the remaining (n / 2) memories M (n / 2 + 1) to Mn) is disposed on the other side of the buffer 20-1.

2, c / a / wd denotes control signal lines, rd denotes read data lines, c denotes command signal lines, a denotes address signal lines, and w / r1 to w / rn denote write / lead data lines. Represent each.

The function of each of the blocks shown in FIG. 2 will be described below.

The memory controller 10 applies a command, an address, and a write command or a packet command including a command and an address through the control signal lines c / a / wd and read data through the control signal lines rd. Receive The buffer 20-1 receives and decodes a packet command to transmit a command, an address, and write data to each of the memories M1 to Mn, and receives read data transmitted from each of the memories M1 to Mn to store the memory. To the controller 10. The buffer 20-1 does not generate data skew according to the length of the write / read data lines w / r1 to w / rn when transmitting / receiving each of the memories M1 to Mn and write / read data. Data must be transmitted / received with a predetermined time difference so that the signal is processed to match the signal transmission rate when the signal transmission rate with the memory controller 10 and the signal transmission rates with the memories M1 to Mn are different. Must transmit and receive signals.

Therefore, in the conventional memory module shown in FIG. 2, since one buffer 20-1 has to perform an interface between the memory controller 10 and n memories M1 to Mn, There was a problem that the function was complicated. That is, there is a problem that the configuration for the interface is complicated.

An object of the present invention is to provide a memory module having a single configuration for an interface with an external device and a simple configuration for an interface.

Another object of the present invention is to provide a memory system having a memory module for achieving the above object.

A first aspect of the memory module of the present invention for achieving the above object includes a plurality of groups of memory sections for receiving packet instructions for each of a plurality of groups and generating read data for each of the plurality of groups, Each memory unit of the group inputs the packet command to generate a command signal and an address, generates write data included in the packet command during a write operation, transmits the write data to write / read data lines, An interface device which receives read data transmitted to the write / read data lines in a read operation and transmits the read data through the read data lines, and commonly receives the command signal and the address, and writes the write data in the write operation. The read / read data is received when the read data is received. And at least two first memories for transmitting to data lines.

A second aspect of the memory module of the present invention for achieving the above object is provided with a plurality of groups of memory units for receiving a packet command of each of a plurality of groups and generating read data for each of the plurality of groups, wherein the plurality of groups Each of the memory units includes a first memory, inputs the packet command to generate a command signal and an address, and generates first and second write data included in the packet command during a write operation. Store write data in the first memory, transmit the second write data to the write / read data lines, and in the read operation, the first memory generates first read data, and write / read data An interface device receiving second lead data transmitted through lines and outputting the first and second lead data to read data lines; And receiving the command signal and the address, receiving the second write data transmitted to the write / lead data lines in the write operation, and writing the second read data to the write / read in the read operation. And a memory device for transmitting data lines.

A third aspect of the memory module of the present invention for achieving the above object comprises a plurality of groups of memory sections for receiving a packet command of each of a plurality of groups and generating read data for each of the plurality of groups, wherein the plurality of groups Each of the memory units includes a first memory, inputs the packet command to generate a command signal and an address, and stores the write data included in the packet command in the first memory or writes the write / write command during a write operation. The read data lines are transmitted to the read data lines, and the read data generated by the first memory in the read operation is output to the read data lines, or the read data transmitted through the write / read data lines is received. Interface device for outputting the data to the terminal, and receiving the command signal and the address in common, And a memory device configured to receive the write data transmitted to the write / read data lines in a write operation, and to transmit the read data to the write / read data lines in the read operation. .

A first aspect of the memory system of the present invention for achieving the above another object is a memory controller for transmitting a plurality of groups of packet commands through the control signal lines, and receives a plurality of groups of read data through the read data lines, and And a memory module including a plurality of groups of memory units for receiving packet instructions of each of the plurality of groups and generating read data for each of the plurality of groups, wherein each of the plurality of groups of memory units executes the packet instructions. Generate a command signal and an address, generate write data included in the packet command during a write operation, transmit the write data to write / lead data lines, and write the read / lead data line during a read operation. Receive read data sent to the An interface device for transmitting, and two for receiving the command signal and the address in common, receiving the write data during the write operation, and transmitting the read data to the write / lead data lines during the read operation. The first memories may be provided.

A second aspect of the memory system of the present invention for achieving the above another object is a memory controller for transmitting a plurality of groups of packet commands through the control signal lines, and receives a plurality of groups of read data through the read data lines, and And a memory module including a plurality of groups of memory units for receiving a packet command of each of the plurality of groups and generating read data for each of the plurality of groups, wherein each of the plurality of groups of memory units includes a first memory. And generating a command signal and an address by inputting the packet command, generating first and second write data included in the packet command during a write operation, and storing the first write data in the first memory. Transmit the second write data to the write / lead data lines, and during the read operation, An interface device for generating a first read data, receiving a second read data transmitted through the write / read data lines, and outputting the first and second read data to read data lines; Receive a command signal and the address, receive the second write data transmitted to the write / read data lines in the write operation, and receive the second read data in the write / read data line during the read operation. And a memory device for transmitting to the network.

A third aspect of the memory system of the present invention for achieving the above another object is a memory controller for transmitting a plurality of groups of packet commands through the control signal lines, and receives a plurality of groups of read data through the read data lines, and And a memory module including a plurality of groups of memory units for receiving a packet command of each of the plurality of groups and generating read data for each of the plurality of groups, wherein each of the plurality of groups of memory units includes a first memory. And generate a command signal and an address by inputting the packet command, and store the write data included in the packet command in the first memory or transmit the read / write data lines to the write / read data lines during a write operation. Read data generated by the first memory in operation to the read data lines; Or an interface device for receiving read data transmitted through the write / read data lines and outputting the read data to the read data lines, and receiving the command signal and the address in common, and performing the write / read operation during the write operation. And a memory device configured to receive the write data transmitted to data lines and to transmit the read data to the write / read data lines during the read operation.

The interface device of the memory system receives the packet command transmitted at the first operating frequency from the memory controller during the write operation, transmits the write data included in the packet command at the second operating frequency, and Receive read data transmitted from the memory device at the second operating frequency during a read operation, transmit the read data to the memory control unit at a first operating frequency, and the first operating frequency is greater than the second operating frequency. It is characterized by high.

The read data lines are composed of differential data line pairs for transmitting differential data, and the write / lead data lines are composed of single data lines for transmitting single data.

Hereinafter, referring to the accompanying drawings, a memory module and a memory system having the same will be described.

Fig. 3 is a block diagram showing the construction of a first embodiment of a memory system with a memory module of the present invention, and is comprised of a memory controller 10 and a memory module 200. As shown in FIG. The memory module 200 includes n groups of memory devices MG1 to MGn, and each of the n groups of memory devices MG1 to MGn includes an interface device IF, a first memory m1 and a first memory device. It consists of two memories (m2).

In Fig. 3, c / a / wd denotes control signal lines, rd denotes read data lines, cs denotes chip select signal lines, c denotes command signal lines, a denotes address signal lines, and wd / rd denotes write / write. Each of the read data lines is shown.

The function of each of the blocks shown in FIG. 3 will be described below.

The interface device IF receives a packet command applied through the control signal lines c / a / wd, interprets the packet command to convert the chip select signal into a chip select signal line cs, and the command signal is a command signal. The address to the lines c is transmitted to the address signal lines a, the write data is transmitted to the write / read data lines wd / rd, and the write data is transmitted through the write / read data lines wd / rd. The read data is received and transmitted to the read data lines rd. The first memory m1 is enabled in response to the chip select signal and is in an operable state. When the command signal is a write command, the first memory m1 is transmitted through the write / read data lines wd / rd to memory cells corresponding to the address. The write data is stored, and in the read command, the read data stored in the memory cells corresponding to the address is transferred to the write / read data lines wd / rd. The second memory m2 is enabled and operated in response to the chip select signal. When the command signal is a write command, the second memory m2 is transmitted through the write / read data lines wd / rd to memory cells corresponding to the address. The write data is stored, and in the read command, the read data stored in the memory cells corresponding to the address is transferred to the write / read data lines wd / rd.

In the memory system illustrated in FIG. 2, since the write / read data lines wd / rd are shared by the first memory m1 and the second memory m2, the write / read data lines (during read and read operations) may be used. In order to prevent data collision in wd / rd), the first memory m1 and the second memory m2 are preferably designed to have different write latency and read latency. For example, if the burst length of the first memory m1 and the second memory m2 is set to 4 and the period of the clock signal corresponding to the burst length is two cycles, the write of the first memory m1 is performed. When the latency is set to 2, the write latency of the second memory m2 is set to 4, and when the read latency of the first memory m1 is set to 6, the read latency of the second memory m2 is set to 8. It is desirable to be. The write latency is a period of a clock signal from when the write command is applied to the first memory m1 and the second memory m2 until the write data is applied to the first memory m1 and the second memory m2. The read latency is a period of a clock signal from when the read command is applied to the first memory m1 and the second memory m2 until the read data is output from the first memory m1 and the second memory m2. In the case where the burst length is 8, the period of the clock signal corresponding to the burst length is 8 when the first memory m1 and the second memory m2 operate at a single data rate, and at a double data rate. 4 if in operation.

The memory system shown in Fig. 3 does not need to include the interface device IF in each of the memories m1 and m2, and the interface device IF is provided for each of the n groups of memory devices MG1 to MGn. The function of the interface device IF is simplified to simplify the configuration of the interface device IF.

Fig. 4 is a block diagram showing the configuration of the embodiment of the interface device shown in Fig. 3, which includes serial and parallel converters 30 and 44, a packet decoder 32, a control signal generator 34, a clock signal generator 36, and a bottle. Serial converters 38, 42, and read data storage 40.

The function of each of the blocks shown in FIG. 4 is as follows.

The clock signal generator 36 inputs the reference clock signal RCLK to generate i clock signals CLK1 to CLKi having the same frequency and different phase differences. One clock signal CLK1 among the i clock signals CLK1 to CLKi is generated in synchronization with the reference clock signal RCLK. The reference clock signal RCLK may be applied from the memory controller 10 or may be applied from an external separate clock generator (not shown). The serial-to-parallel converter 30 generates parallel control signals by converting packet commands applied in series through each of the control signal terminals (not shown) in parallel in response to the i clock signals CLK1 to CLKi. The packet decoder 32 interprets the parallel control signal in response to one clock signal CLK1 among the clock signals CLK1 to CLKi, thereby generating a command signal com, an address signal add, a chip select signal ce, and the like. Generates parallel data WD1 to WDk or generates a command signal com, an address signal add, and a chip select signal ce, and decodes the command signal com to write the command WE and the read command. RE). The packet decoder 32 continuously outputs two groups of parallel data WD1 to WDk in response to the clock signal CLK1 during the write operation, and outputs the first memory m1 (or the second memory m2). First output the first group of parallel data WD1 to WDk for storage, and after a delay of a clock signal corresponding to the burst length j after the second memory m2 (or the first memory m1). The second group of parallel data WD1 to WDk for storage is output, and the first group of parallel data WD1 to WDk and the second group of parallel data WD1 to WDk are continuously output. Each of the parallel data WD1 to WDk is composed of j bits of parallel data corresponding to the burst length j. The control signal generator 34 outputs the command signal com as the command signal COM in response to the clock signal CLK1, outputs the address signal add as the address signal ADD, and selects the chip select signal ce. ) Is generated as a chip select signal (CS). The parallel-to-serial converter 42 writes parallel data WD1 to WDk of j bits of the first group in response to the rising edge and the falling edge of the write command WE and the clock signal CLK1, and writes the data to the write data DQ1 to DQk. In order to convert the signal into serial, the data is transmitted to the write / read data lines wd / rd through k data input / output terminals (not shown). The first group of write data DQ1 to DQk output from the parallel-serial converter 42 is transferred to the first memory m1 and the second group of write data DQ1 to DQk output from the parallel-serial converter 42. ) Is transferred to the second memory m2. The serial-to-parallel converter 44 converts each of the two groups of read data DQ1 to DQk sequentially applied in series in response to the read command RE and the clock signal CLK1 in parallel. Each of the k read data DQ1 to DQk of the first and second groups is j bits of serial data, and each of k parallel data output from the serial-to-parallel converter 44 is composed of j bits. The read data storage unit 40 continuously stores and outputs first and second groups of parallel read data output from the serial-to-parallel converter 44 in response to the read command RE and the clock signal CLK1. Each of the (k / 2) parallel read data output from the read data storage unit 40 is composed of 2j bits, and 2j bits of data are continuously output. The parallel-to-serial converter 34 parallelly outputs the first and second groups of 2j bits in succession from the read data storage unit 40 in response to the read command RD and the i clock signals CLK1 to CLKi. The read data is serially converted and transmitted to the read data lines rd through (k / 2) data output terminals (not shown). Each of the (k / 2) read data MDQ1 to MDQ (k / 2) output from the parallel-serial converter 34 is 4j bits of serial data.

FIG. 5 shows the format of a packet command of the memory system shown in FIG.

In Fig. 5, A represents an active command format, where the active command format consists of a chip select signal CS, a command signal COM, and a row address RADD, and the command signal COM is an inverted chip select signal. , An inverted write enable signal, an inverted column address strobe signal, and an inverted row address strobe signal, in this case, four bits of data. The row address signal is a signal for selecting a word line of the memory cell array of the first or second memory. When the memory cell array is configured of a plurality of banks, the row address signal is applied together with the row address signal.

B denotes a write command format. The write command format includes three packet data, and the first packet data includes a chip select signal CS, a command signal COM, and a column address signal CADD. The second packet data and the third packet data include a first group of write data for storage in the first memory m1 and a second group of write data for storage in the second memory m2.

C denotes a read command format. The read command format is composed of one packet data like the active command format, and consists of a chip select signal CS, a command signal COM, and a column address signal CADD.

When the write command format of B is applied, write data is written to a memory cell connected between the selected word line and the selected bit line of the memory cell array. When the read command format of C is applied, the selected word line and the selected word line of the memory cell array are selected. Data stored in memory cells connected between bit lines is read.

6A and 6B are operation timing diagrams for explaining operations during write and read operations of the interface device of the memory system shown in FIG. 3, respectively, in which the first memory m1 and the second memory m2 have a double data rate. Data is inputted and outputted, the write latency of the first memory m1 is 0, the read latency is 3, the period of the clock signal corresponding to the burst length is set to 2, and the write latency of the second memory m2 is 2; Indicates the operation when the read latency is set to 5. FIG.

As shown in FIG. 6A, when the packet command B of FIG. 5 is applied, the interface device IF responds to the packet command B in response to four clock signals CLK1 to CLK4 having the same frequency and having a phase difference of 90 degrees. ) Is inputted and interpreted and the chip select signal CS, the command signal COM, the column address CADD, the first write data m1 WD, and the second write data m2 WD in response to the clock signal CLK1. ) The second write data m2 WD is output after the command signal COM is output and is delayed by a period of two clock signals corresponding to the burst length.

As shown in Fig. 6B, when the packet command C of Fig. 5 is applied, the interface device IF inputs the packet command C and responds to the clock signal CLK1 to the chip select signal CS and the command signal COM. ) And column address (CADD). The first memory m1 outputs the first group of read data m1 RD after a delay of 5 clock cycles corresponding to the read latency in response to the command signal COM, and the second memory m2 outputs the command signal ( In response to COM), the second group of read data m2 RD is output after a delay of 7 clock cycles corresponding to the read latency. The interface device IF includes a first group of four bits of serial read data m1 RD and a second group of four bits of serial read data applied serially through each of k data input / output terminals (not shown). By converting each of the m2 RDs in parallel, the serial read data of 8 bits of the first group through each of the (k / 2) data output terminals (not shown) in response to the clock signals CLK1 to CLK4. m1 RD ') and serial read data m2 RD' of 8 bits of the second group are continuously output.

If the interface device shown in Fig. 4 transmits and receives data with the memory control unit 10 at an operating frequency of 3.2 GHz and transmits and receives data with the first memory m1 and the second memory m2 at an operating frequency of 800 MHz. Assuming that the first memory m1 and the second memory m2 input and output data at a double data rate, the clock signal generator 36 of the interface device has the same frequency of 800 MHz and a phase difference of 90 degrees. Four clock signals CLK1 to CLK4 may be generated and the 800 MHz clock signal CLK1 synchronized with the reference clock signal RCLK may be transmitted to the first memory m1 and the second memory m2. .

As can be seen from the timing diagram of FIG. 6A, the interface device shown in FIG. 4 converts data transmitted at high speed from the memory controller 10 to low speed, and transmits the data to the first memory m1 and the second memory m2. It is possible to convert the data transmitted from the first memory m1 and the second memory m2 at low speed to high speed and transmit the same to the memory controller 10.

FIG. 7 is a block diagram showing the construction of a second embodiment of a memory system having a memory module of the present invention, wherein the memory module 200 'shown in FIG. 7 is an interface device IF of the memory module 200 shown in FIG. ) And the write / read data lines (wd / rd) are connected between the first memory m1 and the write / read data lines (wd / rd) between the interface device IF and the second memory m2. Is connected, the first write / lead data lines wd1 / rd1 are connected between the interface device IF and the first memory m1, and the interface device IF and the second memory m2 are connected to each other. The second write / lead data lines wd2 / rd2 are connected to each other.

The function of each of the blocks shown in FIG. 7 will be described below.

The interface device IF receives a packet command applied through the control signal lines c / a / wd, interprets the packet command to convert the chip select signal into a chip select signal line cs, and the command signal is a command signal. The address to the lines c is transmitted to the address signal lines a, the write data of the first group is transmitted to the first write / lead data lines wd1 / rd1, and the write data of the second group is the second. Send to the write / read data lines wd2 / rd2 and receive read data transmitted through the first write / lead data lines wd1 / rd1 and the second write / lead data lines wd2 / rd2. Transfer to the read data lines rd. The first memory m1 is enabled and operated in response to the chip select signal. When the command signal is a write command, the first memory m1 is connected to the memory cells corresponding to the address through the first write / read data lines wd1 / rd1. The write data of the first group to be transmitted is stored, and if the read command is performed, the read data of the first group stored in the memory cells corresponding to the address is transmitted to the first write / read data lines wd1 / rd1. The second memory m2 is enabled and operated in response to the chip select signal. When the command signal is a write command, the second memory m2 is connected to the memory cells corresponding to the address through the second write / read data lines wd2 / rd2. The second group of write data is stored, and if the read command is performed, the second group of read data stored in the memory cells corresponding to the address is transmitted to the second write / read data lines wd2 / rd2.

In the memory system shown in FIG. 7, since the first write / read data lines wd1 / rd1 and the first write / lead data lines wd2 / rd2 are separated, the first memory m1 and the second memory are separated. (m2) is preferably designed to have the same light latency, read latency, and burst length.

The memory system shown in Fig. 7 does not have to include the interface device IF in each of the memories m1 and m2, and the interface device IF is provided for each of n groups of memory devices MG1 to MGn. The function of the interface device IF is simplified to simplify the configuration of the interface device IF.

Fig. 8 is a block diagram showing the configuration of an embodiment of the interface device of the memory system shown in Fig. 7, replacing the packet decoder 32 with the packet decoder 32 'and the parallel-to-serial converter 42 to the parallel-to-serial converter 42. The configuration is the same as that of FIG. 4 except that the configuration is replaced with ').

The functions of blocks having the same number as the blocks of FIG. 4 among the blocks shown in FIG. 8 will be referred to the description of the functions of FIG. 4, and only the functions of blocks having other numbers will be described herein.

The packet decoder 32 'inputs a parallel control signal in response to one of the clock signals CLK1 to CLKi to receive a command signal com, an address signal add, and a chip select signal ce. To generate the first group of parallel data WD11 to WD1 (k / 2) and the second group of parallel data WD21 to WD2 (k / 2), or to generate a command signal com, an address signal add, and The chip select signal ce is generated and the command signal com is decoded to generate the write command WE and the read command RE. Each of the first group of parallel data WD11 to WD1 (k / 2) and the second group of parallel data WD21 to WD2 (k / 2) is composed of j bits corresponding to the burst length j. 42 ′ converts each of the first group of parallel data WD11 to WD1 (k / 2) in series in response to the write command WE and the clock signal CLK1 to write the data of the first group of write data DQ1 to DQ. (k / 2)) respectively transmits to the first write / lead data lines wd1 / rd1 through (k / 2) data input / output terminals (not shown), and the second group of parallel data WD21 to WD2 (k / 2)) is converted in series to convert each of the second group of write data DQ (k / 2 + 1) to DQk through (k / 2) data input / output terminals (not shown). The first and second groups of write data DQ1 to DQk output from the parallel-to-serial converter 42 'are j-bit serial data.

The memories of the memory module of the memory system shown in FIG. 7 are reduced by one half as compared with the number of data input / output terminals of the memories shown in FIG. 3. In addition, in the first memory m1 and the second memory m2 shown in FIG. 3, the write latency and the read latency are set such that the write data and the read data are inputted and outputted with a time difference corresponding to the clock period corresponding to the burst length. In the first memory m1 and the second memory m2 shown in FIG. 5, the write latency and the read latency may be set such that the write data and the read data are simultaneously input and output.

The format of the packet command of the memory system shown in FIG. 7 is configured in the same way as that of the packet command of the memory system shown in FIG.

9A and 9B are operation timing diagrams for explaining operations during write and read operations of the interface device of the memory system shown in FIG. 7, respectively, in which the first memory m1 and the second memory m2 have a double data rate. When data is inputted and outputted, the write latency of the first memory m1 and the second memory m2 is 0, the read latency is 3, the burst length is 8, and the clock period corresponding to the burst length is set to 4. It represents.

As shown in FIG. 9A, when the packet command B of FIG. 5 is applied, the interface device IF inputs and decodes the packet command B in response to the four clock signals CLK1 to CLK4 and decodes the clock signal CLK1. ), The chip select signal CS, the command signal COM, the column address CADD, the serial write data m1 WD of the first group of 8 bits, and the serial write of 8 bits of the second group, respectively. Data m2 WD is output at the same time.

As shown in FIG. 9B, when the packet command C of FIG. 5 is applied, the interface device IF inputs and interprets the packet command C, and responds to the clock select signal CSK and the command signal in response to the clock signal CLK1. Outputs (COM) and column address (CADD). The first memory m1 and the second memory m2 each have the serial read data m1 RD and the first group of j bits after a delay of 5 clock cycles corresponding to the read latency in response to the command signal COM. Outputs serial read data (m2 RD) of two groups of j bits. The interface device IF includes a first group of read data m1 RD and a second group of read data m2, each of which is applied in series through (k / 2) data input / output terminals (not shown). RD) is converted in parallel to read the first group of 8 bits of read data (m1 RD ') through (k / 2) data output terminals (not shown) in response to clock signals CLK1 to CLK4. And serially output read data m2 RD 'of 8 bits of the second group.

3 and 7 show a configuration in a case where write and read operations to the first memory m1 and the second memory m2 are performed in common.

FIG. 10 shows a configuration of a third embodiment of a memory system having a memory module of the present invention, wherein the memory module 300 shown in FIG. 10 is a memory in each of the plurality of groups of memory devices MG1 to MGn of FIG. Each of the m3 and m4 is additionally provided, and each of the interface device IF, the first memory m1 and the second memory m2 of each of the plurality of groups of memory devices MG1 to MGn is a first chip. Commonly connected to the selection signal line cs1, the interface device IF, the third memory m3 and the fourth memory m4 are commonly connected to the second chip selection signal line cs2, and the interface device IF. And the first to fourth memories m1 to m4 are commonly connected to the command signal lines c, the address signal lines a, and the write / read data lines wd / rd.

The function of each of the blocks shown in FIG. 10 will be described below.

The interface device IF receives a packet command applied through the control signal lines c / a / wd, interprets the packet command, and converts the first chip select signal into the first chip select signal line cs1. The two-chip select signal is applied to the second chip select signal line cs2, and the command signal, the address signal, and the write data of the first and second groups (or the write data of the third and fourth groups) are respectively commanded. Transmit to signal lines c, address signal lines a, and write / read data lines wd / rd. Each of the first and second memories m1 and m2 is enabled and operable in response to the first chip selection signal. If the command signal is a write command, the write / read data lines may be provided in memory cells corresponding to the address. Stores the first group of write data transmitted through (wd / rd), and transmits the first group of read data stored in the memory cells corresponding to the address to the write / read data lines (wd / rd) when the read command is performed. do. The second memory m2 is enabled and operated in response to the first chip selection signal. When the command signal is a write command, the second memory m2 is connected to the memory cells corresponding to the address through the write / read data lines wd / rd. The second group of write data is stored, and in the case of a read command, the second group of read data stored in memory cells corresponding to the address is transmitted to the write / read data lines wd / rd. The third memory m3 is enabled and operated in response to the second chip selection signal. When the command signal is a write command, the third memory m3 is connected to the memory cells corresponding to the address through the write / read data lines wd / rd. The third group of write data is stored, and if the read command is performed, the third group of read data stored in the memory cells corresponding to the address is transmitted to the write / read data lines wd / rd. The fourth memory m4 is enabled and operated in response to the second chip selection signal. When the command signal is a write command, the fourth memory m4 is connected to the memory cells corresponding to the address through the write / read data lines wd / rd. The fourth group of write data is stored, and in the case of a read command, the fourth group of read data stored in the memory cells corresponding to the address is transmitted to the write / read data lines wd / rd.

In the memory system shown in FIG. 10, the first and second memories m1 and m2 perform a write and read operation in common in response to the first chip select signal, and the third and the third chips in response to the second chip select signal. Four memories m3 and m4 perform write and read operations in common. That is, the memory system shown in Fig. 10 can write and read data to two memories of each of a plurality of groups of memory devices.

The first and second memories m1 and m2 and the third and fourth memories m3 and m4 of the memory module illustrated in FIG. 10 may correspond to the first and second memories m1 and m2 illustrated in FIG. It is preferable that the light latency and the read latency be set in the same manner.

Although not shown, the interface device IF of the memory module 300 shown in FIG. 10 can be configured similarly to the interface device shown in FIG. 3, and only the first chip select signal and the second chip select signal in the packet command. Is transmitted, and the packet decoder may generate the first chip selection signal and the second chip selection signal.

FIG. 11 shows a configuration of a fourth embodiment of a memory system including a memory module of the present invention. In the memory module 300 'shown in FIG. 11, the first write / lead data lines wd1 / rd1 are interface devices. (IF) and first and second memories m1 and m2 are connected in common, and the second write / lead data lines wd2 / rd2 are connected to the interface device IF and the third and fourth memories ( m3, m4) is the same as the configuration of FIG.

In the memory system illustrated in FIG. 11, similarly to the memory system illustrated in FIG. 10, the first and second memories m1 and m2 perform write and read operations in common in response to the first chip selection signal, and select the second chip. In response to the signal, the third and fourth memories m3 and m4 perform a write and read operation in common.

The first and second memories m1 and m2 and the third and fourth memories m3 and m4 of the memory module shown in FIG. 11 are connected to the first and second memories m1 and m2 shown in FIG. Similarly, it is preferable that the light latency and the read latency are set equally. Accordingly, during the write operation, the first memory m1 (third memory m3) and the second memory m2 (fourth memory m4) simultaneously hold the first write / read data lines wd1 / rd1. And stores data transmitted to each of the second write / lead data lines rd2 / wd2, and at the read operation, the first memory m1 (third memory m3) and the second memory m2 (second). Four memories m4 simultaneously output data to each of the first write / lead data lines wd1 / rd1 and the second write / lead data lines rd2 / wd2.

Although not shown, the interface device IF shown in Fig. 11 can be configured similarly to the interface device shown in Fig. 8, and only the first chip selection signal and the second chip selection signal are included in the packet command and transmitted. The packet decoder may be configured to generate the first chip select signal and the second chip select signal.

FIG. 12 shows a configuration of a fifth embodiment of a memory system having a memory module of the present invention. The memory module 400 of FIG. 12 replaces the interface device IF of FIG. 3 with an interface device IF '. The configuration is the same as that of the interface device IF shown in FIG.

The interface device IF 'shown in Fig. 12 is not only an interface function between the memory controller 10 and the first memory m1 and the second memory m2, but also with the first memory m1 and the second memory m2. Similarly, it stores data.

In FIG. 12, the first memory m1 and the second memory m2 are separately configured, but the first memory m1 and the second memory m2 may be configured as one memory device.

FIG. 13 is a block diagram showing the configuration of the embodiment of the interface device IF 'shown in FIG. 12. The packet decoder 32 of the interface device shown in FIG. 4 is replaced with the packet decoder 32', and the memory 60 is shown in FIG. And selectors 62, 64.

Of the blocks shown in FIG. 13, the functions of blocks having the same number as those of the interface device shown in FIG. 4 will be easily understood with reference to the description of the functions of FIG. 4, and only here for the functions of blocks replaced or added. Let's explain.

The packet decoder 32 'inputs a parallel control signal to generate a chip select signal ce2 in addition to the chip select signal ce1, which is different from that of the packet decoder 32 of FIG. The selector 64 transmits the parallel data WD1 to WDk to the parallel-serial converter 42 in response to the write command WE and the chip select signal ce1, and the write command WE and the chip select signal ce2. In response, the parallel data WD1 to WDk are transmitted to the memory 60. The memory 60 is enabled in response to the chip select signal ce2 to perform an operation, and stores write data output from the selector 64 during a write operation in response to the command signal com and the address add. The read data is generated during the read operation. The selector 62 selects read data applied from k data input / output terminals (not shown) in response to the read command RE and the chip select signal ce1, and outputs the read data to the serial / parallel converter 44. In response to the RE and the chip select signal ce2, read data applied from k data input / output terminals (not shown) is selected and output to the serial-to-parallel converter 44.

The memory 60 shown in Fig. 13 is preferably designed to have twice the data storage capacity of the first memory m1 and the second memory m2.

The interface device IF 'of the memory module shown in Fig. 12 has the function of the interface device IF of Fig. 4 and the function of the memory m0.

Although not shown, the write / read data lines wd / rd of the first memory m1 and the second memory m2 of the memory module of FIG. 12 are similar to the first write / read data lines wd1 as shown in FIG. 7. / rd1) and second write / lead data lines wd2 / rd2.

Although the memory m0 and the first and second memories m1 and m2 of the interface device IF ′ of the memory module of FIG. 12 are described as not performing a write operation and a read operation in common, the memory m0 is described as an example. ) And the first and second memories m1 and m2 may be configured to perform a write operation and a read operation in common.

FIG. 14 shows a configuration of a sixth embodiment of a memory system including a memory module of the present invention, wherein the memory module 500 of FIG. 14 is assigned to each of the n groups of memory devices MG1 to MGn of FIG. The third to sixth memories m3 to m6 are added.

In the first and second memories m1 and m2 shown in FIG. 14, an operation is enabled in response to the first chip select signal transmitted to the first chip select signal line cs1, and the third to sixth memories The operations m3 to m6 are enabled in response to the second chip selection signal transmitted to the second chip selection signal line cs2. The interface device IF 'shown in Fig. 14 has a memory m0 similarly to the interface device shown in Fig. 13, and the memory m0 is enabled in response to the first chip selection signal.

The memory module 500 illustrated in FIG. 14 is configured such that the write / read data lines are shared by the first to sixth memories m1 to m6, but the write / read data lines may be separated.

Fig. 15 shows the configuration of an embodiment of a memory of the memory module of the present invention, which includes an instruction decoder 70, an address generator 72, a row decoder 74, a memory cell array 76, a column decoder 78, and data. It consists of an input part 80 and the data output part 82. The memory cell array 76 includes a memory cell MC connected between a word line wl and a bit line BL. In Fig. 15, wl shows one representative word line wl and one representative bit line BL.

The function of each of the blocks shown in FIG. 15 will be described below.

The command decoder 70 decodes the chip select signal CS and the command signal COM to generate a write command WE, a read command RE, and an active command ACT. The address generator 72 inputs the address ADD in response to the active command ACT to generate a row address radd, and inputs the address ADD in response to the write command WE or the read command RE. To generate a column address (cadd). The row decoder 74 decodes the row address radd to generate word select signals WL, and the column decoder 76 decodes the column address cadd to generate a column select signal CSL. The memory cell array 76 may transmit data to the memory cells MC connected between the selected word line wl in response to the word select signals WL and the selected bit line BL in response to the column select signal CSL. The data stored in the memory cells MC is read. The data input unit 80 inputs each of the serial data DQ1 to DQk after a delay by the set write latency, converts them in parallel, and inputs them to the memory cell array 76. The data output unit 82 converts each of the parallel data output from the memory cell array 76 in series and delays the set read latency to output each of the serial data DQ1 to DQk.

The memories of the memory module of the present invention shown in Fig. 15 need not be designed separately, and may be constructed using any kind of memory generally used.

Although not shown, the memory system of the present invention described above is preferably composed of differential read data line pairs because the read data between the memory control unit and the interface device is transmitted at a high speed. Since write / read data is transmitted at a low speed, it is preferable to configure single write / read data lines.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. You will understand that you can.

The memory module of the present invention and the memory system having the same do not need to include an interface device in each of the memories, and the configuration of the interface device is simplified by providing the interface device with respect to each group of memory devices.

Claims (58)

A plurality of groups of memory sections for receiving packet instructions for each of a plurality of groups and for generating read data for each of the plurality of groups, Each of the plurality of groups of memory units Inputs the packet command to generate a command signal and an address, generates write data included in the packet command during a write operation, transmits the write data to write / lead data lines, and writes the read operation / An interface device for receiving read data transmitted to the lead data lines and transmitting the read data lines; And Two or more first memories that receive the command signal and the address in common, receive the write data during the write operation, and transmit the read data to the write / lead data lines during the read operation. A memory module, characterized in that. The method of claim 1, wherein the write / read data lines Commonly connected to the interface device and the two or more first memories, The write data is composed of write data of two or more groups, and the write data of the two or more groups are sequentially output from the two or more first memories, The read data is composed of read data of two or more groups, and the read data of the two or more groups are sequentially output from the two or more first memories. 3. The method of claim 2, wherein the write latency of one of the two or more first memories is n, the read latency is m, the burst length is set to k, and the clock period corresponding to the burst length is determined. When j is set, the write latency of the other one of the two or more first memories is set to n + j, the read latency is set to m + j, and the burst length is set to k. . The method of claim 1, wherein the write / read data lines At least two groups of write / lead data lines connected separately to each of the interface device and the at least two first memories, The write data is composed of write data of the two or more groups, each of the write data of the two or more groups is simultaneously transmitted to each of the two or more first memories, The read data may include read data of two or more groups, and each of the read data of the two or more groups may be simultaneously output from each of the two or more first memories. The method of claim 4, wherein each of the two or more first memories The write latency, the read latency, and the burst length are each set to be the same. The memory of claim 1, wherein each of the plurality of groups of memory units Receives the command signal and the address in common during the write operation, receives the write data transmitted to the write / read data lines in the write operation, and reads the read data in the read operation. And at least two second memories for transmitting to read data lines. 7. The method of claim 6 wherein the packet command is And a first chip select signal for enabling the operation of the two or more first memories and a second chip select signal for enabling the operation of the two or more second memories. 8. The method of claim 7, wherein the write / read data lines First interface devices and the first write / read data lines connected in common between the interface device, one of the two or more first memories, and a second memory of the two or more second memories; And a second write / lead data line commonly connected between the first memory of the other of the two or more first memories and the second memory of the other of the two or more second memories. . 10. The write latency of claim 8 wherein the write latency of the first memory of one of the two or more first memories and the second memory of one of the two or more second memories is n, the read latency is m, and the burst length. Is set to k, and the clock period corresponding to the burst length is j, the write latency of the other first memory and the second memory is n + j, the read latency is m + j, and the burst And the length is set to k. 8. The method of claim 7, wherein the write / read data lines And a common connection between the interface device and the at least two first memories and the at least two second memories. 11. The method of claim 10, wherein each of the two or more first memories and each of the two or more second memories The write latency, the read latency, and the burst length are each set to be the same. The method of claim 1, wherein the interface device Receiving the packet command transmitted at the first operating frequency during the write operation, transmitting the write data included in the packet command at the second operating frequency, Receive the read data transmitted at the second operating frequency from the at least two first memories or the at least two second memories during the read operation, and read the read data into read data lines. Transmit at the operating frequency, And the first operating frequency is higher than the second operating frequency. The method of claim 1, wherein the read data lines Consists of pairs of differential data lines for transmitting differential data, The write / lead data lines And a single data line for transmitting a single data. A plurality of groups of memory sections for receiving packet instructions for each of a plurality of groups and for generating read data for each of the plurality of groups, Each of the plurality of groups of memory units A first memory, inputting the packet command to generate a command signal and an address, generating first and second write data included in the packet command during a write operation, and generating the first write data to the first write data; Stored in one memory, and transmitting the second write data to the write / read data lines, and during the read operation, the first memory generates first read data and is transmitted through the write / read data lines. An interface device receiving second lead data and outputting the first and second lead data to read data lines; And Receive the command signal and the address, receive the second write data transmitted to the write / read data lines in the write operation, and write the second read data to the write / read data in the read operation. And a memory device for transmitting the lines. 15. The method of claim 14, wherein the memory device And at least two second memories. 16. The system of claim 15, wherein the write / read data lines Commonly connected between the interface device and the two or more second memories, The second write data includes at least two groups of third write data, wherein the at least two third write data of the at least two groups is stored in the at least two second memories during the write operation. Are sequentially output to each of the memories, The second lead data includes at least two groups of third lead data, and the third lead data of at least two groups is sequentially output from each of the at least two second memories during the read operation. Memory module, characterized in that. The method of claim 16, wherein the write latency of one of the two or more second memories is n, the read latency is m, the burst length is set to k, and a clock period corresponding to the burst length is set. j, the write latency of the other second memory is set to n + j, the read latency is set to m + j, and the burst length is set to k. 16. The system of claim 15, wherein the write / read data lines And at least two groups of write / lead data lines connected separately to the interface device and each of the at least two second memories. 19. The apparatus of claim 18, wherein each of the two or more second memories The write latency, the read latency, and the burst length are each set to be the same. The apparatus of claim 14, wherein the interface device is Receiving the packet command transmitted at the first operating frequency during the write operation, transmitting the write data included in the packet command at a second operating frequency, Receiving read data transmitted from the memory device at the second operating frequency during the read operation, transmitting the read data at the first operating frequency, And the first operating frequency is higher than the second operating frequency. 15. The method of claim 14, wherein the read data lines Consists of pairs of differential data lines for transmitting differential data, The write / lead data lines And a single data line for transmitting a single data. A plurality of groups of memory sections for receiving packet instructions for each of a plurality of groups and for generating read data for each of the plurality of groups, Each of the plurality of groups of memory units A first memory, inputting the packet command to generate a command signal and an address, and storing the write data included in the packet command in the first memory or writing to the write / read data lines during a write operation; An interface for transmitting and outputting read data generated by the first memory to the read data lines during a read operation, or receiving and outputting read data transmitted through the write / read data lines to the read data lines. Device; And Receive the command signal and the address in common, receive the write data transmitted to the write / read data lines in the write operation, and read the read data into the write / read data lines in the read operation. And a memory device for transmitting. The memory device of claim 22, wherein the memory device is And at least two second memories. 24. The method of claim 23, wherein the write / read data lines Commonly connected between the interface device and the two or more second memories, The second write data includes at least two groups of third write data, wherein the at least two third write data of the at least two groups is stored in the at least two second memories during the write operation. Are sequentially output to each of the memories, The second lead data may include third lead data of two or more groups, and the third lead data of the two or more groups may be sequentially output from each of the two or more second memories during the read operation. And a memory module. 25. The method of claim 24, wherein the write latency of one of the two or more second memories is n, the read latency is m, the burst length is set to k, and the clock period corresponding to the burst length is j, the write latency of the other second memory is set to n + j, the read latency is set to m + j, and the burst length is set to k. 24. The method of claim 23, wherein the write / read data lines And at least two groups of write / lead data lines connected separately to the interface device and each of the at least two second memories. 27. The apparatus of claim 26, wherein each of the two or more second memories The write latency, the read latency, and the burst length are each set to be the same. The apparatus of claim 22, wherein the interface device is Receiving the packet command transmitted at the first operating frequency during the write operation, transmitting the write data included in the packet command at a second operating frequency, Receiving read data transmitted from the memory device at the second operating frequency during the read operation, transmitting the read data at the first operating frequency, And the first operating frequency is higher than the second operating frequency. 23. The method of claim 22, wherein the read data lines are Consists of pairs of differential data lines for transmitting differential data, The write / lead data lines And a single data line for transmitting a single data. A memory controller which transmits a plurality of groups of packet commands via control signal lines and receives a plurality of groups of read data via read data lines; And A memory module including a plurality of groups of memory units for receiving packet instructions of each of the plurality of groups and generating read data for each of the plurality of groups, Each of the plurality of groups of memory units Inputs the packet command to generate a command signal and an address, generates write data included in the packet command during a write operation, transmits the write data to write / lead data lines, and writes the read operation / An interface device for receiving read data transmitted to the lead data lines and transmitting the read data lines; And Two or more first memories that receive the command signal and the address in common, receive the write data during the write operation, and transmit the read data to the write / lead data lines during the read operation. Memory system, characterized in that. 31. The method of claim 30, wherein the write / read data lines Commonly connected to the interface device and the two or more first memories, The write data is composed of write data of two or more groups, and the write data of the two or more groups are sequentially output from the two or more first memories, The read data is composed of read data of two or more groups, and the read data of the two or more groups are sequentially output from the two or more first memories. 32. The method of claim 31, wherein the write latency of one of the two or more first memories is n, the read latency is m, the burst length is set to k, and the clock period corresponding to the burst length is When j is set, the write latency of the other one of the two or more first memories is set to n + j, the read latency is set to m + j, and the burst length is set to k. . 31. The method of claim 30, wherein the write / read data lines At least two groups of write / lead data lines connected separately to each of the interface device and the at least two first memories, The write data is composed of write data of the two or more groups, each of the write data of the two or more groups is simultaneously transmitted to each of the two or more first memories, The read data is composed of read data of two or more groups, and each of the read data of the two or more groups is simultaneously output from each of the two or more first memories. The method of claim 33, wherein each of the two or more first memories The write latency, the read latency, and the burst length are each set equally. The memory of claim 30, wherein each of the plurality of groups of memory units Receives the command signal and the address in common during the write operation, receives the write data transmitted to the write / read data lines in the write operation, and reads the read data in the read operation. And at least two second memories for transmitting to read data lines. 36. The method of claim 35, wherein the packet command is And a first chip select signal for enabling the operation of the two or more first memories and a second chip select signal for enabling the operation of the two or more second memories. 37. The method of claim 36, wherein the write / read data lines First interface devices and the first write / read data lines connected in common between the interface device, one of the two or more first memories, and a second memory of the two or more second memories; And a second write / lead data line commonly connected between the first one of the two or more first memories and the second one of the two or more second memories. . 38. The write latency of claim 37 wherein the write latency of the first memory of one of the two or more first memories and the second memory of one of the two or more second memories is n, the read latency is m, and the burst length. Is set to k, and the clock period corresponding to the burst length is j, the write latency of the other first memory and the second memory is n + j, the read latency is m + j, and the burst And the length is set to k. 37. The method of claim 36, wherein the write / read data lines And a common connection between the interface device and the at least two first memories and the at least two second memories. 40. The apparatus of claim 39, wherein each of the two or more first memories and each of the two or more second memories The write latency, the read latency, and the burst length are each set equally. The device of claim 30, wherein the interface device is Receiving the packet command transmitted at the first operating frequency during the write operation, transmitting the write data included in the packet command at the second operating frequency, Receive the read data transmitted at the second operating frequency from the at least two first memories or the at least two second memories during the read operation, and read the read data into read data lines. Transmit at the operating frequency, And the first operating frequency is higher than the second operating frequency. 31. The method of claim 30, wherein the read data lines are Consists of pairs of differential data lines for transmitting differential data, The write / lead data lines And a memory system comprising a single data line for transmitting a single data. A memory controller which transmits a plurality of groups of packet commands via control signal lines and receives a plurality of groups of read data via read data lines; And A memory module including a plurality of groups of memory units for receiving packet instructions of each of the plurality of groups and generating read data for each of the plurality of groups, Each of the plurality of groups of memory units A first memory, inputting the packet command to generate a command signal and an address, generating first and second write data included in the packet command during a write operation, and generating the first write data to the first write data; Stored in one memory, and transmitting the second write data to the write / read data lines, and during the read operation, the first memory generates first read data and is transmitted through the write / read data lines. An interface device receiving second lead data and outputting the first and second lead data to read data lines; And Receive the command signal and the address, receive the second write data transmitted to the write / read data lines in the write operation, and write the second read data to the write / read data in the read operation. And a memory device for transmitting the lines. 44. The memory device of claim 43, wherein the memory device is And at least two second memories. 45. The method of claim 44, wherein the write / read data lines Commonly connected between the interface device and the two or more second memories, The second write data includes at least two groups of third write data, wherein the at least two third write data of the at least two groups is stored in the at least two second memories during the write operation. Are sequentially output to each of the memories, The second lead data may include third lead data of two or more groups, and the third lead data of the two or more groups may be sequentially output from each of the two or more second memories during the read operation. Characterized by a memory system. 46. The method of claim 45, wherein the write latency of one of the two or more second memories is n, the read latency is m, the burst length is set to k, and the clock period corresponding to the burst length is When j is set, the write latency of the other second memory is set to n + j, the read latency is set to m + j, and the burst length is set to k. 45. The method of claim 44, wherein the write / read data lines And at least two groups of write / lead data lines connected separately to said interface device and each of said at least two second memories. 48. The apparatus of claim 47, wherein each of the two or more second memories The write latency, the read latency, and the burst length are each set equally. 44. The apparatus of claim 43, wherein the interface device is Receiving the packet command transmitted at the first operating frequency during the write operation, transmitting the write data included in the packet command at a second operating frequency, Receiving read data transmitted from the memory device at the second operating frequency during the read operation, transmitting the read data at the first operating frequency, And the first operating frequency is higher than the second operating frequency. 44. The method of claim 43, wherein the read data lines Consists of pairs of differential data lines for transmitting differential data, The write / lead data lines And a memory system comprising a single data line for transmitting a single data. A memory controller which transmits a plurality of groups of packet commands via control signal lines and receives a plurality of groups of read data via read data lines; And A memory module including a plurality of groups of memory units for receiving packet instructions of each of the plurality of groups and generating read data for each of the plurality of groups, Each of the plurality of groups of memory units A first memory, inputting the packet command to generate a command signal and an address, and storing the write data included in the packet command in the first memory or writing to the write / read data lines during a write operation; An interface for transmitting and outputting read data generated by the first memory to the read data lines during a read operation, or receiving and outputting read data transmitted through the write / read data lines to the read data lines. Device; And Receive the command signal and the address in common, receive the write data transmitted to the write / read data lines in the write operation, and read the read data into the write / read data lines in the read operation. And a memory device for transmitting. 53. The memory device of claim 51, wherein the memory device is And at least two second memories. 53. The method of claim 52, wherein the write / read data lines Commonly connected between the interface device and the two or more second memories, The second write data includes at least two groups of third write data, wherein the at least two third write data of the at least two groups is stored in the at least two second memories during the write operation. Are sequentially output to each of the memories, The second lead data may include third lead data of two or more groups, and the third lead data of the two or more groups may be sequentially output from each of the two or more second memories during the read operation. Characterized by a memory system. 54. The method of claim 53, wherein the write latency of one of the two or more second memories is n, the read latency is m, the burst length is set to k, and the clock period corresponding to the burst length is When j is set, the write latency of the other second memory is set to n + j, the read latency is set to m + j, and the burst length is set to k. 53. The method of claim 52, wherein the write / read data lines And at least two groups of write / lead data lines connected separately to said interface device and each of said at least two second memories. 56. The apparatus of claim 55, wherein each of the two or more second memories The write latency, the read latency, and the burst length are each set equally. The apparatus of claim 51, wherein the interface device is Receiving the packet command transmitted at the first operating frequency during the write operation, transmitting the write data included in the packet command at a second operating frequency, Receiving read data transmitted from the memory device at the second operating frequency during the read operation, transmitting the read data at the first operating frequency, And the first operating frequency is higher than the second operating frequency. 53. The method of claim 51, wherein the read data lines are Consists of pairs of differential data lines for transmitting differential data, The write / lead data lines And a memory system comprising a single data line for transmitting a single data.

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