JP4488282B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a semiconductor integrated circuit having an ASIC (Application Specific Integrated Circuit).

  In layout design of a semiconductor memory device, there are various layout design methods depending on the type of the semiconductor memory device. For example, the macro cell system is an effective system when a system such as a microprocessor, a memory, an I / O (input / output), and a custom circuit is integrated on one chip, and circuit blocks of various sizes are arranged in the chip area. Then, it is a method of wiring them.

  The macro cell is a circuit block in which certain functions such as a RAM (Random Access Memory) and a CPU (Central Processing Unit) are determined in advance and optimized in terms of circuit arrangement or operation speed. The macro cell is formed in units of functional blocks such as a RAM, and is formed with a higher density than other circuit parts such as a spread gate region by a design that is mainly manual. Due to advances in circuit technology and process technology, parts such as macrocells can be operated faster than other circuit parts that are formed in a spread gate region.

  A RAM formed as a macro cell includes a time division type multi-port RAM that realizes a multi-port function by serially processing the operation of each port by a time division type (STS) (see, for example, Patent Document 1).

JP-A-7-84987 (FIG. 13 etc.)

  The inventors of the present invention have studied the multi-port RAM using the time division method. As a result, the layout differs depending on the number of ports and port functions. It is necessary to design each individually, and it has been found that this is a factor that hinders cost reduction of the multiport RAM. In addition, since the number of ports cannot be arbitrarily changed on the user side, the use is limited in a gate array type semiconductor integrated circuit equipped with such a multi-port RAM macrocell.

An object of the present invention is to provide a technique for reducing the cost of the semiconductor integrated circuit having a multi-port function by time division system.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a semiconductor memory device is configured including a memory core having a port capable of inputting and outputting signals, and a port expansion circuit coupled to the memory core and capable of expanding the port of the memory core by time division. The port expansion circuit is provided with a port switching circuit capable of switching the ports realized by the time division.

  According to the above means, the port switching circuit enables port switching realized by the time division. Thereby, the layout of the semiconductor memory device can be made common regardless of the number of ports and the port function, and this achieves cost reduction of the multi-port RAM in the time division method.

  At this time, the port expansion circuit determines the timing of the internal clock signal for each port that can be realized by the time division and the first delay element that can set the pulse width of the internal clock signal for each port that can be realized by the time division. Based on the settable second delay element, the output signal of the first delay element, and the output signal of the second delay element, an internal clock signal for each port that can be realized by the time division is formed. And a first logic circuit.

  The port switching circuit is time-division based on a port switching terminal capable of capturing a port switching signal, a port switching signal input via the port switching terminal, and an output signal of the second delay element. And a second logic circuit for performing port switching that can be realized.

  The port expansion circuit may include an address system input unit for fetching an address signal from the outside and a data system input unit for fetching data from the outside, and the address system input unit and the data system The input unit can include a third logic circuit that can fix the logic of a terminal to which no signal is input in response to a port switching signal input via the port switching terminal.

  The semiconductor memory device having the above structure can be incorporated into a semiconductor integrated circuit as a macro cell.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, since the port switching circuit enables port switching realized by time division, the layout of the semiconductor memory device can be made common regardless of the number of ports and the port function, and thereby time division The cost of the semiconductor memory device in the system can be reduced.

  FIG. 2 shows a chip image of a configuration example of a semiconductor integrated circuit according to the present invention. This semiconductor integrated circuit is configured by partially adopting an ASIC, for example, a gate array technique, and a large number of bonding pads 2 and input / output buffers 3 are arranged in the peripheral portion of the chip 1. The spread gate region 4 and the RAM macro cell 5 are arranged in the area.

  In the spread gate region 4, a required function is realized by a connection mode of basic circuits arranged repeatedly in large numbers. For example, a large number of complementary MOS basic cells of a gate array are arranged. Reference numeral 6 denotes a clock pulse generator (CPG) which, for example, divides or simply shapes a system clock signal φ supplied from the outside to generate a clock signal CLK. The circuit of the spread gate region 4 is operated in synchronization with the clock signal CLK.

  The RAM macrocell 5 is an example of a semiconductor memory device according to the present invention, and is a time division multi-port RAM as will be described in detail later. The RAM macrocell 5 is a functional block in which the integration density of circuit elements is higher than that of the spread gate region 4 and the functions thereof are determined in advance.

  FIG. 1 shows a configuration example of the RAM macro cell 5.

  The RAM macrocell 5 includes, but is not limited to, a 1-port SRAM core 10 and a port expansion circuit 20 for expanding the port of the 1-port SRAM core 10 by time division.

  The 1-port SRAM core 10 includes a clock generator 11, a row decoder (X-DEC) 12, a 1-port memory cell array 13, a latch circuit 14, a column decoder (Y-DEC) 15, and an input / output amplifier 16.

  The clock generator 11 generates an operation timing signal for each part based on the internal clock signal φCK supplied from the port expansion circuit 20.

  The latch circuit 14 latches the internal signal supplied from the port expansion circuit 20 in synchronization with the operation timing signal from the clock generator 11. The internal signals latched by the latch circuit 14 include data written to the 1-port SRAM core 10 and address signals of the 1-port SRAM core 10.

  The 1-port memory cell array 13 includes a plurality of word lines, a plurality of bit lines formed so as to intersect with the word lines, and static memory cells provided at intersections between the word lines and the bit lines. When the word line is driven to the selection level, the corresponding static memory cell is selectively coupled to the corresponding bit line. Thereby, data writing to the memory cell and data reading from the memory cell can be performed.

  The row decoder 12 generates a signal for driving the word line in the 1-port memory cell array 13 to a selected level by decoding the row-related address signal fetched through the latch circuit 14.

  The column decoder 15 drives a column switch that selectively couples a plurality of bit lines in the 1-port memory cell array 13 to a common bit line by decoding a column-related address signal fetched via the latch circuit 14. A signal is generated to

  The input / output amplifier 16 includes an input system circuit that captures data to be written into the 1-port memory cell array 13 and an output system circuit that outputs data read from the 1-port memory cell array 13.

  The port expansion circuit 20 includes a timing generator 21, a latch circuit 23, and a selector circuit 24.

  The timing generator 21 generates an internal clock signal φCK that enables port expansion based on the clock signal CLK generated by the clock pulse generator 6. The timing generator 21 includes a port switching circuit 32 that can switch ports realized by time division. The port switching circuit 32 performs port switching that can be realized by time division in accordance with a port switching signal fetched via the port switching terminals PS0 and PS1.

  The latch circuit 23 latches a signal transmitted via signal input terminals corresponding to the ports A, B, C, and D. Here, the signal transmitted via the signal input terminal includes an address signal and write data.

  FIG. 3 shows a detailed configuration example of the timing generator 21.

  The timing generator 21 includes a port switching circuit 32, delay circuits 220, 230, 240, 250, and a parallel / serial conversion circuit 211.

  Each of the delay circuits 220, 230, 240, and 250 has a function of delaying an input clock signal and transmitting the delayed input clock signal to the subsequent parallel-serial conversion circuit 211. When the output clock signal of the delay circuit 220 is φCKA, the output clock signal of the delay circuit 230 is φCKB, the output clock signal of the delay circuit 240 is φCKC, and the output clock signal of the delay circuit 250 is φCKD, the parallel serial The conversion circuit 211 converts the output clock signals φCKA, φCKB, φCKC, φCKD input in the parallel format into a serial format and outputs it as the internal clock signal φCK. The internal clock signal φCK is transmitted to the clock generator 11 in the 1-port SRAM core 10.

  The delay circuit 220 is not particularly limited, but a first delay element (delay A) 223 capable of setting the pulse width of the internal clock signal for each port that can be realized by time division, and the internal for each port that can be realized by the time division. A second delay element (delayB) 224 capable of setting the timing of the clock signal, a two-input NAND gate 222, and an inverter 221 are included. The clock signal CLK input from the clock input terminal CKIN is transmitted to one terminal of the 2-input NAND gate 222 through the first delay element 223. The 2-input NAND gate 222 obtains a NAND logic between the clock signal CLK input from the clock input terminal CKIN and the output clock signal from the first delay element 223. The output signal of the NAND gate 222 is output as the clock signal φCKA through the inverter 221 in the subsequent stage. The output clock signal from the second delay element 224 is transmitted to the port switching circuit 32.

  The delay circuit 230 is not particularly limited, but a first delay element (delayA) 233 capable of setting a pulse width of an internal clock signal for each port that can be realized by time division, and an internal for each port that can be realized by the time division. A second delay element (delay B) 234 capable of setting the timing of the clock signal, a two-input NAND gate 232, and an inverter 231 are included. The clock signal CLK input via the port switching circuit 32 is transmitted to one terminal of the 2-input NAND gate 232 via the first delay element 233. The 2-input NAND gate 232 obtains a NAND logic between the clock signal CLK input via the port switching circuit 32 and the output clock signal from the first delay element 233. The output signal of the NAND gate 232 is output as the clock signal φCKB through the inverter 231 in the subsequent stage. The output clock signal from the second delay element 234 is transmitted to the port switching circuit 32.

  The delay circuit 240 is not particularly limited, but a first delay element (delayA) 243 capable of setting the pulse width of the internal clock signal for each port that can be realized by time division, and the internal for each port that can be realized by the time division. A second delay element (delayB) 244 capable of setting the timing of the clock signal 244, a two-input NAND gate 242, and an inverter 241 are included. The clock signal CLK input via the port switching circuit 32 is transmitted to one terminal of the 2-input NAND gate 242 via the first delay element 243. The 2-input NAND gate 242 obtains a NAND logic between the clock signal CLK input via the port switching circuit 32 and the output clock signal from the first delay element 243. The output signal of the NAND gate 242 is output as the clock signal φCKC through the inverter 241 at the subsequent stage. The output clock signal from the second delay element 244 is transmitted to the port switching circuit 32.

  The delay circuit 250 is not particularly limited, but a first delay element (delay A) 253, a dummy element 254, a two-input NAND gate 252, and an inverter 251 that can set the pulse width of the internal clock signal for each port that can be realized by time division. Including. The clock signal CLK input via the port switching circuit 32 is transmitted to one terminal of the 2-input NAND gate 252 via the first delay element 253. The 2-input NAND gate 252 obtains a NAND logic between the clock signal CLK input via the port switching circuit 32 and the output clock signal from the first delay element 253. The output signal of the NAND gate 252 is output as the clock signal φCKD through the inverter 251 at the subsequent stage. The output clock signal from the second delay element 234 is transmitted to the port switching circuit 32.

  The parallel / serial conversion circuit 211 converts the output clock signals φCKA, φCKB, φCKC, and φCKD from the delay circuits 220, 230, 240, and 250 into a serial clock signal φCK and outputs the clock signal φCK.

  The latch circuit 23 and the selector 24 are operated in synchronization with the output clock signals φCKA, φCKB, φCKC, φCKD from the delay circuits 220, 230, 240, 250.

  The port switching circuit 32 includes port switching terminals PS0 and PS1 that enable capturing of a port switching signal, an inverter 350 for inverting the logic of the port switching signal input via the port switching terminal PS0, and a port switching And logic circuits 320, 330, and 340.

  The logic circuit 320 includes inverters 323, 324, and 325 for delaying an output clock signal from the delay element 224, an output clock signal of the inverter 325, and a port switching signal transmitted through the inverter 350. A two-input NAND gate 322 for obtaining NAND logic and an inverter 321 for inverting the logic of the output signal of the NAND gate 322 are included. The output signal of the inverter 321 is transmitted to the delay circuit 230.

  The logic circuit 330 includes an inverter 337 for inverting the logic of the output clock signal from the delay element 224, an inverter 338 for inverting the logic of the port switching signal transmitted through the inverter 350, and the inverter NAND gate 336 for obtaining the NAND logic of the output signals of 337 and 338, inverters 331 and 332 for delaying the output clock signal from the delay element 234, the output signal of this inverter 332, the output signal of the NAND gate 336, The NAND gate 335 for obtaining the NAND logic of the NAND gate 335 and inverters 333 and 334 for delaying the output signal of the NAND gate 335 are included. The output signal of the inverter 334 is transmitted to the delay circuit 240.

  The logic circuit 340 includes NANDs of inverters 341, 342, and 343 for delaying an output clock signal from the delay element 244, a port switching signal transmitted through the inverter 360, and an output signal of the inverter 343. A NAND gate 345 for obtaining logic and an inverter 344 for inverting the logic of the output signal of the NAND gate 345 are included. The output signal of the inverter 344 is transmitted to the delay circuit 250.

  The port expansion circuit 20 includes an input system circuit between the address input terminals ADRB and ADRD that enable capturing of an address signal, the data input terminal DIND that enables capturing of write data, and the latch circuit 23. Provided. This input system circuit includes an address system input unit 26 and a data system input unit 271. The address system input unit 26 has a NAND gate 261 for obtaining a NAND logic between an address signal input through the address input terminal ADRB and a port switching signal transmitted through the inverter 350, and an input through the address input terminal ADRD. And a NAND gate 262 for obtaining a NAND logic between the received address signal and the port switching signal transmitted through the inverter 360. The output signals of the NAND gates 261 and 262 are transmitted to the latch circuit 23 at the subsequent stage.

  Here, the NAND gates 261, 262, and 271 are examples of a logic circuit that can fix the logic of a terminal to which no signal is input in response to a port switching signal input via the port switching terminal. For example, the output levels of the NAND gates 261, 262, and 271 are forcibly set to a logical value “1” in order to prevent a port that is not selected by a port switching signal input via the port switching terminal from becoming indefinite. By fixing, the level of the input terminal of the latch circuit 23 is prevented from becoming an undesired intermediate potential.

  4 shows a truth table of the port switching terminals PS0 and PS1, and FIG. 5 shows an operation timing chart of the main part of the timing generator 21. As shown in FIG. For convenience of explanation, for example, ports A and B are read ports, and ports C and D are write ports.

As shown in FIG. 5A , when the logical values of the port switching terminals PS0 and PS1 are “0” and “0” by the port switching signal, the clock input via the clock input terminal CKIN. In response to the logical value “1” of the signal CLK, the clock signals φCKA, φCKB, φCKC, and φCKD are all set to the logical value “1”. The selector circuit 24 selects the outputs of the latch circuits 23 corresponding to the ports A, B, C, and D corresponding to the logical values “1” of the clock signals φCKA, φCKB, φCKC, and φCKD, respectively. The parallel / serial conversion is performed, and the converted output is transmitted to the latch circuit 14 of the 1-port SRAM core 10.

As shown in FIG. 5B , when the logical values of the port switching terminals PS0 and PS1 are “1” and “0” by the port switching signal, the clock input via the clock input terminal CKIN. In response to the logic value “1” of the signal CLK, the clock signals φCKA, φCKC, and φCKD are set to the logic value “1”, and only the clock signal φCKB is set to the logic value “0”. The selector circuit 24 selects the outputs of the latch circuits 23 corresponding to the ports A, C, and D corresponding to the logical values “1” of the clock signals φCKA, φCKC, and φCKD. Conversion is performed, and the converted output is transmitted to the latch circuit 14 of the 1-port SRAM core 10. At this time, the output of the latch circuit 23 corresponding to the port B is not selected . Since the port B is a read port, the level of the input terminal which is not used in the latch circuit 23 is fixed to the logical value “1” by the NAND gate 261 corresponding to the port B, so that the terminal is not desired. It is prevented that the intermediate potential is reduced.

As shown in FIG. 5C , when the logical values of the port switching terminals PS0 and PS1 are “0” and “1” by the port switching signal, the clock input via the clock input terminal CKIN. In response to the logic value “1” of the signal CLK, the clock signals φCKA, φCKB, and φCKC are set to the logic value “1”, and only the clock signal φCKD is set to the logic value “0”. The selector circuit 24 selects the outputs of the latch circuits 23 corresponding to the ports A, B, and C corresponding to the logical values “1” of the clock signals φCKA, φCKB, and φCKC. Conversion is performed, and the converted output is transmitted to the latch circuit 14 of the 1-port SRAM core 10. At this time, the output of the latch circuit 23 corresponding to the port D is not selected . Since the port D is a write port, the levels of the address input terminal and the data input terminal that are not used in the latch circuit 23 are fixed to the logical value “1” by the NAND gates 262 and 271 corresponding to the port D. This prevents the terminal from becoming an undesired intermediate potential.

As shown in FIG. 5D , when the logical values of the port switching terminals PS0 and PS1 are “1” and “1” by the port switching signal, the clock input via the clock input terminal CKIN. In response to the logic value “1” of the signal CLK, the clock signals φCKA and φCKC are set to the logic value “1”, and the clock signals φCKB and φCKD are set to the logic value “0”. The selector circuit 24 selects the output of the latch circuit 23 corresponding to the ports A and C corresponding to the logical value “1” of the clock signals φCKA and φCKC, thereby performing parallel-serial conversion by time division. The converted output is transmitted to the latch circuit 14 of the 1-port SRAM core 10. At this time, the output of the latch circuit 23 corresponding to the ports B and D is not selected . Since the port B is a read port and the port D is a write port, the NAND gates 261, 262, and 271 corresponding to the ports B and D are used for address input terminals and data input terminals that are not used in the latch circuit 23. By fixing the level to the logical value “1”, it is possible to prevent the terminal from becoming an undesired intermediate potential.

As described above, by changing the logical values of the port switching terminals PS0 and PS1 by the port switching signal, it is possible to perform port switching that can be realized by time division. At this time, as the number of ports realized by time division is smaller, the cycle of the clock signal CLK can be shortened, so that the operation speed can be increased accordingly. For example, the cycle time is shortened to 3/4 when 3 ports are realized (FIGS. 5B and 5C), compared to when 4 ports are realized (FIG. 5A). Therefore, when 2 ports are realized (FIG. 5D), the speed can be increased by reducing the cycle time to ½.

  According to the above example, the following effects can be obtained.

  (1) By providing the port switching circuit 32 capable of switching ports realized by time division, it is possible to switch ports realized by time division. Therefore, regardless of the number of ports and port functions, the layout of semiconductor memory devices can be shared, and the ports realized by time division can be set according to user specifications, so multi-ports in the time division method The cost of the RAM can be reduced.

  (2) Delay elements 223, 233, 243, 253 that can set the pulse width of the internal clock signal for each port that can be realized by time division, and the timing of the internal clock signal for each port that can be realized by the above time division Ports that can be realized by the time division based on the possible delay elements 224, 234, 244, the output signals of the delay elements 223, 233, 243, 253 and the output signals of the delay elements 224, 234, 244 By providing the logic circuits 222, 232, 242, and 252 for generating the internal clock signal for each, the port expansion circuit 22 having the function (1) can be easily formed.

  (3) The port switching circuit 32 includes port switching terminals PS0 and PS1 that enable the port switching signal to be taken in, the port switching signal input through the port switching terminals PS0 and PS1, and the second delay element 224. It can be easily formed by providing logic circuits 320, 330, and 340 for switching ports that can be realized by time division based on the output signals of 234 and 244. Further, since the port switching terminals PS0 and PS1 are provided, it is possible to easily change the ports realized by time division only by changing the logic level of the port switching signal applied to the terminals PS0 and PS1.

  (4) The port expansion circuit 20 can be configured to include an address system input unit 26 for fetching an address signal from the outside and a data system input unit 27 for fetching data from the outside. At this time, the NAND gate By providing 261,262,271, the logic of a terminal to which no signal is input can be fixed in accordance with the port switching signal input through the port switching terminal. By setting the intermediate potential, the circuit is prevented from malfunctioning.

  (5) Ports that can be realized by time division can be switched according to the logical values of the port switching terminals PS0 and PS1 by the port switching signal. At this time, as the number of ports realized by time division is smaller, the cycle of the clock signal CLK can be shortened, so that the operation speed can be increased accordingly.

  (6) Since the cost of the multi-port RAM 5 in the time division method can be reduced by the effect of the above (1), a semiconductor integrated circuit in which such a multi-port RAM 5 is incorporated as a macro cell is provided at a low cost. Can do.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, whether the ports A, B, C, and D are read ports or write ports can be appropriately changed. The 1-port memory cell array can be configured by arranging a plurality of dynamic memory cells.

  In the above description, the case where the invention made mainly by the present inventor is applied to the multi-port RAM which is the field of use that has been the background has been described. However, the present invention is not limited to this and is applied to various semiconductor memory devices. Can be applied.

  The present invention can be applied on the condition that the port expansion of the memory core is enabled at least by time division.

1 is a block diagram illustrating a configuration example of a RAM macro cell which is an example of a semiconductor memory device according to the present invention. It is explanatory drawing of the example of a structure of the semiconductor integrated circuit containing the said RAM macrocell. FIG. 3 is a circuit diagram illustrating a configuration example of a timing generator included in the RAM macro cell. It is truth table explanatory drawing of the port switching terminal contained in the said AM macrocell. It is an operation | movement timing diagram of the principal part in the said timing generator.

Explanation of symbols

1 chip 5 RAM macro cell 5
10 1-port SRAM core 11 Clock generator 12 Row decoder 13 1-port memory cell array 14 Latch circuit 15 Column decoder 16 Input / output amplifier 20 Port expansion circuit 21 Timing generator 23 Latch circuit 24 Selector circuit 32 Port switching circuit CKIN Clock input terminal PS0, PS1 Port switching terminal

Claims (4)

A semiconductor integrated circuit in which a memory macrocell is arranged,
The memory macrocell includes a terminal to which an external clock signal is input,
A memory core with one port;
4 ports,
A signal coupled between a plurality of selected ports of the four ports and the one port of the memory core and transmitted between the selected ports and the one port of the memory core only contains a conversion circuit for parallel-to-serial conversion, by the time division,
The conversion circuit includes a pair of terminals to which a port selection signal is input;
A selector circuit for selecting a signal transmitted through the selected port;
A timing generator for generating an internal clock pulse for setting a timing for driving the selector circuit according to a combination of selection signals input from the port selection signal input terminal,
(A) In the aspect of selecting the four ports, the timing generator generates an internal clock pulse consisting of four pulses, and the selector circuit driven by the internal clock pulse generates the four ports. The internal signal transmitted between this port and the 1-port memory core is parallel-serial converted by time division.
(B) In the case of selecting any three of the four ports, an internal clock pulse including a set of three pulses by the timing generator corresponding to the selected three ports is set. The internal signal transmitted between the three ports selected by the selector circuit driven by the internal clock pulse and the one-port memory core is parallel-serial converted by time division,
(C) In the case of selecting any two of the four, the internal clock pulse, which is a set of two pulses, is generated by the timing generator corresponding to the two selected ports, The selector circuit driven by the internal clock pulse is configured to parallel-serial convert the internal signal transmitted between the two selected ports and the one-port memory core by time division.
One cycle of the external clock signal input to the external clock signal input terminal is synchronized with the internal clock pulse composed of the four pulses in the mode (a), and the three cycles in the mode (b). A semiconductor integrated circuit, wherein the semiconductor integrated circuit is configured to be synchronized with an internal clock pulse composed of a plurality of pulses, and in the case of the mode (c), is synchronized with an internal clock pulse composed of the two pulses . The conversion circuit includes a first delay element capable of setting a pulse width of the internal clock signal, a second delay element capable of setting a timing of the internal clock signal, and an output signal of said first delay element, said first based on the output signal of 2 delay element, a semiconductor integrated circuit of claim 1 further comprising a logical circuit for forming an internal clock signal for each said selected port. The conversion circuit includes a logic circuit that sets the logic of the port terminal so that the logic of the port terminal can be fixed when there is a port terminal to which no signal is input according to the port selection signal input to the port selection signal input terminal The semiconductor integrated circuit according to claim 1 or 2. A semiconductor integrated circuit in which a memory macrocell is arranged,
The memory macrocell includes a terminal to which an external clock signal is input,
A memory core with one port, multiple ports,
A signal transmitted between the selected ports of the plurality of ports and the one port of the memory core is transmitted between the selected ports and the one port of the memory core. A conversion circuit that performs parallel-serial conversion by dividing,
The conversion circuit includes a terminal to which a port selection signal is input;
A selector circuit for selecting a signal transmitted through the selected port;
A timing generator for generating an internal clock pulse for setting the timing for driving the selector circuit according to the selection signal,
The timing generator generates an internal clock pulse including a plurality of pulses corresponding to the selected port as a set,
The selector circuit is driven by the internal clock pulse, and is configured to parallel-serial convert an internal signal transmitted between the selected plurality of ports and the one-port memory core by time division.
A semiconductor integrated circuit, wherein one cycle of the external clock signal is configured to be synchronized with an internal clock pulse composed of the plurality of pulses corresponding to the selected port .

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