JP2001266574A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize constitution by which collision of input/output data of a memory circuit and a logic circuit on an I/O bus is prevented and a high impedance state of an I/O bus is prevented without increasing chip area. SOLUTION: An output of a D-flip-flop 103 conventionally used as a control signal of a DRAM data output circuit 104 hitherto is directly inputted to a second logic gate 107 consisting of AND gates via a first delay circuit 105 and a second delay circuit 106, while an output of the D-flip-flop 103 is inputted directly to the second logic gate 107 and an output of the second logic gate 107 is used as a control signal D of the DRAM data output circuit 104. Further an output of the first delay circuit 105 is inverted by a third logic gate 108 being an inverter, the inverted output is used as a control signal E of a logic section data output circuit 202.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device in which a dynamic random access memory (DRAM) and a logic circuit (logic circuit) are integrated on the same semiconductor chip.

[0002]

2. Description of the Related Art A conventional semiconductor integrated circuit device will be described below with reference to the drawings. FIG. 3 is a block diagram showing a configuration of a conventional semiconductor integrated circuit device in which a DRAM section and a logic section are integrated on the same semiconductor chip. In the figure, 100 is a DRAM unit, 101 is a memory circuit composed of a memory cell array and peripheral circuits, 102 is a logic gate, 103 is a D flip-flop, and 104 is a D-flip-flop.
The RAM section data output circuit 110 is a power-on reset signal generation circuit. Reference numeral 200 denotes a logic unit, reference numeral 201 denotes a logic circuit, and reference numeral 202 denotes a logic unit data output circuit. Reference numeral 300 denotes a common I / O (input / output) bus between the DRAM unit and the logic unit, and reference numeral 301 denotes a bus hold circuit.

In the semiconductor integrated circuit device shown in FIG. 3, a DRAM unit 100 and a logic unit 200 are mounted in the same chip, and data transfer between the DRAM unit 100 and the logic unit 200 is performed by n (n is a plurality) I data. The configuration is performed through the / O bus 300. In the DRAM section 100, each of the outputs of the n data buses output from the memory circuit 101 including the memory cell array and the peripheral circuit is connected to n tristate buffers to form a DRAM section data output circuit 104. , In the logic unit 200,
Each of the n data bus outputs from the logic circuit 201 is connected to n tristate buffers to form a logic section data output circuit 202.
The output of the DRAM unit data output circuit 104 and the output of the logic unit data output circuit 202 are connected to n common I / O buses 301.

FIG. 4 is a timing chart showing the operation of the conventional semiconductor integrated circuit device having the structure shown in FIG.
Indicates a power supply voltage. In the semiconductor integrated circuit device of FIG. 3, when the power is turned on, the power-on reset signal generation circuit 110 operates and the reset control signal / RST goes to the “L” level (the clock input signal CLK goes from “L” to “H” level). Until the D-flip-flop 103
Are initialized, so that the DRAM unit data output control signal B
Is disabled, and no data is output from the DRAM unit 100 to the I / O bus 300. For this reason, even if there is any output from the logic unit 200 to the I / O bus 300 immediately after the power is turned on, no data is output from the DRAM unit 100, so that the output data of the DRAM unit 100 and the logic unit 200 is not output. Try to avoid collisions.

Next, in the read / write cycle of the DRAM unit, control signals such as / RAS, / CAS, / WE, and address (n bits) are latched in synchronization with the rising edge of the clock input signal CLK, and the DRAM unit is read. 100
Data transfer between the logic units 200 is performed.

First, in a read cycle, a row address (of FIG. 4) and a column address (of FIG. 4) are fetched every clock cycle in synchronization with a rising edge of a clock input signal CLK. Is operated so that the data of the selected address is output at the clock edge of FIG. At this time, since the row address selection control signal / RAS is "L", the column address selection control signal / CAS is "L", and the write enable signal / WE is "H", the output A of the logic gate 102 is "H". 4 and the D-flip-flop 103 at the clock edge in FIG.
Of the DRAM section 100 becomes "H" level, the data output circuit 104 of the DRAM section is enabled, and the DRAM section 100
Is output onto the I / O bus 300. At this time, the logic unit output enable signal F is set to be in a disabled state, and there is no data output from the logic unit 200 onto the I / O bus 300.

Similarly, in a DRAM part write cycle,
Control signals such as / RAS, / CAS, / WE, and address are latched in synchronization with the rising edge of the clock input signal CLK.
Is always at "L" level, the DRAM unit data output circuit 104 is disabled, and there is no output from the DRAM unit 100. In this state, the logic unit output enable signal F is set to “H” level, and the logic unit 200
Output data from the DRAM through the I / O bus 300
Written in part 100.

The bus hold circuit 301 connected to the I / O bus 300 shown in FIG.
Is connected to each I / O bus 300 for the purpose of preventing the potential of the I / O bus 300 from reaching the intermediate level for a long time (this prevents a through current from flowing in the CMOS input circuit of the DRAM unit 100 or the logic unit 200). I have.

As described above, the output from the DRAM unit 100 is prevented by the reset signal / RST output from the power-on reset signal generation circuit 110 when the power is turned on, and the bus collision with the output data of the logic unit 200 is prevented. Avoided. Also, in the read / write cycle of the DRAM section, the DRAM section 100 and the logic
It is designed so that the collision of output data of 0 does not occur.

[0010]

However, in the above-mentioned conventional configuration, in order to prevent a bus collision at the time of turning on the power, the DRAM unit 100 (or the logic unit 20) is turned on at the time of turning on the power.
The power-on reset signal generation circuit 110 for performing the output reset operation of 0) is required. Further, in order to prevent the I / O buses 300 from being in a high impedance state, the bus hold circuits 301 are required by the number of the I / O buses 300. These power-on reset signal generation circuits 11
It is obvious that the bus hold circuits 301 for 0 or the number of I / Os will be an obstacle in reducing the area of the semiconductor integrated circuit device. Therefore, I / O bus collision prevention or I / O in a smaller circuit configuration is required. It is desired to realize the prevention of the high impedance state of the O bus 300.

The present invention focuses on this point, and its object is to prevent collision between input / output data of a memory circuit and a logic circuit inside a semiconductor integrated circuit device on an I / O bus, and
The configuration for preventing the high impedance state of the / O bus is
An object of the present invention is to provide a semiconductor integrated circuit device that can be controlled stably and reliably without using a power-on reset signal generation circuit and a bus hold circuit, that is, without increasing the chip area.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a memory circuit; a logic circuit; a plurality of first tri-state buffers connected to each of a plurality of outputs from the memory circuit; A plurality of second tri-state buffers connected to each of the plurality of outputs from the logic circuit; and a plurality of first tri-state buffers and a plurality of second tri-state buffers respectively connected to the outputs of the plurality of second tri-state buffers. A common I / O bus including a plurality of signal lines;
The output enabled / disabled state of the plurality of first tri-state buffers and the output enabled / disabled state of the plurality of second tri-state buffers are different in response to a control signal and a clock signal supplied from the logic circuit to the memory circuit. Control means for switching control as described above.

According to the first aspect of the present invention, the control means controls whether the output of the plurality of first tristate buffers connected to the output of the memory circuit is enabled / disabled and the plurality of control means connected to the output of the logic circuit. Is switched so that the output enable / disable state of the second tri-state buffer is different from that of the second tri-state buffer, so that when the power is turned on, both data of the memory circuit and the logic circuit are output to the common I / O bus at the same timing. Thus, bus collision can be prevented without using a power-on reset circuit as in the related art. Further, the data of either the memory circuit or the logic circuit is shared by the common I / O.
Since the I / O bus always appears on the O bus, the high impedance state of the I / O bus can be prevented without using a bus hold circuit as in the related art. As described above, since a power-on reset circuit having a large circuit scale and a bus hold circuit for the number of I / Os are not used, the area of the semiconductor integrated circuit device can be reduced.

According to a second aspect of the present invention, there is provided the semiconductor integrated circuit device according to the first aspect, wherein the control means controls the plurality of second tri-state buffers before enabling the outputs of the plurality of first tri-state buffers. Disabling the output of the tri-state buffer and disabling the output of the plurality of first tri-state buffers before enabling the output of the plurality of second tri-state buffers.

By shifting the output enable / disable state switching timing of the first tri-state buffer and the second tri-state buffer, bus collision due to signal skew can be prevented during switching. .

According to a third aspect of the present invention, in the semiconductor integrated circuit device according to the second aspect, the control means includes a row address selection control signal and a column address which are control signals supplied from the logic circuit to the memory circuit. A first logic gate for inputting a selection control signal and a write enable signal, a D-flip-flop for receiving an output of the first logic gate and outputting in synchronization with a clock signal supplied from the logic circuit to the memory circuit; , A first delay circuit receiving the output of the D-flip-flop, a second delay circuit receiving the output of the first delay circuit, and an output of the second delay circuit and an output of the D-flip-flop. A second logic gate for inputting and outputting an output to a terminal for controlling output enable / disable states of the plurality of first tri-state buffers;
And a third logic gate which inputs the output of the delay circuit, inverts the output, and inputs the output to a terminal for controlling the output enable / disable state of the plurality of second tristate buffers.

According to the third aspect, the control means of the second aspect can be specifically configured.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device in which a DRAM unit and a logic unit according to an embodiment of the present invention are integrated on the same semiconductor chip. In the figure, reference numeral 100 denotes a DRAM unit,
01 is a memory circuit comprising a memory cell array and peripheral circuits, 102 is a first logic gate, 103 is a D-flip-flop, 104 is a DRAM unit data output circuit, 105
Is a first delay circuit, 106 is a second delay circuit, 107 is a second logic gate which is an AND gate, and 108 is a third logic gate which is an inverter. 200 is a logic unit, 201 is a logic circuit, 202 is a logic unit data output circuit, and 300 is a common I / O bus between the DRAM unit and the logic unit.

In the semiconductor integrated circuit device according to the embodiment of the present invention, the conventional power-on reset signal generating circuit 1 shown in FIG.
10 and the bus hold circuit 301 are not provided. Then, the output of the D-flip-flop 103 is AND-ed via the first delay circuit 105 and the second delay circuit 106.
The output of the D-flip-flop 103 is directly input to the second logic gate 107, and the output of the second logic gate 107 constitutes the DRAM part data output circuit 104. It is used as a DRAM unit data output control signal D for controlling the output enable / disable state of the tristate buffer 109. Further, the output of the first delay circuit 105 is inverted by a third logic gate 108 which is an inverter,
The inverted output is used as a logic section data output control signal E for controlling the output enable / disable state of the tristate buffer 203 constituting the logic section data output circuit 202. Other configurations are the same as in the conventional example.

The control means includes a first logic gate 10
2, a D-flip-flop 103, a first delay circuit 105, a second delay circuit 106, a second logic gate 107 as an AND gate, and a third logic gate 108 as an inverter. Is done. Further, the first logic gate 102 is formed of a three-input AND gate as in the prior art, inputs the row address selection control signal / RAS and the column address selection control signal / CAS in reverse, and inputs the write enable signal / WE ( The output is input to the D-flip-flop 103, and the clock input signal CL
It is output in synchronization with K (output B).

FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit device having the configuration shown in FIG. 1 according to the embodiment of the present invention.

First, when the power is turned on, the D-flip-flop 103 is not initialized as in the prior art, and
The level of the M section data output control signal D becomes undefined. Here, when the DRAM unit data output control signal D is at “H” level, the n tri-state buffers 109 constituting the DRAM unit data output circuit 104 are enabled, so that the output data DO ( 0) to DO
(n-1) is output to the I / O bus 300. In this case, since the output C of the first delay circuit 105 is at "H" level, the output of the third logic gate 108 is at "L" level. Therefore, n tristate buffers 203 constituting the logic part data output circuit 203 connecting the logic circuit 201 and the I / O bus 300 are disabled, and the output data DOL (0) to DO of the logic circuit 201 are disabled.
L (n-1) is not output to the I / O bus 300. Therefore DR
The output data of the AM unit 100 and the logic unit 200 does not collide with the bus.

When the DRAM section data output control signal D is at "L" level, the DRAM section data output circuit 10
4 n-state buffers 109
Is disabled, so that the output data DO (0) to DO (n-1) of the memory circuit 101 are not output to the I / O bus 300. In this case, since the output C of the first delay circuit 105 is at "L" level, the output of the third logic gate 108 is at "H" level. Therefore, the logic circuit 201 and I /
The logic unit data output circuit 203 connected to the O bus 300 is enabled, and the output data DOL (0) to DOL (n-1) of the logic circuit 201 are output to the I / O bus 300.
Output to Also in this case, the output data of the DRAM unit 100 and the logic unit 200 does not collide with the bus.

In order to prevent bus collision due to signal skew, the output of the first delay circuit 105 connected to the output of the D-flip-flop 103 is input to the input of the third logic gate 108, The output of the gate 108 is used as the logic part data output control signal E, and the DRAM part data output control signal D is output from the second logic gate 107 which takes the logical product of the second delay circuit 106 and the output of the D flip-flop 103. It is configured to be. As a result, the output of the second logic gate 107 changes from “L” to “H”.
Becomes "H" level later than the output of the first delay circuit 105, and the DRAM unit data output control signal D
The logic section data output control signal E is disabled (FIG. 2) before is enabled (FIG. 2). When the output of the second logic gate 107 changes from “H” to “L”, the output of the second delay gate 105 goes to “L” before the output of the first delay circuit 105, and the logic unit data output control signal E is enabled ( DR before it becomes
The AM section data output control signal D is disabled (FIG. 2).

With the above configuration, even if the data output control signals D and E are indefinite at power-on, the DR
The output data of the AM unit 100 and the logic unit 200 does not collide.

Next, in the read / write cycle of the DRAM section, control signals such as / RAS, / CAS, / WE, and address (n bits) are latched in synchronization with the rising edge of the clock input signal CLK, and the DRAM section is read. 100
Data transfer between the logic units 200 is performed.

First, in a read cycle, a row address (of FIG. 2) and a column address (of FIG. 2) are fetched every clock cycle in synchronization with a rising edge of a clock input signal CLK. Is operated, so that the data of the selected address is output at the clock edge of FIG. At this time, since the row address selection control signal / RAS is "L", the column address selection control signal / CAS is "L", and the write enable signal / WE is "H", the output A of the logic gate 102 is "H". 4 and the D-flip-flop 103 at the clock 0 edge in FIG.
The output B of the DRAM section goes high and the output control signal D goes high.
Is enabled, and read data from the DRAM unit 100 is output onto the I / O bus 300. At this time, the logic unit data output control signal E is disabled, so that the logic unit 200 sends the I / O bus 300
There is no data output up.

Similarly, in the DRAM section write cycle,
Control signals such as / RAS, / CAS, / WE, and address are latched in synchronization with the rising edge of the clock input signal CLK.
Is always at "L" level, the DRAM unit data output circuit 104 is disabled, and there is no output from the DRAM unit 100. In this state, the logic unit data output control signal E is in the enable state.
0 is output from the DRA through the I / O bus 300.
Written in M section 100.

As described above, according to the present embodiment, when the power is turned on, the first logic gate 102, the D flip-flop 103, the first delay circuit 105, and the second delay circuit 1
06, the second logic gate 107 and the third logic gate 10
8, the data output circuits 104 and 20 of both the DRAM section 100 and the logic section 200 are provided.
2 is controlled so that the enable / disable state is different, so that the I / O bus 3
The data output to 00 and the data output from the logic unit 200 to the I / O bus 300 do not occur at the same timing, and bus collision can be prevented without using a power-on reset circuit. Also, the DRAM unit 100 and the logic unit 20
Since one of the data 0 always appears on the I / O bus 300, there is no need to fix the previous state. Therefore, the high impedance state of the I / O bus 300 can be prevented without using a bus hold circuit. Therefore, since a power-on reset circuit having a large circuit scale and bus hold circuits corresponding to the number of I / Os are not used, the area of the semiconductor integrated circuit device can be reduced.

Further, using two delay circuits 105 and 106 and a second logic gate 107, the DRAM section data output control signal D and the logic section data output control signal E are delayed so that the DRAM section output enable timing is changed to the logic section. By delaying the output enable timing from the output disable timing and delaying the logic unit output enable timing from the DRAM unit output disable timing, the I / O due to signal skew at the time of switching between the output enable / disable of the DRAM unit and the logic unit is performed. Since the bus collision is prevented from occurring, the bus collision can be controlled stably and reliably.

In the above embodiment, as shown in FIG. 1, the control means (102, 103, 105, 106,
All of the components 107 and 108) are provided in the DRAM unit 100, but the present invention is not limited to this. For example, the third logic gate 108 is provided in the logic unit 200, and the other elements (102, 103, 105, 106, 107) are D
You may make it provide in RAM part 100. The control means (102, 103, 105, 106, 107, 10)
All the components of 8) may be provided in the logic unit 200.

[0032]

As described above, according to the present invention, the output enable / disable state of the plurality of first tristate buffers and the plurality of output states of the plurality of first tristate buffers in response to the control signal and the clock signal supplied from the logic circuit to the memory circuit are determined. By providing control means for performing switching control so that the output enable / disable state of the second tri-state buffer is different, when the power is turned on, the data of both the memory circuit and the logic circuit are shared at the same timing by the common I / O bus. It is not output upward and bus collision can be prevented without using a power-on reset circuit as in the related art.

Further, since either the data of the memory circuit or the data of the logic circuit always appears on the common I / O bus, the high impedance state of the I / O bus is prevented without using the conventional bus hold circuit. be able to.

Accordingly, since a power-on reset circuit having a large circuit scale and bus hold circuits corresponding to the number of I / Os are not used, the area of the semiconductor integrated circuit device can be reduced.

Further, the control means disables the outputs of the plurality of second tri-state buffers before enabling the outputs of the plurality of first tri-state buffers and outputs the outputs of the plurality of second tri-state buffers. Disables the outputs of the plurality of first tri-state buffers before enabling the first tri-state buffer and the second tri-state buffer. Bus collisions can be prevented.

In particular, the above effect is great in a semiconductor device which incorporates various kinds of peripheral circuits in a system LSI which will be miniaturized in the future.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 3 is a block diagram showing an overall configuration of a conventional semiconductor integrated circuit device.

FIG. 4 is a timing chart showing an operation of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 DRAM section 101 memory circuit 102 first logic gate 103 D-flip-flop 104 DRAM section data output circuit 105 first delay circuit 106 second delay circuit 107 second logic gate 108 third logic gate 109 DRAM section Tristate buffer 200 Logic section 201 Logic circuit 202 Logic section data output circuit 203 Logic section tristate buffer 300 I / O bus

Claims (3)

[Claims] 1. A memory circuit, a logic circuit, a plurality of first tri-state buffers connected to each of a plurality of outputs from the memory circuit, and a plurality of outputs from the logic circuit. Common I / O bus comprising a plurality of second tri-state buffers, and a plurality of signal lines respectively connected to outputs of the plurality of first tri-state buffers and outputs of the plurality of second tri-state buffers. Output enable / disable state of the plurality of first tristate buffers and output enable of the plurality of second tristate buffers in response to a control signal and a clock signal supplied from the logic circuit to the memory circuit. A semiconductor integrated circuit device having control means for performing switching control so as to be different from the disabled state. 2. The control unit disables the outputs of the plurality of second tri-state buffers before enabling the outputs of the plurality of first tri-state buffers, and controls the plurality of second tri-state buffers. 2. The semiconductor integrated circuit device according to claim 1, wherein the outputs of the plurality of first tri-state buffers are disabled before the output of the state buffer is enabled. A first logic gate for inputting a row address selection control signal, a column address selection control signal, and a write enable signal, which are control signals supplied from the logic circuit to the memory circuit; A D-flip-flop receiving an output of the first logic gate and outputting the same in synchronization with a clock signal supplied from the logic circuit to the memory circuit; and a first inputting an output of the D-flip-flop. A delay circuit; a second delay circuit for receiving an output of the first delay circuit; a delay circuit for receiving an output of the second delay circuit and an output of the D-flip-flop; A second logic gate input to a terminal for controlling the output enable / disable state of the tri-state buffer, and an output of the first delay circuit, and inverting the It is possible to output a plurality of second tri-state buffers.
3. The semiconductor integrated circuit device according to claim 2, further comprising a third logic gate input to a terminal for controlling a disabled state.