JP4487738B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit in which a circuit is configured by connecting a plurality of circuit cells serving as basic structural units, such as a structured ASIC.

  A structured ASIC is an IC that uses a circuit cell having a coarser grain structure than a basic gate such as a NAND circuit as the minimum structural unit of a circuit.

For example, “Regular logic fabrics for a via patterned gate array (VPGA), CMU KYTong, IBM R. Puri, IEEE 2003 Custom integrated circuits conference” is a typical paper on the basic logical building blocks of structured ASICs. In this paper, a basic structural unit is configured by using a 3-input lookup table, a scan flip-flop, two 3-input NAND circuits, and seven buffers.
Patent Document 1 proposes a logic cell in which a NAND circuit is connected to an input of a lookup table.

Unlike a field programmable gate array (FPGA), a structured ASIC can configure a circuit having a desired function by mask routing that customizes a part of wiring according to the application. Reconfigurable wiring structure in FPGA is very wasteful, but by replacing it with mask routing, it is possible to develop a circuit that is less wasteful than FPGA, but less wasteful than FPGA. There is a merit.
US Pat. No. 6,236,229

  By the way, each of the basic logical structural units of the structured ASIC proposed in the above-mentioned paper and Patent Document 1 includes a NAND circuit. For example, digital circuits, such as multipliers, generally use NAND operations as basic logic operations. Therefore, the entire circuit size can be reduced by incorporating a NAND circuit with a small circuit size in the basic logic configuration unit in advance. be able to. In addition, since the NAND circuit operates at a higher speed than the look-up table, the performance of the circuit operation speed can be improved.

However, since the conventional basic structural unit described above is obtained by simply adding a NAND circuit to a component such as a lookup table, for example, when only the lookup table is used, the added NAND circuit is unnecessary. As a result, there is a disadvantage that unused circuit elements are unused.
Since waste generated in the basic structural unit affects the entire integrated circuit, it is desirable to reduce it as much as possible.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor integrated circuit capable of reducing waste of circuit cells serving as basic structural units and suppressing an increase in circuit size.

A semiconductor integrated circuit according to a first aspect of the present invention is a semiconductor integrated circuit configured by connecting a plurality of circuit cells whose logic functions can be adaptively configured, the circuit cell including a first input terminal and A plurality of input terminals including a plurality of second input terminals, a first output terminal, and a signal corresponding to a logic function configured in the circuit cell from a predetermined signal group, respectively, or the circuit a plurality of nodes that are insulated from the first input terminal in accordance with the logic function configured in the cell, among the above SL plurality of nodes, selected according to a signal input from at least some of said plurality of input terminals A selection circuit for connecting the node and the first input terminal , a plurality of first wirings formed in the first wiring layer and connected to the plurality of nodes, and a second wiring covering the first wiring layer The predetermined signal group formed in the layer A plurality of second wirings for transmitting each signal and any one of the plurality of second wirings are selectively connected to the first wiring via a via according to a logic function configured in the circuit cell. a lookup table having one or more third wiring and to, when the in the via is not formed first terminals are insulated from the plurality of nodes, is input from the upper Symbol plurality of second input terminals And calculates the inverted logical product of the signals, outputs the inverted logical product to the first output terminal, forms the via, and connects the first terminal to at least one of the plurality of nodes for lookup. when operating as a table, the look-signal selected by the up tables are supplied from the output terminal of the look-up table, first logic having a buffer function for amplifying and outputting the supplied signal And a road.

The circuit cell may further include an inverter circuit that logically inverts a signal input from a predetermined input terminal among the plurality of input terminals. The predetermined signal group may include an input signal and an output signal of the first inverter circuit.
The circuit cell may further include a first amplifier circuit that amplifies a signal input from the predetermined input terminal and inputs the signal to the inverter circuit. The predetermined signal group may include a signal amplified in the first amplifier circuit.

The selection circuit is inserted into a signal path between the plurality of nodes and the second input terminal, and is set on or off according to a signal input from at least a part of the plurality of input terminals. A plurality of switches may be included.
The switch may include, for example, an n-channel insulated gate transistor.
Alternatively, the switch may include an n-channel insulated gate transistor and a p-channel insulated gate transistor connected in parallel and driven to be turned on or off in common.

The circuit cell includes a second logic circuit that calculates and outputs an inverted logical product of signals input from at least some of the plurality of input terminals, and outputs an output signal of the second logic circuit to the outside of the circuit cell. And a second output terminal that outputs to the output. The selection circuit may include a selection element that is inserted into a signal path between the plurality of nodes and the first input terminal and selects and outputs one of the two input signals. The selection element is connected between a first input node and a second input node, an output node, the first input node and the output node, and is selected from among a plurality of signals input to the second logic circuit A first switch that is turned on when the predetermined signal has a first value and turned off when the predetermined signal has a second value obtained by logically inverting the first value, the second input node, and the output node And a second switch that is turned on when the output signal of the second logic circuit has the first value and turned off when the output signal has the second value.
In this case, the circuit cell further includes a wiring for connecting a wiring for transmitting the output signal of the second logic circuit and at least a part of the plurality of input terminals according to a logic function configured in the circuit cell. You may have.

The circuit cell may further include a third logic circuit that calculates and outputs an inverted logical product of signals input from at least a part of the plurality of input terminals. The predetermined signal group may include an output signal of the third logic circuit and at least one of a plurality of signals input to the third logic circuit.
In this case, the circuit cell may further include a third amplifier circuit that amplifies a signal input from the input terminal and inputs the signal to the third logic circuit. The predetermined signal group may include a signal amplified in the third amplifier circuit.
The circuit cell may further include a third output terminal that outputs an output signal of the third logic circuit to the outside of the circuit cell.
The circuit cell further includes a wiring for connecting a wiring for transmitting an output signal of the third logic circuit and at least a part of the plurality of input terminals according to a logic function configured in the circuit cell. You may do it.

A semiconductor integrated circuit according to a second aspect of the present invention is a semiconductor integrated circuit configured by connecting a plurality of circuit cells whose logic functions can be adaptively configured, and the circuit cell includes a plurality of input terminals. ,
A first output terminal, from among the predetermined signal group, among signals input a signal corresponding to the configured logic function to the circuit cells and a plurality of nodes respectively input, on SL plurality of nodes, the A selection circuit that outputs a signal selected according to a signal input from at least a part of the plurality of input terminals to the first output terminal, and a plurality of circuits formed in the first wiring layer and connected to the plurality of nodes. One of the plurality of second wirings formed on the first wiring layer, the second wiring layer covering the first wiring layer, and transmitting each signal of the predetermined signal group, and the plurality of second wirings. A lookup table having one or a plurality of third wirings selectively connected to the first wiring according to a logic function configured in the circuit cell via a via, and the via is not formed The first terminal is connected to the plurality of nodes. When, by calculating the inverted logical product between the signals to be input to at least a portion of said plurality of input terminals and an output, the vias are formed by the first terminal at least one of said plurality of nodes A logic circuit having a buffer function for amplifying and outputting the supplied signal when the signal selected by the lookup table is supplied from the output terminal of the lookup table when connected and operated as a lookup table ; A second output terminal for outputting an output signal of the logic circuit to the outside of the circuit cell, and the selection circuit is inserted in a signal path between the plurality of nodes and the first output terminal, A selection element that selects and outputs one of the two input signals, the selection element including a first input node, a second input node, an output node, and the first input node; Is turned on when a predetermined signal has a first value among a plurality of signals input to the logic circuit, and the second value is obtained by logically inverting the first value. A first switch that is turned off when it has a value of N, and is connected between the second input node and the output node, and is turned on when an output signal of the logic circuit has the first value. And a second switch that is turned off when it has a value of 2.

  The circuit cell may further include a wiring for connecting a wiring for transmitting an output signal of the logic circuit and at least a part of the plurality of input terminals according to a logic function configured in the circuit cell. .

The circuit cell may further include an inverter circuit that logically inverts a signal input from a predetermined input terminal among the plurality of input terminals. The predetermined signal group may include an input signal and an output signal of the first inverter circuit.
In this case, the circuit cell may further include a first amplifier circuit that amplifies a signal input from the predetermined input terminal and inputs the signal to the inverter circuit. The predetermined signal group may include a signal amplified in the first amplifier circuit.

  The circuit cell may further include a second amplifier circuit that amplifies the signal selected by the selection circuit and outputs the amplified signal to the first output terminal.

The first switch and the second switch may each include, for example, an n-channel insulated gate transistor.
Alternatively, the first switch and the second switch may include an n-channel insulated gate transistor and a p-channel insulated gate transistor that are connected in parallel and are driven to be turned on or off in common.

The circuit cell may further include a third logic circuit that calculates and outputs an inverted logical product of signals input from at least a part of the plurality of input terminals. The predetermined signal group may include an output signal of the third logic circuit and at least one of a plurality of signals input to the third logic circuit.
In this case, the circuit cell may further include a third amplifier circuit that amplifies a signal input from the input terminal and inputs the signal to the third logic circuit. The predetermined signal group may include a signal amplified in the third amplifier circuit.
The circuit cell may further include a third output terminal that outputs an output signal of the third logic circuit to the outside of the circuit cell.
The circuit cell further includes a wiring for connecting a wiring for transmitting an output signal of the third logic circuit and at least a part of the plurality of input terminals according to a logic function configured in the circuit cell. You may do it.

  According to the present invention, it is possible to reduce the waste of circuit cells and suppress an increase in circuit size by providing a circuit having a NAND operation function together with a logic inversion function necessary in the circuit cell.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an example of the configuration of a semiconductor integrated circuit according to an embodiment of the present invention.
The semiconductor integrated circuit shown in FIG. 1 has mxn circuit cells C11 to Cmn. The circuit cells C11 to Cmn are arranged in a matrix of m rows and n columns, for example, as shown in FIG.

Each circuit cell has a coarser structure than a basic gate such as a NAND circuit, and each logic function can be configured adaptively. That is, it is possible to give an independent logic function to each circuit cell.
The logic function program for each circuit cell is performed, for example, by forming an independent program wiring (via, etc.) for each circuit cell.
Also, the connection between circuit cells is performed by connecting wirings having a predetermined regular structure with wirings such as vias, as in the programming method for circuit cells. This wiring structure will be described in detail later with reference to FIG.

FIG. 2 is a diagram illustrating a first configuration example of the circuit cell.
The circuit cell shown in FIG. 2 includes input terminals A, B, C, D1, and D2, output terminals Y1 and Y1b, test input terminals Ta, Tb, Tc, and Td2, and n-channel MOS transistors Qn1, .., Qn13, Qn14-2, Qn15, a p-channel MOS transistor Qp7, inverter circuits INV1,..., INV4, and a NAND circuit U1.

The input terminals A, B, C, D1, and D2 are an embodiment of the input terminal of the present invention.
Input terminals N1 to N4 are an embodiment of the first input terminal of the present invention.
The input terminals D1 and D2 are an embodiment of the second input terminal of the present invention.
The output terminal Y1 is an embodiment of the first output terminal of the present invention.
The NAND circuit U1 is an embodiment of the first logic circuit of the present invention.
The circuit including the transistors Qn1 to Qn6 is an embodiment of the selection circuit of the present invention.
Transistors Qn1-Qn6 are an embodiment of an n-channel insulated gate transistor of the present invention.
The inverter circuit INV4 is an embodiment of the inverter circuit of the present invention.

Input terminals A, B, C, D1, and D2 input signals from outside the circuit cell (other circuit cells, input / output circuits, etc.).
The output terminals Y1 and Y1b output signals to the outside of the circuit cell.

The inverter circuit INV2 logically inverts the signal input to the input terminal A and outputs it.
The inverter circuit INV3 logically inverts the signal input to the input terminal B and outputs it.
The inverter circuit INV4 logically inverts the signal input to the input terminal C and outputs it.

Transistor Qn1 is connected between nodes N1 and N6.
Transistor Qn2 is connected between nodes N2 and N6.
Transistor Qn3 is connected between nodes N3 and N7.
Transistor Qn4 is connected between nodes N4 and N7.
Transistor Qn5 is connected between nodes N6 and N5.
Transistor Qn6 is connected between nodes N7 and N5.
Node N5 is connected to input terminal D1.
The gates of transistors Qn1 and Qn3 are connected to input terminal B.
The gates of the transistors Qn2 and Qn4 are connected to the output of the inverter circuit INV3 that logically inverts the signal of the input terminal B.
The gate of the transistor Qn5 is connected to the input terminal A.
The gate of the transistor Qn6 is connected to the output of the inverter circuit INV2 that logically inverts the signal at the input terminal A.

  The NAND circuit U1 calculates the inverted logical product of the signals input from the input terminals D1 and D2, and outputs the inverted logical product to the output terminal Y1.

The transistor Qp7 pulls up the node N5 when the output of the NAND circuit U1 is at a low level.
Transistor Qp7 has its source connected to power supply voltage VDD, its drain connected to node N5, and its gate connected to the output of NAND circuit U1.

  The inverter circuit INV1 logically inverts the signal at the output terminal Y1 and outputs it to the output terminal Y1b.

Nodes N1 to N4 correspond to a plurality of nodes of the present invention. That is, each of the nodes N1 to N4 inputs a signal corresponding to the logic function configured in the circuit cell from a predetermined signal group, or the input terminal D1 according to the logic function configured in the circuit cell. Insulated from.
The logical relationship between signals input to the input terminals A, B, C, D1, and D2 and signals output from the output terminals Y1 and Y1b is determined by a combination of signals input to the nodes N1 to N4.

Symbols P11 ',..., P14', P21 ', ..., P24', P31 ', ..., P34', P41 ', ..., P44' in FIG. The creation position of the via for inputting various signals is shown.
Vias for applying the power supply voltage VDD to the nodes N1 to N4 are created at the positions P11 to P41.
At positions P12 to P42, vias for applying the reference potential VSS to the nodes N1 to N4 are created.
At positions P13 to P43, vias for connecting the nodes N1 to N4 and the input terminal C are created.
At positions P14 to P44, vias for connecting the nodes N1 to N4 and the output of the inverter circuit INV4 are created.

  Transistors Qn7 to Qn13, Qn14-2 constitute a circuit for inputting a test signal to the circuit cell in an operation mode (hereinafter referred to as a test mode) for inspecting the circuit cell.

The transistor Qn7 is connected between the test signal input terminal Ta and the input terminal A.
The transistor Qn8 is connected between the test signal input terminal Tb and the input terminal B.
The transistor Qn9 is connected between the test signal input terminal Tc and the input terminal C.
Transistor Qn10 is connected between the output of inverter circuit INV4 and node N1.
Transistor Qn11 is connected between the output of inverter circuit INV4 and node N2.
Transistor Qn12 is connected between the output of inverter circuit INV4 and node N3.
Transistor Qn13 is connected between the output of inverter circuit INV4 and node N4.
The transistor Qn14-2 is connected between the test signal input terminal Td2 and the input terminal D2.
The gates of the transistors Qn7 to Qn13, Qn14-2 are commonly connected to a terminal Tmod that is set to a high level in the test mode.

Transistor Qn15 outputs the output signal of the circuit cell to test output line SL in the test mode.
The drain of the transistor Qn15 is connected to the output terminal Y1b, its source is connected to the inspection output line SL, and its gate is connected to the column selection line CL.

The column selection line CL is provided in each column of the circuit cell array shown in FIG. 1, and circuit cells belonging to the same column are connected to a common column selection line CL. The inspection output line SL is provided in each row of the circuit cell array, and circuit cells belonging to the same row are connected to a common inspection output line SL.
When the column selection line CL of a certain column in the column selection circuit 100 described later is set to a high level, the transistor Qn15 of the circuit cell belonging to this column is turned on, and the signal of the output terminal Y1b of the circuit cell passes through the transistor Qn15. Is output to the inspection output line SL.

Here, the operation of the circuit cell shown in FIG. 2 having the above-described configuration will be described.
In the following description, the signal of the power supply voltage VDD is a logical value 1 ′, and the signal of the reference potential VSS is a logical value 0 ′. Further, signals input to the input terminals A, B, C, D1, and D2 are symbols a ′, b ′, c ′, d1 ′, and d2 ′, and signals output from the output terminals Y1 and Y1b are symbols y1 ′, This is represented by y1b ′. Further, the logical product is represented by a symbol · ′, the logical sum is represented by a symbol + ′, and the logical inversion is represented by a symbol / ′.

  The circuit of the transistors Qn1 to Qn6 connected in a tree shape selectively connects one of the nodes N1 to N4 to the node N5 according to two input signals (a ′, b ′).

Here, the circuit of transistors Qn1 and Qn2 is called a first selection element, the circuit of transistors Qn3 and Qn4 is called a second selection element, and the circuit of transistors Qn5 and Qn6 is called a third selection element.
The first selection element selects either the node N1 or the node N2 in accordance with the input signal b and its logical inversion signal / b and connects it to the node N6. That is, the node N1 and the node N6 are connected when the signal b = 1 ′, and the node N2 and the node N6 are connected when the signal b = 0 ′.
The second selection element selects either the node N3 or the node N4 in accordance with the input signal b and the logical inversion signal / b, and connects to the node N7. That is, the node N3 and the node N7 are connected when the signal b = 1 ′, and the node N4 and the node N7 are connected when the signal b = 0 ′.
The third selection element selects either the node N6 or the node N7 in accordance with the input signal a and the logical inversion signal / a, and connects it to the node N5. That is, when the signal a = 1 ′, the node N6 and the node N5 are connected, and when the signal a = 0 ′, the node N7 and the node N5 are connected.
Therefore, the node N1 when the signal a = 1 ′ and the signal b = 1 ′, the node N2 when the signal a = 1 ′ and the signal b = 0 ′, the node N3 when the signal a = 0 ′ and the signal b = 1 ′, When the signal a = 0 ′ and the signal b = 0 ′, the node N4 is selected and connected to the node N5.

On the other hand, each of the nodes N1 to N4 has four kinds of signals {1 ′, 0 ′, c ′, / c ′}.
One signal corresponding to the via created at positions P11 to P44 is input. For example, when a via is created at the position P11, the node N1 inputs a signal of 1 ′.

Accordingly, when two input signals (a ′, b ′) are given, any one of the nodes N1 to N4 is selected in accordance with the two input signals (a ′, b ′), and four kinds of signals {1 ′, 0 are selected from the selected node. ', C', / c '}
Is input to node N5.
For example, when a via is created at the position P11, a signal 1 ′ is input to the node N5 by inputting the signal A = 1 ′ and the signal B = 1 ′. In this case, signals of output terminals Y1 to 0 ′ and output terminals Y1b to 1 ′ are output.

  The signal y1b at the output terminal Y1b is expressed by the following logical expression.

In Expression (1), symbols n1 ′ to n4 ′ indicate signals of the nodes N1 to N4. The signals n1 to n4 are four kinds of signals {1 ′, 0 ′, c ′, / c) ′}, respectively.
It corresponds to either.

By the way, in general, when a 3-bit input signal is given, a 3-input lookup table selects and outputs one signal corresponding to the input signal from 8 kinds of signals stored in the table in advance. When 2 bits of the 3-bit input signal are given, the lookup table outputs a signal whose value changes according to the remaining 1-bit input signal or a signal having a fixed value. If the remaining 1-bit signal is represented by the symbol c ′, the lookup table has four signals {1 ′, 0 ′, c ′, / c ′}.
Any one of these is output.
That is, the three-input lookup table has four signals {1 ′, 0 ′, c ′, / c ′} when two input signals are given.
Any one of these is output.
Therefore, it can be seen that the circuit cell shown in FIG. 2 operates as a lookup table having three inputs (A, B, C).

  Next, the operation of the circuit cell shown in FIG. 2 in the test mode will be described.

  The test of the circuit cell is performed, for example, after forming the circuit cell on the semiconductor substrate and before forming a program wiring (such as a via) for determining the logic function of the circuit cell or a connection wiring between the circuit cells.

  In the test mode, the terminal Tmod is set to a high level by an inspection device (not shown), and the transistors Qn7 to Qn13 and Qn14-2 are set to an on state. In addition, a test signal is input from an inspection apparatus (not shown) to the inspection input terminals Ta, Tb, Tc, and Td2. In order to read out the inspection result corresponding to the test signal, the column selection line CL is selectively set to the high level by the column selection circuit 100 described later.

When the transistors Qn7, Qn8, Qn9, and Qn14-2 are turned on, test signals are input from the input terminals Ta, Tb, Tc, and Td2 to the input terminals A, B, C, and D2.
Test signals at input terminals Ta and Tb set the on / off states of transistors Qn1-Qn6. That is, the connection state between the nodes N1 to N4 and the node N5 is set.
The test signal at the input terminal Td2 sets the operating state of the NAND circuit U1. That is, when a 1 ′ test signal is input to the input terminal Td2, the NAND circuit U1 operates as an inverter that logically inverts the signal of the node N5. When a 0 'test signal is input to the input terminal Td2, the NAND circuit U1 always outputs a 1' signal.

  On the other hand, when the transistors Qn10 to Qn13 are turned on, the output signal of the inverter circuit INV4 is input to the nodes N1 to N4, respectively. Since the output signal of the inverter circuit INV4 has a value corresponding to the test signal at the input terminal Tc, the signal values at the nodes N1 to N4 are all set to 1 'or all 0' according to the test signal at the input terminal Tc. The

When the transistors Qn1 to Qn6 and the inverter circuits INV2 to INV4 are operating normally, a signal having a value corresponding to the test signal at the input terminal Tc is input to the nodes N1 to N4. The connection state between the nodes N1 to N4 and the node N5 is set according to the test signals at the input terminals Ta and Tb. Therefore, a signal corresponding to the test signals of the input terminals Ta, Tb, and Tc is generated at the node N5.
Further, when the NAND circuit U1, the transistor Qp7 and the inverter circuit INV1 are operating normally, when a test signal of 1 ′ is input to the input terminal Td2, a signal having the same value as that of the node N5 is generated at the output terminal Y1b. When a 0 'test signal is input to the input terminal Td2, a 1' signal is generated at the output terminal Y1.
Therefore, when each element in the circuit cell is operating normally, a signal corresponding to the test signals of the input terminals Ta, Tb, Tc, and Td2 is generated at the output terminal Y1b.
When a column is selected by the column selection circuit 100 and the column selection line CL of that column is set to a high level, the transistor Qn15 of the circuit cell belonging to the column is turned on. As a result, a signal generated at the output terminal Y1b of the circuit cell belonging to the column is output to the inspection output line SL of each row via the transistor Qn15. The signal output to the inspection output line SL is taken into an inspection device (not shown) and inspected whether or not it has a value corresponding to the test signal. The quality of each circuit cell can be determined by inspecting the signal on the inspection output line SL while variously changing the test signals supplied to the input terminals Ta, Tb, Tc, and Td2.

  In the circuit cell shown in FIG. 2, the node N5 is electrically connected to any one of the nodes N1 to N4 through a selection circuit including transistors Qn1 to Qn6, and is also electrically connected to the input terminal D1. . Therefore, in order to logically determine the signal level of the node N5, it is necessary to electrically insulate the nodes N1 to N4 from the input terminal D1.

  This electrical insulation is achieved, for example, by opening the input terminal D1 without connecting it to another circuit cell. When a fixed value 1 ′ is input to the input terminal D2 in this state, the NAND circuit U1 operates as an inverter circuit that logically inverts the signal of the node N5 and outputs it to the output terminal Y1. In this case, as can be seen from the equation (1), the circuit cell shown in FIG. 2 operates as a three-input lookup table using the input terminals A, B, and C as inputs.

  Further, the electrical insulation between the nodes N1 to N4 and the input terminal D1 can also be achieved by opening the nodes N1 to N4 and insulating them from the power supply voltage VDD and the reference potential VSS. That is, the nodes N1 to N4 and the input terminal D1 can be insulated by creating no vias at any of the positions P11 to P44. In this case, the output signals from the output terminals Y1 and Y1b are the inverted logical product or logical product of the signals input from the input terminals D1 and D2.

  As described above, according to the circuit cell shown in FIG. 2, the NAND operation function is added to the circuit cell by the NAND circuit U1 built in the circuit cell in advance. The NAND operation is a basic operation frequently used in various digital circuits, as will be described later by taking a multiplier as an example. Therefore, by incorporating the NAND circuit in the basic structural unit circuit cell in advance, the circuit cell can be used efficiently, and the overall circuit size of the semiconductor integrated circuit can be suppressed.

  Since the NAND circuit operates at a higher speed than the lookup table, the operation speed of the circuit can be improved by incorporating the NAND circuit in the circuit cell.

  In addition, since the NAND circuit is a circuit having a small size that can be configured by, for example, four transistors, the size of the circuit cell can be reduced as compared with the case where a function equivalent to this is realized by a lookup table.

  Further, in the circuit cell shown in FIG. 2, the NAND circuit U1 has a function of performing a NAND operation on the input signals from the input terminals D1 and D2, and a buffer for amplifying the output of the selection circuit composed of the transistors Qn1 to Qn6. It also has a function as an amplifier. Therefore, it is possible to use the circuit elements more efficiently than in the system in which the NAND circuit is simply added to the circuit cell. As a result, unused circuit elements can be reduced, and the overall circuit size of the semiconductor integrated circuit can be suppressed.

  Next, a second configuration example of the circuit cell will be described.

FIG. 3 is a diagram illustrating a second configuration example of the circuit cell. The difference from the circuit cell shown in FIG. 2 is that an inverter circuit INV5 is inserted into the input of the inverter circuit 4, and an output node Cb of the inverter circuit INV5 is connected to the nodes N1 to N4.
The inverter circuit INV5 is an embodiment of the first amplifier circuit of the present invention.

  The inverter circuit INV5 is inserted in a signal path from the input terminal C to the inverter circuit INV4. The signal of the input terminal C is logically inverted and input to the inverter circuit INV4. The input of the inverter circuit INV5 is connected to the inspection input terminal Tc via the transistor Qn9.

At positions P13, P23, P33, and P43, vias that connect the output node Cb of the inverter circuit INV5 and the nodes N1 to N4 are formed. Vias that connect the output node Cbb of the inverter circuit INV4 and the nodes N1 to N4 are formed at the positions P14, P24, P34, and P44.
Therefore, each of the nodes N1 to N4 in the circuit cell shown in FIG. 3 has four kinds of signals {1 ′, 0 ′, / c ′, c ′}.
Enter one of these.

  In the circuit cell shown in FIG. 2, the nodes N1 to N4 and the input terminal C are directly connected through the programming vias formed at the positions P13, P23, P33, and P43. The node N5 is driven by a circuit outside the circuit cell via a wiring outside the circuit cell connected to the input terminal C and a switch (Qn1 to Qn6) inside the circuit cell. That is, the node N5 is driven by a circuit outside the circuit cell via a high impedance signal path including the resistance of the switch. For this reason, the delay of the signal propagating to the node N5 increases. On the other hand, in the circuit shown in FIG. 3, since the signal c input to the input terminal C is input to the nodes N1 to N4 via the inverter circuit INV5, the inverter circuit INV5 operates as a buffer amplifier, and the node N5 has a low impedance. Can be driven by. Therefore, according to the circuit cell shown in FIG. 3, the delay due to the resistance of the switches (Qn1 to Qn6) can be improved and the operation speed can be increased.

  Next, a third configuration example of the circuit cell will be described.

FIG. 4 is a diagram illustrating a third configuration example of the circuit cell. The difference from the circuit cell shown in FIG. 3 is that the p-channel MOS transistors Qp1 to Qp6 are connected in parallel to the n-channel MOS transistors Qn1 to Qn6, respectively, and the pull-up transistor Qp7 is deleted. It is in.
Transistors Qp1-Qp6 are an embodiment of a p-channel insulated gate transistor of the present invention.

Transistors Qn1 and Qp1, transistors Qn2 and Qp2, transistors Qn3 and Qp3, transistors Qn4 and Qp4, transistors Qn5 and Qp5, and transistors Qn6 and Qp6 are connected in parallel, respectively.
The gates of the transistors Qp1 and Qp3 are connected to the output of the inverter circuit INV3. The gates of the transistors Qp2 and Qp4 are connected to the input of the inverter circuit INV3. The gate of the transistor Qp5 is connected to the output of the inverter circuit INV2. The gate of the transistor Qp6 is connected to the input of the inverter circuit INV2.

The above-described parallel circuits of transistors (Qn1 and Qp1, Qn2 and Qp2, Qn3 and Qp3, Qn4 and Qp4, Qn5 and Qp5, Qn6 and Qp6) each operate as a transfer gate type switch. That is, since complementary signals having opposite polarities are input to the gates of the n-channel MOS transistor and the p-channel MOS transistor connected in parallel, the two transistors are turned on or off in common. Driven.
Therefore, when a high level signal is input to the gate of the n-channel MOS transistor and a low level signal is input to the gate of the p-channel MOS transistor, at least one of the two transistors is turned on.

  When an n-channel MOS transistor is used alone as a switch as in the circuit cells shown in FIGS. 2 and 3, when the source becomes a high potential, a voltage drop occurs due to the threshold level of the transistor. For example, when a via is created at the position P11 and the power supply voltage VDD is applied to the node N1, a threshold level voltage drop occurs in the transistors Qn1 and Qn5. Due to this voltage drop, the signal at the node N5 that has passed through the transistors Qn1 and Qn5 becomes lower than the power supply voltage VDD by the threshold level of two transistors. If the node N5 is not driven to a level sufficiently higher than the logical threshold value of the NAND circuit 1, the operation speed of the NAND circuit U1 and the power consumption are increased. Therefore, in the circuit cell shown in FIGS. A transistor Qp7 that pulls up the power supply voltage VDD is provided to assist the driving of the node N5 to a high level.

On the other hand, according to the circuit cell shown in FIG. 4, a transfer in which an n-channel MOS transistor and a p-channel MOS transistor are connected in parallel as a switch inserted in a signal path from the nodes N1 to N4 to the node N5. Since the gate type switch is used, the voltage drop due to the threshold level as described above does not occur. As a result, since the voltage drop of the switch is reduced, the pull-up transistor Qp7 at the node N5 can be omitted.
Further, since the resistance component of the switch is reduced and the input capacitance of the NAND circuit U1 can be driven at high speed, the operation speed can be increased as compared with the circuit cell shown in FIG.

  Next, a fourth configuration example of the circuit cell will be described.

  FIG. 5 is a diagram illustrating a fourth configuration example of the circuit cell. The circuit cell shown in FIG. 5 deletes the inverter circuits INV2 and INV3, transistors Qn7 and Qn8, input terminals A and B, and test input terminals Ta and Tb of the circuit cell shown in FIG. U3, n-channel MOS transistors Qn7-1, Qn7-2, Qn8-1, Qn8-2, input terminals A1, A2, B1, B2, output terminals Y2, Y3, test input terminals Ta1, Ta2, Tb1 , Tb2 are provided.

NAND circuits U2 and U3 are an embodiment of the second logic circuit of the present invention.
The output terminals Y2 and Y3 are an embodiment of the second output terminal of the present invention.
The circuit of transistors Qn1 and Qn2, the circuit of transistors Qn3 and Qn4, and the circuit of transistors Qn5 and Qn6 are an embodiment of the selection element of the present invention.
Transistors Qn1, Qn3, and Qn5 are an embodiment of the first switch of the present invention.
Transistors Qn2, Qn4, and Qn6 are an embodiment of the second switch of the present invention.

The NAND circuit U2 calculates an inverted logical product of the signals input to the input terminals A1 and A2, and outputs the calculation result to the output terminal Y2.
The NAND circuit U3 calculates an inverted logical product of the signals input to the input terminals B1 and B2, and outputs the calculation result to the output terminal Y3.
The output terminals Y2 and Y3 are terminals for outputting signals to the outside of the circuit cell, similarly to the output terminals Y1 and Y1b.

The gates of transistors Qn1 and Qn3 are connected to input terminal B1.
The gates of transistors Qn2 and Qn4 are connected to the output of NAND circuit U3.
The gate of the transistor Qn5 is connected to the input terminal A1.
The gate of transistor Qn6 is connected to the output of NAND circuit U2.

The wiring for transmitting the output signal of the NAND circuit U3 is connected to the input terminals A1 and A2 according to the logic function configured in the circuit cell.
Symbols P51 ′ and P52 ′ in FIG. 7 indicate creation positions of vias that connect the output of the NAND circuit U3 and the input terminals A1 and A2.

Transistors Qn7-1, Qn7-2, Qn8-1, and Qn8-2 constitute a circuit for inputting a test signal to the circuit cell in the test mode.
The transistor Qn7-1 is connected between the test signal input terminal Ta1 and the input terminal A1.
The transistor Qn7-2 is connected between the test signal input terminal Ta2 and the input terminal A2.
The transistor Qn8-1 is connected between the test signal input terminal Tb1 and the input terminal B1.
The transistor Qn8-2 is connected between the test signal input terminal Tb2 and the input terminal B2.
The gates of the transistors Qn7-1, Qn7-2, Qn8-1, and Qn8-2 are commonly connected to the terminal Tmod.
When the terminal Tmod is set to the high level in the test mode, the transistors Qn7-1, Qn7-2, Qn8-1, and Qn8-2 are turned on. Thereby, the test signals supplied to the input terminals Ta1, Ta2, Tb1, and Tb2 are input to the input terminals A1, A2, B1, and B2 through these transistors.

According to the circuit cell shown in FIG. 5 having the above-described configuration, the NAND circuit U2 outputs an inverted logical product of two signals input from the input terminals A1 and A2 from the output terminal Y2 to the outside of the circuit cell. The NAND circuit U3 outputs the inverted logical product of two signals input from the input terminals B1 and B2 from the output terminal Y3 to the outside of the circuit cell.
That is, the NAND circuits U2 and U3 can be independently connected to other circuit cells as circuits for performing a two-input NAND operation.
As described above, by incorporating a NAND circuit frequently used in a general logic circuit in a circuit cell in advance, it is possible to increase the use efficiency of the circuit cell. In addition, the operation speed of the circuit can be improved while suppressing the size of the circuit cell.

  When NAND operations are performed in NAND circuits U2 and U3, transistors Qn1 and Qn2, transistors Qn3 and Qn4, and transistors Qn5 and Qn6 may be turned on simultaneously. Therefore, it is necessary to create no via for the positions P11 to P44, or to create a via so that the nodes N1 to N4 are connected to a common signal (for example, the reference potential VSS). In this case, the circuit cell shown in FIG. 5 does not operate as a lookup table.

On the other hand, in the circuit cell shown in FIG. 5, when a signal having a fixed value 1 ′ is input to the input terminals A2 and B2, the NAND circuits U2 and U3 operate as inverter circuits that logically invert the input signals of the input terminals A1 and B1. To do. In this case, if the input terminals A1 and B1 are regarded as the input terminals A and B in the circuit cell of FIG. 3, the circuit cell shown in FIG. 5 is equivalent to the circuit cell shown in FIG.
Therefore, when the circuit cell shown in FIG. 5 operates as a lookup table, the NAND circuits U2 and U3 include the first selection element (Qn1, Qn2), the second selection element (Qn3, Qn4), and the third selection element (Qn5). , Qn6) is used as an inverter circuit for generating logic inversion signals necessary for driving.
As described above, when the circuit cell shown in FIG. 5 operates as a lookup table, the NAND circuit U1 is used as a buffer amplifier that amplifies the signal at the node N5.
In this way, in the circuit cell shown in FIG. 5, the NAND circuits U1 to U3 have both a logic inversion function and a NAND operation function necessary for the look-up table operation. Therefore, according to the circuit cell shown in FIG. 5, it is possible to use the circuit elements more efficiently than in the system in which the NAND circuit is simply added to the circuit cell. As a result, unused circuit elements can be reduced, and the overall circuit size of the semiconductor integrated circuit can be suppressed.

  Moreover, according to the circuit cell shown in FIG. 5, it is possible to arbitrarily connect the output of the NAND circuit U3 and the input terminals A1 and A2 by vias. This increases the degree of freedom of wiring inside the circuit cell and increases the types of logic functions that can be programmed into the circuit cell, thereby further improving the use efficiency of the circuit cell.

  Next, a fifth configuration example of the circuit cell will be described.

FIG. 6 is a diagram illustrating a fifth configuration example of the circuit cell. In the circuit cell shown in FIG. 6, the inverter circuit INV4, the transistor Qn9, the input terminal C, and the test input terminal Tc in the circuit cell shown in FIG. 5 are deleted. Instead, the NAND circuit U4, the inverter circuit INV6, and the transistor Qn9-1. , Qn9-2, input terminals C1, C2, output terminal Y4, and test input terminals Tc1, Tc2.
NAND circuit U4 is an embodiment of the third logic circuit of the present invention.
The output terminal Y4 is an embodiment of the third output terminal of the present invention.
The inverter circuit INV5 is an embodiment of the third amplifier circuit of the present invention.

The inverter circuit INV5 logically inverts and outputs a signal input at the input terminal C1.
The inverter circuit INV6 logically inverts the signal input at the input terminal C2 and outputs it.

  The NAND circuit U4 calculates an inverted logical product of the output signals of the inverter circuits INV5 and INV6, and outputs the inverted logical product to the output terminal Y4.

The wiring that transmits the output signal of the inverter circuit INV5 is connected to the nodes N1, N2, N3, and N4 according to the logic function configured in the circuit cell.
Symbols P13 ′, P23 ′, P33 ′, and P43 ′ in FIG. 6 indicate creation positions of vias that connect the output of the inverter circuit INV5 and the nodes N1, N2, N3, and N4.

The wiring for transmitting the output signal of the NAND circuit U4 is connected to the nodes N1, N2, N3, N4 and the input terminals A1, A2, B1, B2 according to the logic function configured in the circuit cell.
Symbols P14 ′, P24 ′, P34 ′, and P44 ′ in FIG. 6 indicate creation positions of vias that connect the output of the NAND circuit U4 and the nodes N1, N2, N3, and N4. Symbols P61 ′, P62 ′, P63 ′, and P64 ′ in FIG. 6 indicate creation positions of vias that connect the output of the NAND circuit U4 and the input terminals A1, A2, B1, and B2.

Transistors Qn9-1 and Qn9-2 constitute a circuit for inputting a test signal to the circuit cell in the test mode.
The transistor Qn9-1 is connected between the test signal input terminal Tc1 and the input terminal C1.
The transistor Qn9-2 is connected between the test signal input terminal Tc2 and the input terminal C2.
The gates of the transistors Qn9-1 and Qn9-2 are commonly connected to the terminal Tmod.
When the terminal mod is set to the high level in the test mode, the transistors Qn9-1 and Qn9-2 are turned on. As a result, the test signal supplied to the input terminals Tc1 and Tc2 is input to the input terminals C1 and C2 via these transistors.

When the input signals of the input terminals C1 and C2 are represented by symbols c1 ′ and c2 ′, the four signals {1 ′, 0 are generated at the nodes N1 to N4 according to the vias created at the positions P11 to P44, respectively. ', / C1', / (/ c1 · / c2) '}
One signal selected from among them is input.

When a fixed value 1 ′ is input to each of the input terminals A2, B2, and D2 and the input terminal D1 is opened, the circuit cell shown in FIG. 6 has four inputs (A1, B1, C1, and C2) and two inputs. It operates as a logic circuit having outputs (Y1, Y1b). The function of this logic circuit is that four signals {1 ′, 0 ′, / c1 ′, / (/ c1 · / c2) ′} for each of the nodes N1 to N4.
Is selected from the following formulas, and the selected signals are substituted into the signals n1 to n4 in the equation (1).
Therefore, in this case, various logic functions can be programmed in the circuit cell shown in FIG. 6 according to the vias created at the positions P11 to P44.
In particular, when a fixed value 0 ′ is input to the input terminal C2, four signals {1 ′, 0 ′, / c1 ′, c1 ′} are supplied to each of the nodes N1 to N4.
Any one of these is input. In this case, the circuit cell shown in FIG. 6 can operate as a three-input (A1, B1, C1) lookup table.

Further, according to the circuit cell shown in FIG. 6, the output signal of the NAND circuit U4 can be output to the outside of the circuit cell through the output terminal Y4. Therefore, the NAND circuit U4 can be independently connected to another circuit cell as a circuit that performs a 2-input NAND operation.
As described above, by incorporating a NAND circuit frequently used in a general logic circuit in a circuit cell of a basic structural unit in advance, the circuit cell can be used efficiently. In addition, the operation speed of the circuit can be improved while suppressing the size of the circuit cell.

  Further, the NAND circuit U4 has a logical inversion function and a 2-input NAND operation function necessary for operating the circuit cell shown in FIG. 6 as a 3-input (A1, B1, C1) lookup table. Have both. Therefore, the use efficiency of the circuit elements is improved as compared with a method in which the NAND circuit is simply added to the circuit cell, and the entire size of the semiconductor integrated circuit can be suppressed.

  Moreover, according to the circuit cell shown in FIG. 6, it is possible to arbitrarily connect the output of the NAND circuit U4 and the input terminals A1, A2, B1, and B2 by vias. As a result, the degree of freedom of wiring inside the circuit cell is increased, and the types of logic functions that can be programmed in the circuit cell can be increased. Therefore, the use efficiency of the circuit cell can be further improved.

  Next, a sixth configuration example of the circuit cell will be described.

  FIG. 7 is a diagram illustrating a sixth configuration example of the circuit cell. In the circuit cell shown in FIG. 7, the NAND circuit U1, the transistor Qn14-2, the input terminals D1 and D2, and the test input terminal Td2 in the circuit cell shown in FIG. 5 are deleted, and an inverter INV7 is provided instead. .

  The inverter circuit INV7 is an embodiment of the second amplifier circuit of the present invention. The inverter circuit INV7 logically inverts the signal at the node N5 and outputs it to the output terminal Y1.

According to the circuit cell shown in FIG. 7 having the above-described configuration, the NAND circuits U2 and U3 can be independently connected to other circuit cells, similarly to the circuit cell shown in FIG. As described above, by incorporating the NAND circuit in the circuit cell in advance, the use efficiency of the circuit cell can be improved, and the operation speed of the circuit can be increased while suppressing the circuit size.
Further, according to the circuit cell shown in FIG. 7, as in the circuit cell shown in FIG. 5, the NAND circuits U1 and U2 have both a logic inversion function and a NAND operation function necessary for the look-up table operation. . Therefore, the overall circuit size of the semiconductor integrated circuit can be suppressed as compared with a method in which a NAND circuit is simply added to a circuit cell.
Furthermore, according to the circuit cell shown in FIG. 7, it is possible to arbitrarily connect the output of the NAND circuit U3 and the input terminals A1 and A2 by vias. Therefore, like the circuit cell shown in FIG. 5, the degree of freedom of wiring inside the circuit cell is increased, and the types of logic functions that can be programmed into the circuit cell can be increased.

  Further, according to the circuit cell shown in FIG. 7, by providing the inverter circuit INV7, the signal at the node N5 can be amplified and output to the output terminal Y1, so that the signal level due to the resistance of the switch (Qn1 to Qn6). Can be suppressed.

  Next, a seventh configuration example of the circuit cell will be described.

  FIG. 8 is a diagram illustrating a seventh configuration example of the circuit cell. In the circuit cell shown in FIG. 8, the NAND circuit U1, the transistor Qn14-2, the input terminals D1 and D2, and the test input terminal Td2 in the circuit cell shown in FIG. 6 are deleted, and an inverter INV7 is provided instead. .

  The inverter circuit INV7 is an embodiment of the second amplifier circuit of the present invention. The inverter circuit INV7 logically inverts the signal at the node N5 and outputs it to the output terminal Y1.

According to the circuit cell shown in FIG. 8 having the above-described configuration, the NAND circuits U2, U3, U4 can be independently connected to other circuit cells, similarly to the circuit cell shown in FIG. As described above, by incorporating the NAND circuit in the circuit cell in advance, the use efficiency of the circuit cell can be improved, and the operation speed of the circuit can be increased while suppressing the circuit size.
Further, according to the circuit cell shown in FIG. 8, like the circuit cell shown in FIG. 6, the NAND circuits U2, U3, U4 have both a logic inversion function and a NAND operation function necessary for the look-up table operation. ing. Therefore, the overall circuit size of the semiconductor integrated circuit can be suppressed as compared with a method in which a NAND circuit is simply added to a circuit cell.
Further, according to the circuit cell shown in FIG. 8, the output of the NAND circuit U3 and the input terminals A1 and A2 can be arbitrarily connected by vias, and the output of the NAND circuit U4 and the input terminals A1, A2, and A2 can be arbitrarily connected. B1 and B2 can be arbitrarily connected by a via. Therefore, like the circuit cell shown in FIG. 6, the degree of freedom of wiring inside the circuit cell is increased, and the types of logic functions that can be programmed into the circuit cell can be increased.

  Next, an eighth configuration example of the circuit cell will be described.

  FIG. 9 is a diagram illustrating an eighth configuration example of the circuit cell. 9 deletes the NAND circuit U1, the inverter circuit INV4, the transistors Qn9, Qn14-2, the input terminals C, D1, D2, and the test input terminals Tc, Td2 in the circuit cell shown in FIG. Are provided with a NAND circuit U4, an inverter circuit INV7, transistors Qn9-1 and Qn9-2, input terminals C1 and C2, and an output terminal Y4.

  The NAND circuit U4 calculates the inverted logical product of the signals input to the input terminals C1 and C2, and outputs the inverted logical product to the output terminal Y4.

The input terminal C1 that supplies one of the two signals input to the NAND circuit U4 is connected to the nodes N1, N2, N3, and N4 according to the logic function configured in the circuit cell.
Symbols P13 ′, P23 ′, P33 ′, and P43 ′ in FIG. 9 indicate via creation positions that connect the input terminal C1 and the nodes N1, N2, N3, and N4.

The wiring that transmits the output signal of the NAND circuit U4 is connected to the nodes N1, N2, N3, and N4 according to the logic function configured in the circuit cell.
Symbols P14 ′, P24 ′, P34 ′, and P44 ′ in FIG. 9 indicate creation positions of vias that connect the output of the NAND circuit U4 and the nodes N1, N2, N3, and N4.

  The inverter circuit INV7 logically inverts the signal at the node N5 and outputs it to the output terminal Y1.

Transistors Qn9-1 and Qn9-2 constitute a circuit for inputting a test signal to the circuit cell in the test mode.
The transistor Qn9-1 is connected between the test signal input terminal Tc1 and the input terminal C1.
The transistor Qn9-2 is connected between the test signal input terminal Tc2 and the input terminal C2.
The gates of the transistors Qn9-1 and Qn9-2 are commonly connected to the terminal Tmod.
When the terminal Tmod is set to a high level in the test mode, the transistors Qn9-1 and Qn9-2 are turned on. As a result, the test signal supplied to the input terminals Tc1 and Tc2 is input to the input terminals C1 and C2 via these transistors.

Each of the nodes N1 to N4 has four signals {1 ′, 0 ′, c1 ′, / (c1 · c2) ′} according to the vias created at the positions P11 to P44.
One signal selected from among them is input.

The circuit cell shown in FIG. 9 is a logic circuit having four inputs (A1, B1, C1, C2) and two outputs (Y1, Y1b), and its logic function is applied to each of the nodes N1 to N4. Four kinds of signals {1 ′, 0 ′, c1 ′, / (c1 · c2) ′}
Is selected from the following formulas, and the selected signals are substituted into the signals n1 to n4 in the equation (1).
Accordingly, various logic functions can be programmed in the circuit cell shown in FIG. 9 according to the vias created at the positions P11 to P44.
In particular, when a fixed value 1 ′ is input to the input terminal C2, four signals {1 ′, 0 ′, c1 ′, / c1 ′} are supplied to each of the nodes N1 to N4.
Any one of these is input. In this case, the circuit cell shown in FIG. 9 can operate as a three-input (A1, B1, C1) lookup table.

Further, according to the circuit cell shown in FIG. 9, the output signal of the NAND circuit U4 can be output to the outside of the circuit cell through the output terminal Y4. Therefore, the NAND circuit U4 can be independently connected to another circuit cell as a circuit that performs a 2-input NAND operation.
As described above, by incorporating a NAND circuit frequently used in a general logic circuit in a circuit cell of a basic structural unit in advance, the circuit cell can be used efficiently. In addition, the operation speed of the circuit can be improved while suppressing the size of the circuit cell.

  Further, the NAND circuit U4 has a logical inversion function and a 2-input NAND operation function necessary for operating the circuit cell shown in FIG. 9 as a 3-input (A1, B1, C1) lookup table. Have both. Therefore, the use efficiency of the circuit elements is improved as compared with a method in which the NAND circuit is simply added to the circuit cell, and the entire size of the semiconductor integrated circuit can be suppressed.

  Next, a ninth configuration example of the circuit cell will be described.

  FIG. 10 is a diagram illustrating a ninth configuration example of the circuit cell. The difference from the circuit cell shown in FIG. 9 is that an inverter circuit INV5 is inserted at the input of the NAND circuit U4, and an output node of the inverter circuit INV5 is connected to the nodes N1 to N4 via a program via.

  The inverter circuit INV5 is inserted in a signal path from the input terminal C1 to the NAND circuit U1, and logically inverts the signal of the input terminal C1 and inputs the signal to the NAND circuit U1. The input of the inverter circuit INV5 is connected to the inspection input terminal Tc1 through the transistor Qn9-1.

The output of the inverter circuit INV5 is connected to the nodes N1, N2, N3 and N4 according to the logic function configured in the circuit cell.
Symbols P13 ′, P23 ′, P33 ′, and P43 ′ in FIG. 10 indicate creation positions of vias that connect the output of the inverter circuit INV5 and the nodes N1, N2, N3, and N4.

The circuit cell shown in FIG. 10 is a logic circuit having four inputs (A, B, C1, C2) and two outputs (Y1, Y1b), and its logic function is applied to each of the nodes N1 to N4. Four kinds of signals {1 ′, 0 ′, / c1 ′, / (/ c1 · c2) ′}
Is selected from the following formulas, and the selected signals are substituted into the signals n1 to n4 in the equation (1).
Therefore, various logic functions can be programmed in the circuit cell shown in FIG. 10 according to the vias created at the positions P11 to P44.
In particular, when a fixed value 1 ′ is input to the input terminal C2, four signals {1 ′, 0 ′, / c1 ′, c1 ′} are supplied to each of the nodes N1 to N4.
Any one of these is input. In this case, the circuit cell shown in FIG. 10 can operate as a three-input (A, B, C1) lookup table.

  In the circuit cell shown in FIG. 9, the nodes N1 to N4 and the input terminal C1 are directly connected through the programming vias formed at the positions P13, P23, P33, and P43. The node N5 is driven by a circuit outside the circuit cell via a wiring outside the circuit cell connected to the input terminal C1 and switches (Qn1 to Qn6) inside the circuit cell. That is, the node N5 is driven by a circuit outside the circuit cell via a high impedance signal path including the resistance of the switch. For this reason, the delay of the signal propagating to the node N5 increases. On the other hand, in the circuit shown in FIG. 10, since the signal c1 input to the input terminal C1 is input to the nodes N1 to N4 via the inverter circuit INV5, the inverter circuit INV5 operates as a buffer amplifier, and the node N5 has a low impedance. Can be driven by. Therefore, according to the circuit cell shown in FIG. 10, the delay due to the resistance of the switches (Qn1 to Qn6) can be improved and the operation speed can be increased.

  Next, a tenth configuration example of the circuit cell will be described.

  FIG. 11 is a diagram illustrating a tenth configuration example of the circuit cell. The circuit cell shown in FIG. 11 has an inverter circuit INV6 inserted in a signal path from the input terminal C2 of the circuit cell shown in FIG. 10 to the NAND circuit U4. The input of the inverter circuit INV6 is connected to the inspection input terminal Tc2 via the transistor Qn9-2.

  According to the circuit cell shown in FIG. 11, since the input signals of the input terminals C1 and C2 are logically inverted by the inverter circuit and input to the NAND circuit U4, the propagation delay from the input terminal C1 to the output terminal Y4, the input terminal The propagation delay from C2 to the output terminal Y4 can be substantially balanced. As a result, the wiring between the external circuit cell and the input terminals C1 and C2 can be reversely connected, so that the layout and wiring design of the circuit cell can be facilitated.

  Next, the wiring structure of the semiconductor integrated circuit according to the present embodiment will be described.

FIG. 12 is a diagram showing an example of the wiring structure of the semiconductor integrated circuit according to the present embodiment, showing wiring patterns in the a-th layer (a represents an integer of 1 or more) and the (a + 1) -th layer above it. ing.
The wiring structure shown in FIG. 12 is applied to the circuit cell shown in FIG. 5, for example.

In FIG. 12, symbols L1 ′ to L4 ′ indicate wiring groups that connect circuit cells to each other. Symbols LC1 ′ to LC17 ′ indicate input / output terminals of circuit cells and wiring of internal nodes. Symbol LS1 ′ indicates a wiring of the power supply voltage VDD. Symbol LS2 ′ indicates a wiring of the reference potential VSS.
The wirings LC12 to LC15 are an embodiment of the first wiring of the present invention.
The wirings LS1, LS2, LC16, and LC17 are an embodiment of the second wiring of the present invention.

In the a-th layer, a wiring group L1 extending in the row direction of the circuit cell array (the horizontal direction in FIG. 12) is formed. In the example of FIG. 12, the wiring group L1 is a bundle of six wirings, and the length thereof is substantially the same as the column width of the circuit cell array. A plurality of wiring groups L1 are arranged in the row direction. A plurality of wiring groups L1 connected in the row direction are formed in each row of the circuit cell array.
For example, as shown in FIG. 12, the wiring group L1 corresponds to each piece formed by obliquely cutting one bundle (six wirings) extending in the row direction one place on each circuit cell. In the example of FIG. 12, the wiring groups L1 corresponding to the respective pieces are arranged alternately shifted in the column direction.

  In the (a + 1) th layer, a wiring group L3 for connecting the wiring groups L1 connected in the row direction via vias is formed. The wiring group L3 is a bundle of the same six wirings as the wiring group L1, and is formed on the upper layer of two adjacent wiring groups L1 so as to extend in a direction intersecting with these.

In the (a + 1) th layer, a wiring group L2 extending in the column direction (vertical direction in FIG. 12) of the circuit cell array is formed. In the example of FIG. 12, the wiring group L2 is a bundle of 10 wirings, and the length thereof is substantially the same as the row width of the circuit cell array. A plurality of wiring groups L2 are arranged in the column direction. In each column of the circuit cell array, a plurality of wiring groups L2 connected in the column direction are formed.
For example, as illustrated in FIG. 12, the wiring group L2 corresponds to each piece formed by obliquely cutting one bundle (10 pieces) of wiring extending in the column direction one place on each circuit cell. In the example of FIG. 12, the wiring group L2 corresponding to each fragment is arranged so as to be alternately shifted in the row direction.

  In the a-th layer, a wiring group L4 for connecting the wiring groups L2 connected in the column direction via vias is formed. The wiring group L4 is a bundle of the same ten wirings as the wiring group L2, and is formed below the adjacent two wiring groups L2 so as to extend in a direction crossing these.

In the a-th layer, wirings LC1 to LC7 connected to the input terminals (A1, A2, B1, B2, C, D1, D2) of each circuit cell, and wirings LC8 to LC8 connected to the output nodes (Y2, Y3, Y1, Y1b) Wiring lines LC12 to LC15 connected to the LC11 and logic function program nodes (N1, N2, N3, N4) are formed.
In the (a + 1) th layer, wirings LC16 and LC17 connected to the nodes (Cb and Cbb) in the circuit cell are formed. The wirings LC16 and LC17 are connected to the nodes N1 to N4 through a program via.

The wirings LC1, LC2, LC3, LC4, LC5, LC6, and LC7 are connected to input terminals A1, A2, B1, B2, C, D1, and D2, respectively. Further, the wirings LC8, LC9, LC10, and LC11 are connected to the output terminals Y2, Y3, Y1, and Y1b, respectively.
The wirings LC1 to LC11 are all formed so as to extend in the row direction, and are formed side by side in the column direction in this order. Further, the wirings LC1 to LC11 are formed at positions intersecting with the upper layer wiring group L2, and can be connected to the wiring group L2 via vias.

The wirings LC12, LC13, LC14, and LC15 are connected to logic function program nodes N1, N2, N3, and N4, respectively.
The wirings LC12 to LC15 are all formed extending in the row direction, and are formed side by side in the column direction in this order. The wirings LC12 to LC15 are formed at positions intersecting with the upper wirings LS1, LS2, LC16, and LC17, and can be connected to these wirings through vias.

  The wiring LC16 is a wiring connected to the output node Cb of the inverter circuit INV5, and is formed extending in the column direction. The wiring LC16 is formed at a position intersecting with the lower wirings LC12 to LC15, and can be connected to these wirings via vias.

  The wiring LC17 is a wiring connected to the output node Cbb of the inverter circuit INV4, and is formed extending in the column direction. The wiring LC17 is formed at a position intersecting with the lower wirings LC12 to LC15, and can be connected to these wirings via vias.

The wiring LS1 is a wiring for supplying the power supply voltage VDD to the circuit cell.
The wiring LS2 is a wiring for supplying the reference potential VSS to the circuit cell.
The wirings LS1 and LS2 are both (a + 1) th layer wirings and are formed in each column of the circuit cell array so as to extend in the column direction.

  Next, an example of configuring a multiplier in the semiconductor integrated circuit according to the present embodiment will be described. In the following, it is assumed that the circuit cell shown in FIG. 5 is used as an example.

FIG. 13 is a diagram illustrating an example of a method of multiplying 4-bit data.
In the example of FIG. 13, the multiplicand data is {a3, a2, a1, a0} in order from the upper bits, and the multiplier data is {b3, b2, b1, b0} in order from the upper bits. When multiplying the numbers in binary notation, a process of obtaining and adding the products of the respective digits is performed in the same manner as the multiplication method by manual calculation. In this case, a product of 1-bit data is obtained by an AND operation.

FIG. 14 is a diagram illustrating an example of a configuration of an array type multiplier that performs multiplication of 4 bits × 4 bits.
The array type multiplier is configured by combining a plurality of functional units having a form in which an AND circuit is added to the input of a full adder or a half adder. 15 to 17 show configuration examples of main functional units.

The functional unit shown in FIG. 15A has four inputs (input signals IN1 to IN4) and two outputs (sum signal S, carry signal Co), and two half adders (HA). It is configured as a circuit in which a 2-input AND circuit is connected to each input.
In the functional unit shown in FIG. 15A, the sum signal S and the carry signal Co are each expressed by the following logical expressions.

The functional unit shown in FIG. 15A can be composed of two circuit cells Cf1 and Cf2 and one NAND circuit Cf3 as shown in FIG. 15B.
In the functional unit illustrated in FIG. 15A, the NAND circuit Cf3 performs a NAND operation on the two input signals IN3 and IN4. The circuit cell Cf1 uses the output of the NAND circuit Cf3 to generate the sum signal S expressed by Expression (2). The circuit cell Cf2 generates the carry signal Co represented by the expression (3) using the output of the same NAND circuit Cf3.

  When the circuit cell shown in FIG. 5 is used, a maximum of three independent NAND circuits Cf3 can be configured by one circuit cell.

The functional unit shown in FIG. 16A has four inputs (input signals IN1 to IN3, carry signal Ci) and two outputs (sum signal S, carry signal Co), and a full adder (FA ) Is connected to a two-input AND circuit.
In the functional unit shown in FIG. 16A, the sum signal S and the carry signal Co are each expressed by the following logical expressions.

The functional unit shown in FIG. 16A can be composed of two circuit cells Cf4 and Cf5 and one NAND circuit Cf3 as shown in FIG. 16B.
In the functional unit illustrated in FIG. 15A, the NAND circuit Cf3 performs a NAND operation on the two input signals IN1 and IN2. The circuit cell Cf4 uses the output of the NAND circuit Cf3 to generate the sum signal S expressed by Expression (4). The circuit cell Cf2 uses the output of the same NAND circuit Cf3 to generate a carry signal Co expressed by Expression (5).

The functional unit shown in FIG. 17A has five inputs (input signals IN1 to IN4, carry signal Ci) and two outputs (sum signal S, carry signal Co), and a full adder (FA ) Is connected to a 2-input AND circuit.
In the functional unit shown in FIG. 17A, the sum signal S and the carry signal Co are each expressed by the following logical expressions.

The functional unit shown in FIG. 17A can be composed of two circuit cells Cf6 and Cf7 and two NAND circuits Cf3 as shown in FIG. 17B.
In the functional unit shown in FIG. 17, one NAND circuit Cf3 performs a NAND operation on two input signals IN1 and IN2, and the other NAND circuit Cf3 performs a NAND operation on two input signals IN3 and IN4. The circuit cell Cf6 uses the outputs of the two NAND circuits Cf3 to generate the sum signal S expressed by Expression (6). The circuit cell Cf7 generates a carry signal Co expressed by Expression (7) using the outputs of the same two NAND circuits Cf3.

In general, an n-bit xn-bit array type multiplier includes the following number of functional units.
Functional units shown in FIG. 15 (n-1) units;
Functional units shown in FIG. 16 ... {(n-2) ² +1} units;
Functional units shown in FIG. 17 (n-2) units;
Full adders (n-3);
Half adder ... 1 piece;
AND circuit: 1 piece;

When the circuit cell shown in FIG. 5 is used, the number of circuit cells necessary for constituting one functional unit is as follows.
Functional units shown in FIG. 15: 7/3 units;
Functional units shown in FIG. 16: 7/3 units;
Functional units shown in FIG. 17: 8/3 units;
Full adder ... 2 pieces;
Half adder ... 2 pieces;
AND circuit: 1/3;

However, the number of circuit cells necessary for configuring a NAND circuit and an AND circuit is 1/3.
Therefore, the number of circuit cells Z1 required to construct an n-bit xn-bit array type multiplier using the circuit cells shown in FIG.
Z1 = (7n ² -7n + 1) / 3;
It becomes.

On the other hand, when a 3-input lookup table is used as a circuit cell, one circuit cell is consumed to form one NAND circuit and one AND circuit. For this reason, the number of circuit cells required to constitute one functional unit is as follows.
15 functional units shown in FIG. 15;
16 functional units shown in FIG. 16;
17 functional units shown in FIG. 17;
Full adder ... 2 pieces;
Half adder ... 2 pieces;
AND circuit: 1 piece;

When a 3-input look-up table is used as a circuit cell, the number of circuit cells Z2 required to construct an n-bit xn-bit array multiplier is:
Z2 = 3n ² -4n + 4;
It becomes.

Therefore,
Z2-Z1 = (2n ² -5n + 11) / 3;
When n = 4,
Z2−Z1 = 23 / 3≈8;
It becomes. That is, when a 4-bit × 4-bit array-type multiplier is configured using the circuit cell shown in FIG. 5, the number of circuit cells used is reduced by about 8 compared to the case where a 3-input lookup table is used for the circuit cell. be able to. As the number of bits of the multiplier increases, the difference in the number of circuit cells used further increases.
As described above, by configuring the multiplier using the circuit cell according to the present embodiment, the usage efficiency of the circuit cell can be improved and the overall circuit size can be reduced.

Next, a specific circuit configuration example will be described.
FIG. 18 is a diagram showing a part of the circuit of the array type multiplier shown in FIG.
In the circuit shown in FIG. 18, the unit MU1 is the functional unit shown in FIG. 17, and the unit MU2 is the functional unit shown in FIG.
The unit MU1 inputs multiplicand bit signals a2 and a3 and multiplier bit signals b0 and b1, and outputs a sum signal Sm1 and a carry signal Ca1.
Unit MU2 inputs carry signal Ca1, multiplicand bit signals a2 and a3, and multiplier bit signals b1 and b2, and outputs sum signal Sm2 and carry signal Ca2.

  FIG. 19 is a diagram illustrating an example in which the circuit shown in FIG. 18 is configured using the circuit cell shown in FIG.

The circuit cell C_1 constitutes three independent NAND circuits.
The input terminals A1 and A2 of the circuit cell C_1 receive the multiplicand bit signal a2 and the multiplier bit signal b1, and the output terminal Y2 outputs an inverted logical product of the two signals.
The input terminals B1 and B2 of the circuit cell C_1 receive the multiplicand bit signal a3 and the multiplier bit signal b1, and the output terminal Y3 outputs an inverted logical product of the two signals.
The input terminals D1 and D2 of the circuit cell C_1 receive the multiplicand bit signal a2 and the multiplier bit signal b2, and the output terminal Y1 outputs an inverted logical product of the two signals.

The circuit cell C_2 has the same logic function as the circuit cell Cf1 illustrated in FIG.
The multiplicand bit signal a3 is input to the input terminal A1 of the circuit cell C_2. The input terminal B1 inputs a multiplier bit signal b0. The input terminal C receives the inverted logical product of the bit signals a2 and b1 output from the output terminal Y2 of the circuit cell C_1. The input terminals A2, B2, and D2 receive the power supply voltage VDD. The input terminal D1 is opened.

FIG. 20 is a diagram for explaining the logic function of the circuit cell C_2 and the creation position of the via.
As shown in FIG. 20A, the circuit cell C_2 includes an exclusive OR of the logical product of two signals input from the input terminals A1 and B1 and the logical inversion signal of the signal input from the input terminal C. Is output from the output terminal Y1.

In the circuit shown in FIG. 20A, when a signal of 1 ′ is input to the input terminals A1 and B1, a signal having the same logical value as that of the signal of the input terminal C is generated at the output terminal Y1. In this case, a signal obtained by logically inverting the signal at the input terminal C is generated at the node N5. Accordingly, as shown in FIG. 20B, the node N1 is connected to the output node Cb of the inverter circuit INV5 by the via at the position P13.
When a signal of 1 ′ is input to the input terminal A1 and 0 ′ is input to the input terminal B1, a signal obtained by logically inverting the signal of the input terminal C is generated at the output terminal Y1, and the signal of the input terminal C is generated at the node N5. A signal having the same logical value as is generated. Therefore, as shown in FIG. 20B, the node N2 is connected to the output node Cbb of the inverter circuit INV4 by the via at the position P24.
When the signal 0 'is input to the input terminal A1 and the signal 1' is input to the input terminal B1, a signal obtained by logically inverting the signal of the input terminal C is generated at the output terminal Y1, and the signal of the input terminal C is generated at the node N5. A signal having the same logical value as is generated. Therefore, as shown in FIG. 20B, the node N3 is connected to the output node Cbb of the inverter circuit INV4 by the via at the position P34.
When a signal of 0 ′ is input to the input terminals A1 and B1, a signal obtained by logically inverting the signal of the input terminal C is generated at the output terminal Y1, and the same logical value as that of the signal of the input terminal C is generated at the node N5. A signal is generated. Therefore, as shown in FIG. 20B, the node N4 is connected to the output node Cbb of the inverter circuit INV4 by the via at the position P44.

The circuit cell C_5 has the same logic function as the circuit cell Cf2 illustrated in FIG.
The multiplicand bit signal a3 is input to the input terminal A1 of the circuit cell C_5. The input terminal B1 inputs a multiplier bit signal b0. The input terminal C receives the inverted logical product of the bit signals a2 and b1 output from the output terminal Y2 of the circuit cell C_1. The input terminals A2, B2, and D2 receive the power supply voltage VDD. The input terminal D1 is opened.

FIG. 21 is a diagram for explaining a logic function of the circuit cell C_5 and a position where a via is created.
As shown in FIG. 21A, the circuit cell C_5 outputs a logical product of the logical product of two signals input from the input terminals A1 and B1 and the logical inversion signal of the signal input from the input terminal C. Output from terminal Y1.

In the circuit shown in FIG. 21A, when a 1 'signal is input to the input terminals A1 and B1, a signal obtained by logically inverting the signal of the input terminal C is generated at the output terminal Y1. In this case, a signal having the same logical value as that of the signal at the input terminal C is generated at the node N5. Therefore, as shown in FIG. 21B, the node N1 is connected to the output node Cbb of the inverter circuit INV4 by the via at the position P14.
When a signal 1 'is input to the input terminal A1 and a signal 0' is input to the input terminal B1, a signal 0 'is generated at the output terminal Y1, and a signal 1' is generated at the node N5. Accordingly, as shown in FIG. 21B, the node N2 is connected to the power supply voltage VDD by the via at the position P21.
When a signal of 0 ′ is input to the input terminal A1 and a signal of 1 ′ is input to the input terminal B1, a signal of 0 ′ is generated at the output terminal Y1, and a signal of 1 ′ is generated at the node N5. Therefore, as shown in FIG. 21B, the node N3 is connected to the power supply voltage VDD by the via at the position P31.
When a 0 ′ signal is input to the input terminals A1 and B1, a 0 ′ signal is generated at the output terminal Y1, and a 1 ′ signal is generated at the node N5. Accordingly, as shown in FIG. 21B, the node N4 is connected to the power supply voltage VDD by the via at the position P41.

The circuit cell C_3 has the same logic function as that of the circuit cell Cf6 illustrated in FIG.
The input terminal A1 of the circuit cell C_3 inputs the inverted logical product of the bit signals a2 and b2 output from the output terminal Y1 of the circuit cell C_1. The input terminal B1 inputs an inverted logical product of the bit signals a3 and b1 output from the output terminal Y3 of the circuit cell C_1. The input terminal C receives the carry signal Ca1 output from the output terminal Y1 of the circuit cell C_5. The input terminals A2, B2, and D2 receive the power supply voltage VDD. The input terminal D1 is opened.

FIG. 22 is a diagram for explaining a logic function of the circuit cell C_3 and a position where a via is created.
As shown in FIG. 22A, the circuit cell C_3 has an exclusive OR between the logical inversion signals of the two signals input from the input terminals A1 and B1 and the signal input from the input terminal C. A logical sum is output from the output terminal Y1.

In the circuit shown in FIG. 22A, when a signal of 1 ′ is input to the input terminals A1 and B1, a signal having the same logical value as that of the signal of the input terminal C is generated at the output terminal Y1, and the node N5 has a signal. A signal obtained by logically inverting the signal at the input terminal C is generated. Therefore, as shown in FIG. 22B, the node N1 is connected to the output node Cb of the inverter circuit INV5 by the via at the position P13.
When a signal of 1 ′ is input to the input terminal A1 and 0 ′ is input to the input terminal B1, a signal obtained by logically inverting the signal of the input terminal C is generated at the output terminal Y1, and the signal of the input terminal C is generated at the node N5. A signal having the same logical value as is generated. Therefore, as shown in FIG. 22B, the node N2 is connected to the output node Cbb of the inverter circuit INV4 by the via at the position P24.
When the signal 0 'is input to the input terminal A1 and the signal 1' is input to the input terminal B1, a signal obtained by logically inverting the signal of the input terminal C is generated at the output terminal Y1, and the signal of the input terminal C is generated at the node N5. A signal having the same logical value as is generated. Therefore, as shown in FIG. 22B, the node N3 is connected to the output node Cbb of the inverter circuit INV4 by the via at the position P34.
When a signal of 0 ′ is input to the input terminals A1 and B1, a signal having the same logical value as that of the signal of the input terminal C is generated at the output terminal Y1, and the signal of the input terminal C is logically inverted at the node N5. A signal is generated. Therefore, as shown in FIG. 22B, the node N4 is connected to the output node Cb of the inverter circuit INV5 by the via at the position P43.

The circuit cell C_6 has the same logic function as that of the circuit cell Cf7 illustrated in FIG.
The input terminal A1 of the circuit cell C_6 receives the inverted logical product of the bit signals a2 and b2 output from the output terminal Y1 of the circuit cell C_1. The input terminal B1 inputs an inverted logical product of the bit signals a3 and b1 output from the output terminal Y3 of the circuit cell C_1. The input terminal C receives the carry signal Ca1 output from the output terminal Y1 of the circuit cell C_5. The input terminals A2, B2, and D2 receive the power supply voltage VDD. The input terminal D1 is opened.

FIG. 23 is a diagram for explaining the logic function of the circuit cell C_6 and the creation position of the via.
As shown in FIG. 23A, the circuit cell C_6 includes a logical product of logical inversion signals of two signals input from the input terminals A1 and B1, and a logical inversion signal and an input of the signal input from the input terminal A1. The logical product of the signal input from the terminal B1 and the logical product of the signal input from the input terminal A1 and the logical inversion signal of the signal input from the input terminal B1 are calculated, and the logical product of these logical products is calculated. The sum is output from the output terminal Y1.

In the circuit shown in FIG. 23A, when a 1 'signal is input to the input terminals A1 and B1, a 0' signal is generated at the output terminal Y1, and a 1 'signal is generated at the node N5. . Therefore, as shown in FIG. 23B, the node N1 is connected to the power supply voltage VDD by the via at the position P11.
When a signal of 1 ′ is input to the input terminal A1 and a signal of 0 ′ is input to the input terminal B1, a signal having the same logical value as the signal of the input terminal C is generated at the output terminal Y1, and the signal of the input terminal C is generated at the node N5. A signal obtained by logically inverting is generated. Therefore, as shown in FIG. 23B, the node N2 is connected to the output node Cb of the inverter circuit INV5 by the via at the position P23.
When a signal of 0 ′ is input to the input terminal A1 and a signal of 1 ′ is input to the input terminal B1, a signal having the same logical value as the signal of the input terminal C is generated at the output terminal Y1, and the signal of the input terminal C is generated at the node N5. A signal obtained by logically inverting is generated. Accordingly, as shown in FIG. 23B, the node N3 is connected to the output node Cb of the inverter circuit INV5 by the via at the position P33.
When a 0 ′ signal is input to the input terminals A1 and B1, a 1 ′ signal is generated at the output terminal Y1, and a 0 ′ signal is generated at the node N5. Therefore, as shown in FIG. 23B, the node N4 is connected to the reference potential VSS by the via at the position P42.

  24 is a diagram illustrating an example of a specific wiring structure of the circuit cells C_1, C_2, C_3, C_5, and C_6 illustrated in FIG.

  In the example of FIG. 24, circuit cells C_1, C_2, and C_3 are formed side by side in this order in the row direction. Circuit cells C_4, C_5, and C_6 are formed in the row direction in this order. The circuit cells C_1 and C_5, the circuit cells C_2 and C_6, and the circuit cells C_3 and C_6 are formed side by side in the column direction.

The circuit cell C_1 does not operate as a look-up table because no via is created at the positions P11 to P44, and instead, the three built-in NAND circuits (U1 to U3) function as independent circuits.
The circuit cell C_2 has vias at positions P13, P24, P34, and P44, and has a logic function corresponding to the circuit cell Cf1 in FIG.
The circuit cell C_5 has vias at positions P14, P21, P31, and P41, and has a logic function corresponding to the circuit cell Cf2 in FIG.
The circuit cell C_3 has vias at positions P13, P24, P34, and P43, and has a logic function corresponding to the circuit cell Cf6 in FIG.
The circuit cell C_6 has vias at positions P11, P23, P33, and P42, and has a logic function corresponding to the circuit cell Cf7 in FIG.

  The input / output terminal of the circuit cell is connected to a wiring group extending between the circuit cells via a via formed between the wiring group L2 and the wirings LC1 to LC11, or is connected to the power supply wirings LS1 and LS2 and the wiring It is connected to the power supply voltage VDD and the reference potential VSS via a via formed between LC1 to LC11.

  A wiring group that crosses between circuit cells is connected by a via formed between the wiring groups L2 and L4 and a via formed between the wiring groups L1 and L3.

  As described above, according to the semiconductor integrated circuit according to the present embodiment, the logic function of each circuit cell and the wiring path between the circuit cells are set according to the via formed between the a-th layer and the (a + 1) -th layer. It is possible to program freely.

Next, a method for inspecting circuit cells in the semiconductor integrated circuit according to the present embodiment will be described.
FIG. 25 is a diagram showing an example of a circuit related to the inspection of circuit cells, and the same reference numerals shown in FIGS. 1 and 25 indicate the same components.

  The semiconductor integrated circuit according to the present embodiment includes a column selection circuit 100, a precharge circuit 200, sense amplifiers 301, 302, 303,..., And scan flip-flops 401, 402 as circuits related to circuit cell inspection. , 403,.

The column selection circuit 100 sequentially sets the column selection lines CL1, CL2, CL3... To a high level in a test mode for inspecting the circuit. However, the column selection lines CL1, CL2, CL3... Are connected in common to circuit cells belonging to the first column, the second column, the third column,.
For example, when the column selection line CLi of the i-th column is set to a high level by the column selection circuit 100, the transistor Qn15 is turned on in each circuit cell connected to the column selection line CLi. As a result, a signal indicating the inspection result of the circuit cell in the i-th column is output to the inspection output lines SL1, SL2, SL3,.

  The precharge circuit 200 precharges the test output lines SL1, SL2, SL3,... To the power supply voltage VDD before the column selection line is set to a high level in the column selection circuit 100. However, the inspection output lines SL1, SL2, SL3,... Are commonly connected to circuit cells belonging to the first row, the second row, the third row,.

  The sense amplifiers 301, 302, 303,... Amplify the circuit cell inspection result signals output to the inspection output lines SL1, SL2, SL3,.

  The scan flip-flops 401, 402, 403,... Latch the test result signal amplified by the sense amplifiers 301, 302, 303,.

  FIG. 26 is a flowchart illustrating an example of inspection processing by the circuit shown in FIG.

  First, at the start of inspection, a number indicating a test target column (hereinafter referred to as a test column number), a number indicating a test signal pattern (hereinafter referred to as a test pattern number), and a number indicating a test target row ( Hereinafter, the test bit numbers are initialized to 0 '(steps ST201 to ST203).

Next, a test signal indicated by a test pattern number is supplied to a circuit cell from an inspection device (not shown). For example, in the case of the circuit cell shown in FIG. 5, a test signal is supplied from an inspection device (not shown) to the input terminals Ta1, Ta2, Tb1, Tb2, and Td2. Further, the terminal Tmod of each circuit cell is set to the high level, and the column selection line of the column indicated by the test column number is set to the high level by the column selection circuit 100.
When the terminal Tmod becomes high level, the test signal of the inspection apparatus is input to each circuit cell. Each circuit cell outputs a test result signal corresponding to the test signal.
At this time, in the circuit cell of the column in which the column selection line is set to the high level, the transistor Qn15 is turned on. The signal at the output terminal Y1b is output to the inspection output lines SL1, SL2, SL3,... Via the transistor Qn15. The signals of the test output lines SL1, SL2, SL3,... Are amplified by the sense amplifiers 301, 302, 303,... And latched by the scan flip-flops 401, 402, 403,. ).

  .. Among the data latched by the scan flip-flops 401, 402, 403,..., The data in the row indicated by the test bit number is compared with the expected value (step ST205). The information on the block and column of the circuit cell thus recorded is recorded as information on the circuit cell having a defect (step ST206). If it matches the expected value, the data of the scan flip-flops 401, 402, 403,... Is shifted by 1 bit (step ST207), and 1 ′ is added to the test bit number (step ST208). At this time, if the test bit number does not reach the predetermined maximum value (that is, the number indicating the last row), the above-mentioned data is stored in the next row corresponding to the test bit number added with 1 ′. The processes in steps ST205 to ST208 are repeated.

  When it is determined that the test bit number has reached a predetermined maximum value (that is, the number indicating the last row) (step ST209), 1 ′ is added to the test pattern number (step ST210). At this time, if the test pattern number does not reach the predetermined maximum value (that is, the number indicating the last pattern), the next test pattern corresponding to the test pattern number to which 1 ′ is added is generated in an inspection apparatus (not shown). Then, the processing of steps ST203 to ST210 described above is repeated.

When it is determined that the test pattern number has reached a predetermined maximum value (that is, the number indicating the last pattern) (step ST211), 1 ′ is added to the test column number. At this time, if the test column number does not reach the predetermined maximum value (that is, the number indicating the last column), the next column corresponding to the test column number added with 1 ′ is the inspection target. That is, the column selection signal for the next column is set to a high level by the column selection circuit 100, and the processes of steps ST202 to ST212 described above are repeated.
When it is determined that the test column number has reached a predetermined maximum value (that is, the number indicating the last column) (step ST213), the inspection of all circuit cells is completed.

  As mentioned above, although embodiment of this invention was described in detail, this invention is not limited only to said form, Various modifications are included.

  The circuit cell shown in FIG. 4 is obtained by replacing the switches of the transistors Qn1 to Qn6 in the circuit cell shown in FIG. 3 with transfer gate type switches. It can be replaced with. Further, the switches used in the selection circuit of the present invention are not limited to those shown in the above-described embodiments, and various other switches can be used.

In the embodiment described above, an example in which a two-input NAND circuit is built in a circuit cell is given as an example. However, the present invention is not limited to this, and a NAND circuit having three or more inputs may be built in a circuit cell.
In addition, the specific numerical values (the number of circuit cells input, the number of outputs, etc.) listed in the above-described embodiments are merely examples for explanation, and in the present invention, these can be changed to arbitrary numerical values.

It is a figure which shows an example of a structure of the semiconductor integrated circuit which concerns on embodiment of this invention. It is a figure which shows the 1st structural example of a circuit cell. It is a figure which shows the 2nd structural example of a circuit cell. It is a figure which shows the 3rd structural example of a circuit cell. It is a figure which shows the 4th structural example of a circuit cell. It is a figure which shows the 5th structural example of a circuit cell. It is a figure which shows the 6th structural example of a circuit cell. It is a figure which shows the 7th structural example of a circuit cell. It is a figure which shows the 8th structural example of a circuit cell. It is a figure which shows the 9th structural example of a circuit cell. It is a figure which shows the 10th structural example of a circuit cell. It is a figure which shows an example of the wiring structure of the semiconductor integrated circuit which concerns on this embodiment. It is a figure which shows an example of the method of multiplying 4-bit data. It is a figure which shows an example of a structure of the array type multiplier which performs a multiplication of 4 bits x4 bits. It is a figure which shows the structural example of the 1st functional unit contained in the array type | mold multiplier shown in FIG. It is a figure which shows the structural example of the 2nd functional unit contained in the array type | mold multiplier shown in FIG. It is a figure which shows the structural example of the 3rd functional unit contained in the array type | mold multiplier shown in FIG. It is a figure which shows a part of circuit contained in the array type | mold multiplier shown in FIG. It is a figure which shows the example which comprises the circuit shown in FIG. 18 by the circuit cell shown in FIG. FIG. 19 is a first diagram for explaining a logic function of a circuit cell used in the circuit shown in FIG. 18 and a creation position of a via. FIG. 19 is a second diagram for explaining a logic function of a circuit cell used in the circuit shown in FIG. 18 and a via creation position. FIG. 19 is a third diagram for describing a logic function of a circuit cell used in the circuit shown in FIG. 18 and a creation position of a via. FIG. 19 is a fourth diagram for illustrating a logic function of a circuit cell used in the circuit shown in FIG. 18 and a creation position of a via. FIG. 20 is a diagram illustrating an example of a wiring structure of the circuit illustrated in FIG. 19. It is a figure which shows an example of the circuit regarding the test | inspection of a circuit cell. FIG. 26 is a flowchart illustrating an example of inspection processing by the circuit shown in FIG. 25. FIG.

Explanation of symbols

  C11 to Cmn: circuit cells, U1 to U4: NAND circuits, INV1 to INV7: inverter circuits, A, B, C, A1, A2, B1, B2, C1, C2, D1, D2. Input terminals, Ta, Tb, Tc, Ta1, Ta2, Tb1, Tb2, Tc1, Tc2, Td2 ... test input terminals, Y1, Y1b, Y2, Y3, Y4 ... output terminals, Qn1 to Qn15 .. n-channel MOS transistors, Qp1 to Qp7... P-channel MOS transistors, 100... Column selection circuit, 200... Precharge circuit, 301, 302, 303. , 403... Scan flip-flop, L1 to L4... Wiring group, LC1 to LC17, LS1, LS2.

Claims (23)

A semiconductor integrated circuit configured by connecting a plurality of circuit cells whose logic functions can be adaptively configured,
The circuit cell is
A plurality of input terminals including a first input terminal and a plurality of second input terminals;
A first output terminal;
A signal corresponding to a logic function configured in the circuit cell is input from a predetermined signal group, or a plurality of signals isolated from the first input terminal according to the logic function configured in the circuit cell. and a node, among the above SL plurality of nodes, a selection circuit for connecting the at least a portion the node selected according to a signal inputted from the above first input terminal of said plurality of input terminals, the first wiring layer A plurality of first wirings formed and connected to the plurality of nodes and a plurality of second wirings formed on a second wiring layer covering the first wiring layer and transmitting each signal of the predetermined signal group And one or more third wirings that selectively connect one of the plurality of second wirings to the first wiring according to a logic function configured in the circuit cell via a via A lookup table having
When in the via is not formed above the first terminal is insulated from the plurality of nodes, calculates the inverted logical product between the signals inputted from above SL plurality of second input terminals, said the inverted logical product When the signal is output to the first output terminal and the via is formed and the first terminal is connected to at least one of the plurality of nodes and operates as a lookup table, the signal selected in the lookup table is And a first logic circuit having a buffer function which is supplied from an output terminal of the lookup table and amplifies and outputs the supplied signal . The circuit cell further includes an inverter circuit that logically inverts a signal input from a predetermined input terminal of the plurality of input terminals,
The predetermined signal group includes an input and output signals of the upper heard inverter circuit,
The semiconductor integrated circuit according to claim 1. The circuit cell further includes a first amplifier circuit that amplifies a signal input from the predetermined input terminal and inputs the signal to the inverter circuit,
The predetermined signal group includes a signal amplified in the first amplifier circuit.
The semiconductor integrated circuit according to claim 2. The selection circuit is inserted into a signal path between the plurality of nodes and the first input terminal, and is set on or off according to a signal input from at least a part of the plurality of input terminals. Including multiple switches,
The semiconductor integrated circuit according to claim 1. The switch includes an n-channel insulated gate transistor.
The semiconductor integrated circuit according to claim 4. The switch includes an n-channel insulated gate transistor and a p-channel insulated gate transistor connected in parallel and driven to be turned on or off in common.
The semiconductor integrated circuit according to claim 5. The circuit cell is
A second logic circuit that calculates and outputs an inverted logical product of signals input from at least a part of the plurality of input terminals;
A second output terminal for outputting the output signal of the second logic circuit to the outside of the circuit cell;
The selection circuit includes a selection element that is inserted into a signal path between the plurality of nodes and the first input terminal and selects and outputs one of the two input signals.
The selection element is
A first input node and a second input node;
An output node;
Connected between the first input node and the output node, and is turned on when a predetermined signal of the plurality of signals input to the second logic circuit has a first value, and the first A first switch that turns off when having a second value obtained by logically inverting the value;
A second node connected between the second input node and the output node and turned on when the output signal of the second logic circuit has the first value and turned off when the second signal has the second value. Including switches and
The semiconductor integrated circuit according to claim 1. The circuit cell further includes a wiring that connects a wiring for transmitting an output signal of the second logic circuit and at least a part of the plurality of input terminals according to a logic function configured in the circuit cell.
The semiconductor integrated circuit according to claim 7 . The circuit cell further includes a third logic circuit that calculates and outputs an inverted logical product of signals input from at least a part of the plurality of input terminals,
The predetermined signal group includes an output signal of the third logic circuit and at least one of a plurality of signals input to the third logic circuit.
The semiconductor integrated circuit according to claim 1. The circuit cell further includes a third amplifier circuit that amplifies a signal input from the input terminal and inputs the signal to the third logic circuit,
The predetermined signal group includes a signal amplified in the third amplifier circuit.
The semiconductor integrated circuit according to claim 9 . The circuit cell further includes a third output terminal that outputs an output signal of the third logic circuit to the outside of the circuit cell.
The semiconductor integrated circuit according to claim 9 . The circuit cell further includes a wiring that connects a wiring for transmitting an output signal of the third logic circuit and at least a part of the plurality of input terminals according to a logic function configured in the circuit cell.
The semiconductor integrated circuit according to claim 9 . A semiconductor integrated circuit configured by connecting a plurality of circuit cells whose logic functions can be adaptively configured,
The circuit cell is
Multiple input terminals,
A first output terminal;
From a predetermined signal group, among signals input a signal corresponding to the configured logic function to the circuit cells and a plurality of nodes respectively input, on SL plurality of nodes, at least of the plurality of input terminals A selection circuit for outputting a signal selected according to a signal input from a part to the first output terminal, a plurality of first wirings formed in a first wiring layer and connected to the plurality of nodes, A plurality of second wirings that are formed on a second wiring layer covering the first wiring layer and transmit each signal of the predetermined signal group, and any one of the plurality of second wirings are connected via a via A lookup table having one or more third wirings selectively connected to the first wiring according to a logic function configured in the circuit cell ;
When the via is not formed and the first terminal is insulated from the plurality of nodes, an AND operation of signals inputted to at least a part of the plurality of input terminals is calculated and output, and the via Is formed and the first terminal is connected to at least one of the plurality of nodes to operate as a lookup table, a signal selected in the lookup table is supplied from an output terminal of the lookup table, A logic circuit having a buffer function for amplifying and outputting the supplied signal ;
A second output terminal for outputting an output signal of the logic circuit to the outside of the circuit cell;
The selection circuit includes a selection element that is inserted into a signal path between the plurality of nodes and the first output terminal and selects and outputs one of two input signals.
The selection element is
A first input node and a second input node;
An output node;
It is connected between the first input node and the output node, and is turned on when a predetermined signal among the plurality of signals input to the logic circuit has a first value, and the first value is logically A first switch that turns off when having an inverted second value;
A second switch connected between the second input node and the output node and turned on when the output signal of the logic circuit has the first value and turned off when the output signal has the second value; including,
Semiconductor integrated circuit. The circuit cell further includes a wiring that connects a wiring that transmits an output signal of the logic circuit and at least a part of the plurality of input terminals according to a logic function configured in the circuit cell.
The semiconductor integrated circuit according to claim 13 . The circuit cell further includes an inverter circuit that logically inverts a signal input from a predetermined input terminal of the plurality of input terminals,
The predetermined signal group includes an input signal and an output signal of the first inverter circuit.
The semiconductor integrated circuit according to claim 13 . The circuit cell further includes a first amplifier circuit that amplifies a signal input from the predetermined input terminal and inputs the signal to the inverter circuit,
The predetermined signal group includes a signal amplified in the first amplifier circuit.
The semiconductor integrated circuit according to claim 15 . The circuit cell includes a second amplifier circuit that amplifies the signal selected in the selection circuit and outputs the amplified signal to the first output terminal.
The semiconductor integrated circuit according to claim 13 . The first switch and the second switch each include an n-channel insulated gate transistor.
The semiconductor integrated circuit according to claim 13 . The first switch and the second switch include an n-channel insulated gate transistor and a p-channel insulated gate transistor that are connected in parallel and are driven to be turned on or off in common.
The semiconductor integrated circuit according to claim 13 . The circuit cell further includes a third logic circuit that calculates and outputs an inverted logical product of signals input from at least a part of the plurality of input terminals,
The predetermined signal group includes an output signal of the third logic circuit and at least one of a plurality of signals input to the third logic circuit.
The semiconductor integrated circuit according to claim 13 . The circuit cell further includes a third amplifier circuit that amplifies a signal input from the input terminal and inputs the signal to the third logic circuit,
The predetermined signal group includes a signal amplified in the third amplifier circuit.
The semiconductor integrated circuit according to claim 20 . The circuit cell further includes a third output terminal that outputs an output signal of the third logic circuit to the outside of the circuit cell.
The semiconductor integrated circuit according to claim 20 . The circuit cell further includes a wiring that connects a wiring for transmitting an output signal of the third logic circuit and at least a part of the plurality of input terminals according to a logic function configured in the circuit cell.
The semiconductor integrated circuit according to claim 20 .

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