JP4483775B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an impurity diffusion region by ion implantation and thermal diffusion.

  When the impurity diffusion region is formed by ion implantation and thermal diffusion, the crystallinity of the ion implanted region deteriorates due to the ion implantation. Crystal defects will occur in the periphery.

  Therefore, conventionally, as a countermeasure method, after the ion implantation into the semiconductor substrate, the first heat treatment for the purpose of recovering the crystallinity is performed, and then the drive-in for activating and thermally diffusing the impurities, A method of performing a second heat treatment at a higher temperature than the first heat treatment has been proposed (see, for example, Patent Documents 1, 2, and 3).

According to this method, the generation of crystal defects can be suppressed, and the occurrence of leakage defects in the manufactured semiconductor device can be suppressed.
Japanese Patent Publication No. 7-95537 Japanese Patent No. 026972222 JP-A-6-45270

  However, in the above-described conventional method for manufacturing a semiconductor device, a trench is formed at a position sandwiching a region in the semiconductor substrate, and the trench is filled with a filling material, and then an impurity diffusion region is formed in the region by ion implantation. In this case, even if the first heat treatment is performed after the ion implantation, the crystallinity cannot be sufficiently recovered.

  The reason for this is that stress is applied to the ion-implanted region from the trench filling material, so that greater energy is required to restore crystallinity than when the ion-implanted region is not sandwiched between trenches. However, in the conventional method described above, since the heat treatment temperature in the first heat treatment is lower than the second heat treatment temperature, it is estimated that the energy is insufficient to recover the crystallinity.

  As described above, the above-described conventional method for manufacturing a semiconductor device is an effective method when no stress is applied to the ion implantation region. However, when the stress is applied from the trench filling material to the ion implantation region, the method is sufficient. It is thought that the effect cannot be exhibited.

  In view of the above, the present invention provides a semiconductor capable of suppressing the occurrence of crystal defects in and around the impurity diffusion region when an impurity diffusion region is formed in a region sandwiched between trenches of a semiconductor substrate by an ion implantation method. An object is to provide a method for manufacturing a device.

  In order to achieve the above object, the present invention provides a trench forming step (S2) for forming a trench (6) in a semiconductor substrate (4), and a burying step for embedding a filling material (7, 8) in the trench (6) ( S3), an ion implantation step (S6) for implanting ions into a region (5) around the trench (6) that receives stress from the filling material (7, 8) in the semiconductor substrate (4), and a first heat treatment step (S7) and a second heat treatment step (S8), and the first heat treatment step (S7) performs the heat treatment at a temperature higher and shorter than the heat treatment temperature and heat treatment time in the second heat treatment step (S8). It has a feature.

  When the filling material is buried in the trench, the region around the trench is in a state where stress is applied from the filling material. In the present invention, the first heat treatment step is performed at a higher temperature than the second heat treatment step. Therefore, even if ions are implanted into this region, the crystallinity in this region can be recovered, and the generation of crystal defects in the impurity diffusion region and its periphery can be suppressed. Since the heat treatment time in the first heat treatment step is short, an impurity region having a desired diffusion depth can be formed even after the second heat treatment step for the purpose of drive-in.

  Specifically, in the step of preparing a semiconductor substrate (S1), a semiconductor substrate (4) having a structure in which a first semiconductor layer (1), an insulating layer (2), and a second semiconductor layer (3) are stacked in this order is formed. In the trench formation step (S2) prepared, the depth reaches the insulating layer (2) from the surface of the second semiconductor layer (3) and surrounds one region (5) of the second semiconductor layer (3). A trench (6) is formed at the position. In the ion implantation step (S6), ions are implanted into this region (5).

  Thus, in the layout on the substrate surface, when one region (5) is surrounded by the trench, the stress applied to the one region is large. Therefore, in this case, it is particularly effective to apply the present invention. .

In the trench formation step (S2), it is preferable to form the trench (6) so that the area of one region (5) is less than 2.5 × 10 ⁴ μm.

  In this case, since the stress applied to one region is larger than the case where the area of one region is larger than this, it is particularly effective to apply the present invention to this case.

  In the trench formation step (S2), it is preferable to form a trench (6) having a depth of 11 to 16 μm.

  In the semiconductor device having the above-described structure, the second semiconductor layer (3) generally has a thickness of 2 to 3 μm and a trench depth of 2 to 3 μm. Since the stress applied to one region is larger when the depth of the trench is 11 to 16 μm, it is particularly effective to apply the present invention in this case.

  In the ion implantation step (S6), it is preferable to use boron as the ion species. When boron is used as the ion species, crystal defects are more likely to occur than when other ion species are used. In this case, it is particularly effective to apply the present invention.

  In the second heat treatment step (S8), the heat treatment is preferably performed at a heat treatment temperature of 1050 to 1200 ° C. and a heat treatment time of 10 to 80 minutes.

  In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

(First embodiment)
First, the semiconductor device manufactured in this embodiment will be described. FIG. 1 is a plan view of an LDMOS that is a semiconductor device manufactured in the present embodiment, and FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 1 mainly shows a layout of trenches, source and drain regions on the surface of the semiconductor substrate.

  As shown in FIGS. 1 and 2, the semiconductor device manufactured in this embodiment includes a single crystal Si substrate 1 as a first semiconductor layer, an oxide film 2 as an insulating layer, and a single crystal Si layer (as a second semiconductor layer). In an SOI structure semiconductor substrate 4 composed of an SOI layer 3, the SOI layer 3 is insulated and separated from an element region 5 as a region where a device (transistor) is formed and a region around the element region 5. In this structure, an element isolation trench 6 is formed. In the present embodiment, a semiconductor substrate made of Si is used, but a semiconductor substrate made of a material other than Si can also be used.

  As shown in FIG. 1, the element isolation trench 6 surrounds the entire periphery of the element region 5 and has a depth reaching the oxide film 2 in the semiconductor substrate 4 as shown in FIG. Hereinafter, the element region 5 surrounded by the trench 6 is referred to as a trench island 5. The shape of the trench island 5 on the substrate surface is a quadrangle.

  Further, as shown in FIG. 2, an oxide film 7 and a PolySi layer 8 as a filling material are formed in the trench 6. On the surface of the SOI layer 3, an oxide film 9 (hereinafter referred to as a LOCOS oxide film 9) formed by a LOCOS method as a field insulating film, and a gate insulating film and a gate electrode (not shown) are formed. . Of the plurality of source formation regions 10 and drain formation regions 11 in which the LOCOS oxide film 9 is not formed in the surface layer of the trench island 5, the source formation region 10 includes a P-type impurity diffusion region (for channel formation). (Hereinafter referred to as a channel P-type region) 12 and a P-type impurity diffusion region 13 for suppressing the operation of the parasitic transistor are formed. This P-type impurity diffusion region 13 has a depth (hereinafter referred to as diffusion depth) 14 from the substrate surface of about 2 μm. Further, an N-type source region (not shown) is formed on the inner surface side of the channel P-type region 12. On the other hand, an N-type drain region (not shown) is formed in the drain formation region 11.

  Next, a method for manufacturing the semiconductor device having the above structure will be described. FIG. 3 shows a flowchart of this manufacturing method. Hereinafter, description will be given with reference to FIGS.

  First, step S1 for preparing a semiconductor substrate 4 having an SOI structure is performed. At this time, the thickness of the SOI layer 3 in FIG. 2 is, for example, 11 to 16 μm.

  Subsequently, step S2 of forming an element isolation trench 6 in the SOI layer 3 is performed. At this time, as shown in FIG. 1, the trench 6 is formed at a position completely surrounding the element region 5 of the SOI layer 3 so that the shape on the substrate surface becomes a square frame shape.

  At this time, as shown in FIG. 2, the depth of the trench 6 is the same as the depth reaching the oxide film 2 under the SOI layer 3, that is, the thickness of the SOI layer 3, for example, 11 to 16 μm. Further, the width of the trench 6 on the substrate surface is set to 2 μm, for example.

Thereby, an element region (trench island) 5 surrounded by the trench 6 is formed. In other words, the element region 5 is defined by the trench 6. In addition, the shape on the substrate surface of the trench island 5 is a quadrangle, and the area is, for example, 1 mm ² or less, and is preferably less than 2.5 × 10 ⁴ μm ² for the reason described later.

  Subsequently, a process S3 for filling the inside of the trench 6 with the oxide film 7 and the PolySi layer 8 is performed. In this step, when the PolySi layer 8 is buried in the trench 6, stress is applied from the PolySi layer 8 to the element region 5 through the oxide film 7 in the trench 6. In the present embodiment, the element region 5 corresponds to a region around the trench described in the claims.

  Subsequently, step S4 for forming a LOCOS oxide film 9 on the surface of the SOI layer 3 is performed. At this time, the thickness of the LOCOS oxide film 9 is set to, for example, 950 nm.

Also at this time, stress is applied to the trench island 5 from the edges 9a, 9b, 9c, 9d of the LOCOS oxide film 9. Here, FIG. 4 shows the result of measuring the stress applied to the trench island 5 immediately after this step. This measurement result is a result measured by Raman spectroscopy. As can be seen from FIG. 4, when the area of the trench island 5 is 1 mm ² or less, a stress of about 130 MPa or more is applied to the trench island 5.

  Subsequently, step S5 of forming a gate electrode on the surface of the SOI layer 3 through a gate insulating film is performed.

Subsequently, after forming the channel P-type region 12, a step S <b> 6 of performing ion implantation into the plurality of source formation regions 10 in the trench island 5 is performed in order to form the P-type impurity diffusion region 13. At this time, for example, B (boron) is used as the ion species, the dose amount is 5 × 10 ¹⁵ cm ⁻² , and the ion implantation energy is 70 keV.

Subsequently, a first heat treatment (lamp annealing) step S7 for performing heat treatment on the trench island 5 of the semiconductor substrate 4 is performed. In this process, a lamp heating RTP (Rapid Thermal Process) apparatus is used as the heat treatment apparatus, and the heat treatment is performed in, for example, an N ₂ atmosphere.

  At this time, the heat treatment temperature is set higher than the heat treatment temperature in the second heat treatment step to be described later so that the crystallinity in the trench island 5 in the state where the stress from the PolySi layer 8 in the trench 6 is applied can be recovered. In addition, the heat treatment time is set shorter than the heat treatment time in the second heat treatment step so that the P-type impurity diffusion region 13 having a desired diffusion depth can be formed in the second heat treatment step.

Here, FIG. 5 shows the results of investigating leakage defects when the first heat treatment step is performed at various heat treatment temperatures and heat treatment times. As a result, the thickness of the SOI layer 3, the ion implantation conditions, and the like are the conditions exemplified in this embodiment. The area of the trench island 5 is 1.23 × 10 ³ μm ² and the second heat treatment step is performed. This is the result of investigating the leak between the source and drain after forming the protective film through the normal wiring process after performing the manufacturing process shown in FIG. 3 under the heat treatment condition of 1050 ° C. × 80 minutes.

  As shown in FIG. 5, when the heat treatment temperature was 1050 ° C., the occurrence rate of leakage failure exceeded 1% regardless of the heat treatment time. Further, when the heat treatment temperatures are 1100 ° C., 1150 ° C., and 1180 ° C., when the heat treatment time is 10 seconds, the occurrence rate of leakage failure is less than 1%, and when the heat treatment time is 30 seconds and 50 seconds, the leakage failure occurs. The occurrence rate of was 0%. Note that if the occurrence rate of the leak failure is less than 1%, it can be said that the occurrence rate of the leak failure is reduced as compared with the case where the first heat treatment S7 is not performed.

  Therefore, when the process shown in FIG. 3 is performed under the above-described conditions, the heat treatment temperature is set to 1100 ° C. or higher, and the heat treatment time is set to 10 seconds or longer. More preferably, it is 30 seconds or more. This is because the occurrence rate of leakage failure can be reduced to 0% by setting it to 30 seconds or longer. Further, the upper limit of the heat treatment temperature is lower than the melting point of the semiconductor substrate, but since the limit temperature of the RTP apparatus is usually 1250 ° C., the upper limit is 1250 ° C. Further, the heat treatment time varies depending on the degree of influence on the device, but does not have an influence (in order to form the P-type impurity diffusion region 13 having a desired diffusion depth in the second heat treatment step), that is, impurity ions In order to prevent the thermal diffusion of this, it has been found by the inventors that less than 60 seconds is preferable.

  From the above, the heat treatment conditions in this step are set to temperature: 1100 to 1250 ° C. and time: about 10 to 60 seconds.

The heat treatment temperature and heat treatment time are the results when the ion implantation conditions in the ion implantation step S6 are ion species B (boron) and the dose amount is 5 × 10 ¹⁵ dose. If the amount of heat treatment increases, the range of the heat treatment conditions will be higher and longer, and if the dose is reduced, the temperature will be lower and shorter. Therefore, it is estimated to shift.

  Similarly, the heat treatment temperature and the heat treatment time are those when the thickness of the SOI layer 3, that is, when the depth of the trench 6 is 11 to 16 μm, but the stress from the trench 6 to the trench island 5 is reduced. Since the influence depends on the depth of the trench 6, that is, the thickness of the SOI layer 3, if the SOI layer 3 is thicker than 11 to 16 μm, the higher the temperature and the longer time the SOI layer 3 is. If it is thin, it is estimated that the temperature shifts to a shorter time side at a lower temperature within a range satisfying the relationship of a higher temperature and a shorter time than the second heat treatment step.

Similarly, the heat treatment temperature and the heat treatment time are those when the area of the trench island 5 is 1.23 × 10 ³ μm ² and the heat treatment conditions in the second heat treatment step are 1050 ° C. × 80 minutes, Depending on the area of the trench island 5 and the heat treatment conditions in the second heat treatment step, it seems to vary within a range satisfying the relationship of higher temperature and shorter time than the second heat treatment step.

Thereafter, a second heat treatment (drive-in) step S8 is performed to heat-treat the trench island 5 of the semiconductor substrate. In this step, a furnace is used as a heat treatment apparatus, and heat treatment is performed in an N ₂ atmosphere.

  At this time, the heat treatment temperature and the heat treatment time are set to a temperature and a time at which the impurity diffusion region can be formed by thermally diffusing the introduced ions. For example, the heat treatment temperature is 1000 ° C. or more (more preferably 1050 ° C. or more) 1200 ° C. or less, and the heat treatment time is 10 minutes or more and 80 minutes or less. In the present embodiment, in order to set the diffusion depth 14 of the P-type impurity diffusion region 13 to about 2 μm, for example, 1050 ° C. × 80 minutes. Thereby, a P-type impurity diffusion region 13 having a desired diffusion depth (about 2 μm) is formed.

  Thereafter, although not shown, an IC product (semiconductor device) is manufactured through a wiring formation process, a dicing process, a packaging process, and the like.

  Next, main effects of this embodiment will be described.

  As described above, in this embodiment, after the ion implantation step S6 and before the second heat treatment step S8 for the purpose of drive-in, the first heat treatment is performed at a higher temperature and in a shorter time than the second heat treatment step. One heat treatment step S7 is performed.

  As a result, the P-type impurity diffusion region 13 having a desired diffusion depth can be formed, that is, even if stress is applied to the trench island 5 without substantially changing the target device characteristics, Damage recovery (crystallinity recovery) in the trench island 5 of the semiconductor substrate 4 can be achieved, and generation of crystal defects due to damage can be suppressed. As a result, it is possible to reduce leakage defects of the device (LDMOS).

Here, as a reference, FIG. 6 shows the relationship between the yield (leakage yield) and the trench island area investigated based on the presence or absence of leakage defects in the semiconductor device manufactured by the manufacturing method of the present embodiment. In addition, in FIG. 6, the investigation result of the semiconductor device manufactured by omitting the first heat treatment step with respect to the manufacturing method of the present embodiment is also shown. These results also indicate that the ion implantation conditions in the ion implantation step S6 are B (boron) as the ion species, the dose amount is 5 × 10 ¹⁵ dose, and the first heat treatment step S7 and the second heat treatment step. The heat treatment conditions in S8 are the results when 1180 ° C. × 30 seconds and 1050 ° C. × 80 minutes, respectively.

From the results shown in FIG. 6, when the area of the trench island 5 is 1 mm ² or less, the method of this embodiment is compared with the method in which the first heat treatment step S7 is not performed (no first heat treatment). It can be seen that the yield is high.

In particular, as shown in FIG. 6, in the method in which the first heat treatment step S7 is not performed, the yield was low at 1.23 × 10 ³ μm ² (0.00123 mm ² ). This is presumably due to the following reasons. As shown in FIG. 4, when the area of the trench island 5 is 2.5 × 10 ⁴ μm ² (0.025 mm ² ) or more, the stress value is about 130 MPa, which is almost the same, but the area of the trench island 5 is When it is less than 2.5 × 10 ⁴ μm ² (0.025 mm ² ), it is 143 MPa at 7.6 × 10 ³ μm ² , 156 MPa at 2.3 × 10 ³ μm ² , 1.6 × 10 ³ μm ² when 165 MPa, a 172MPa when 5.8 × 10 ² μm ^2, the stress tends to increase is observed as the area becomes smaller. Therefore, when the area of the trench island 5 is smaller than 2.5 × 10 ⁴ μm ² (including the case of 1.23 × 10 ³ μm ^{2 in} this case), the inside of the trench island 5 6 and LOCOS oxide film 9 are particularly strongly affected by the stress, and it is assumed that damage recovery by ion implantation is not sufficiently performed only by heat treatment for drive-in, and crystal defects are likely to occur. .

On the other hand, according to the present embodiment, for example, even when the area of the trench island 5 is small as in the case of 1.23 × 10 ³ μm ² (0.00123 mm ² ), the first heat treatment is performed. Compared with a method in which a process is not performed, the yield can be improved. That is, it can be said that the effect of this embodiment is remarkable when the area of the trench island 5 is in a range where the stress applied to the trench island 5 is particularly large, that is, when the area is smaller than 2.5 × 10 ⁴ μm ² .

  In addition, the semiconductor device manufacturing method of this embodiment is designed to include the first heat treatment step S7 from the beginning at the time of the process design. However, the first heat treatment step S7 can be added after the process design. Have.

  That is, in this embodiment, the heat treatment temperature and heat treatment time in the first heat treatment step S7 have an influence on the device characteristics so that the P-type impurity diffusion region 13 having a desired diffusion depth can be formed in the second heat treatment step S8. There is no set temperature and time. For this reason, when designing the manufacturing process, the first heat treatment process S7 is not considered, and when the process design is performed and it is found that crystal defects occur after the process design, the first heat treatment process S7 is added for the first time. Thus, it is possible to cope with the occurrence of crystal defects without redesigning the process.

  Note that the conventional techniques described in Patent Documents 1 to 3 described in the background section above have a shallow diffusion depth, as can be seen from the low temperature and the short time of the second heat treatment (drive-in). The purpose was to form an impurity diffusion layer (about 0.1 to 0.2 μm).

  In this case, if the temperature during the first heat treatment is higher than that of the second heat treatment, the diffusion depth of the impurity diffusion region becomes greater than a desired size. In addition, if drive-in is performed in a short time, it is difficult to perform the first heat treatment in a shorter time than the second heat treatment for the purpose of performing only damage recovery without affecting the drive-in. For this reason, conventionally, the first heat treatment temperature must be lower than that of the second heat treatment.

  In contrast, the present embodiment is intended for a semiconductor device having an impurity diffusion layer deeper than a semiconductor device targeted by a conventional semiconductor device manufacturing method having a depth from the substrate surface of, for example, about 2 μm. Therefore, the heat treatment temperature and heat treatment time in the first heat treatment step S7 can be made higher and shorter than those in the second heat treatment step.

(Other embodiments)
(1) In the first embodiment, the case where the shape of the trench island 5 on the substrate surface is a square has been described as an example. However, other shapes such as a circle and a polygon may be used. Even if the shape of the trench island 5 is different from that of the first embodiment, it is presumed that the heat treatment temperature and the heat treatment time in the first heat treatment step S7 are the same as long as they have the same area.

  (2) In the first embodiment, the depth of the trench 6 is set to reach the oxide film 2. However, if the trench island 5 is subjected to stress, the depth of the trench 6 is arbitrarily changed. Also good. For example, the trench may be shallow like STI.

  (3) In the first embodiment, the case where the element region 5 to be ion-implanted is completely surrounded by the trench 6 is described as an example. However, the element region may not necessarily be completely surrounded, and at least, The present invention can be applied when an ion-implanted region is located around the trench and receives stress from a filling material such as the PolySi layer 8 in the trench.

  In the first embodiment, the case of forming a trench for element isolation has been described as an example. However, the same applies to the case of forming a trench for another purpose such as a trench gate.

  For example, the present invention is applied when an impurity diffusion region is formed in a region sandwiched between two opposing trenches when the trench is planarly laid out like a trench gate. You can also

  (4) In the first embodiment, the case where the semiconductor substrate 4 having an SOI structure is used has been described as an example. However, a semiconductor substrate having another structure can also be used.

  (5) In the first embodiment, the case where the heat treatment temperature and the heat treatment time in the first heat treatment step S7 are set to a temperature and time at which impurity ions are not thermally diffused has been described as an example. If the impurity diffusion region having a desired diffusion depth can be formed in the second heat treatment step and the temperature is higher than that in the second heat treatment step and within a short time, the temperature and time at which the impurity ions are thermally diffused are set. May be.

  (6) In the first embodiment, the case where the present invention is applied to the formation of the P-type impurity diffusion region 13 has been described as an example. However, other impurity diffusion regions such as the formation of the channel P-type region 12 are described. The present invention can also be applied to the formation of. That is, the present invention can be applied to the formation of an impurity diffusion region that can be formed by the present invention and has a diffusion depth larger than 0.2 μm.

2 is a planar layout of the semiconductor device according to the first embodiment of the present invention. It is the sectional view on the AA line in FIG. 3 is a flowchart showing a manufacturing process of the semiconductor device shown in FIGS. It is a figure which shows the relationship between the area of trench island 5, and the magnitude | size of the stress applied to trench island. FIG. 4 is a diagram showing a relationship between a heat treatment temperature and a heat treatment time in a first heat treatment step S7 in FIG. 3 and a leak defect occurrence rate in a manufactured semiconductor device. It is a figure which shows the relationship between the yield investigated by the presence or absence of the leak defect of the semiconductor device manufactured with the manufacturing method of 1st Embodiment, and the method which does not perform 1st heat treatment process S7, and a trench island area.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Single crystal Si substrate, 2 ... Oxide film, 3 ... Single crystal Si layer (SOI layer),
4 ... Semiconductor substrate, 5 ... Element region (trench island), 6 ... Trench,
7 ... oxide film, 8 ... PolySi layer, 10 ... source formation region, 11 ... drain formation region,
12 ... Channel P-type region, 13 ... P-type impurity diffusion region.

Claims (6)

A step (S1) of preparing a semiconductor substrate (4);
A trench forming step (S2) for forming a trench (6) in the semiconductor substrate (4);
An embedding step (S3) for embedding an embedding material (7, 8) in the trench (6);
An ion implantation step (S6) in which ions are implanted into a region (5) around the trench (6) that receives stress from the filling material (7, 8) of the semiconductor substrate (4);
A first heat treatment step (S7) for performing heat treatment on the semiconductor substrate (4) in order to recover the crystallinity in the region (5) after the ion implantation step;
After the first heat treatment step, the semiconductor substrate (4) is subjected to a heat treatment to form an impurity diffusion region in the region (5) by thermally diffusing ions introduced into the region (5). A second heat treatment step (S8) to be performed,
In the semiconductor device manufacturing method, the first heat treatment step (S7) is performed at a temperature higher and shorter than the heat treatment temperature and the heat treatment time in the second heat treatment step (S8). In the step (S1) of preparing the semiconductor substrate, a semiconductor substrate (4) having a structure in which a first semiconductor layer (1), an insulating layer (2), and a second semiconductor layer (3) are stacked in this order is prepared.
In the trench forming step (S2), the depth reaches the insulating layer (2) from the surface of the second semiconductor layer (3), and a region (5) of the second semiconductor layer (3) is formed. Forming the trench (6) in a surrounding position;
2. The method of manufacturing a semiconductor device according to claim 1, wherein in the ion implantation step (S6), ions are implanted into the one region (5). The trench (6) is formed in the trench formation step (S2), so that the area of the one region (5) is less than 2.5 × 10 ⁴ μm. A method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein in the trench formation step (S <b> 2), the trench (6) having a depth of 11 to 16 μm is formed. 5. 5. The method of manufacturing a semiconductor device according to claim 1, wherein boron is used as an ion species in the ion implantation step (S <b> 6). 6. The method of manufacturing a semiconductor device according to claim 1, wherein in the second heat treatment step (S8), the heat treatment is performed at a heat treatment temperature of 1050 to 1200 [deg.] C. and a heat treatment time of 10 to 80 minutes.

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