JP4466833B2 - Bus control device - Google Patents

Description

  The present invention relates to a bus control device, and more particularly to a bus control device that efficiently transmits and receives data when an upper system accesses a lower system.

As shown in FIG. 5, the bus control device in the prior art has a host system 111 having a host bus 112 for connecting to the host system 117, a function of connecting to the host bus 112, and via the host bus 113. And a lower system 117 having a bus interface 116 for controlling transmission / reception and control of data with the microprocessor 114 and the memory 115.
The lower system 117 includes a plurality of systems, each of which is connected to the upper bus 112 to transmit / receive data to / from the higher system 111 and to transmit / receive data to / from other lower systems 117.

  The lower system 117 includes at least a lower bus 113, and a bus interface 116 connected to the upper bus 112, a microprocessor 114, and a memory 115 are connected via the lower bus 113. In order to release the lower bus 113, a bus release request (BREQ) is output from the bus interface 116, and when the bus release response (BACK) is received from the microprocessor 114, the lower bus 113 is released. The memory 115 can be accessed via the.

The bus control device having such a configuration will be described with reference to the flowchart shown in FIG.
First, in response to a data write / read request from the upper system 111 to the lower system 117, the microprocessor (bus master) 114 of the lower system 117 opens the lower bus 113 to realize the operation.
In other words, the bus interface 116 of the lower system 116 sends a bus release request (BREQ) to the microprocessor if the host system 111 has requested access to the resources of the lower system 117 from the upper system 111 (such as writing to and reading from the memory). 114, and a bus release response (BACK) is obtained (steps ST11, ST12, ST13, ST14). Thereafter, the bus interface 116 of the lower system 117 occupies the lower bus 113, and performs writing and reading of data to and from resources such as the memory 115 (step ST15). After execution, the bus release request (BREQ) to the microprocessor 114 is canceled, the bus right is returned to the microprocessor 114, and a series of accesses is completed (step ST16).

Japanese Unexamined Patent Publication No. 2003-281084 (page 4, Fig. 1)

  However, according to the access method in the bus control apparatus described in the prior art, the bus interface in the lower system, in accordance with the request from the higher system, unconditionally releases the bus to the microprocessor and then resources such as memory in the lower system. Data is written to and read from. Here, since the operation of the microprocessor of the lower system is stopped during the bus opening period, there is a problem that the operation efficiency of the lower system is hindered.

Further, since the response from the lower system is also realized after the bus release request (BREQ) and the bus release response (BACK), there is a problem that the upper system also has a longer response waiting time.
As described above, the conventional method has a problem that the operating efficiency is deteriorated in both the lower system and the upper system.

  Therefore, there is a problem that must be solved to avoid the deterioration of the operation efficiency of both the upper system and the lower system due to the bus opening and opening procedures.

In order to solve the above problems, the bus control device of the present invention is configured as follows.
(1) The bus control device
A host system with a host bus;
A lower system having a lower level bus connected to a memory as a resource and a bus interface having an interface function with the upper level bus, and
The bus interface is
The buffer unit having an area for storing an address when accessing the resource and an area for storing data corresponding to the address functions to store the address and data at the time of access. 1 control unit;
A second control unit having a function of referring to the address and data stored in the buffer unit,
The first control unit constantly monitors access to the resource of the lower system, compares an address stored in the buffer unit with an address when the resource is accessed, and In the case of writing to an address to function, it functions to rewrite the data corresponding to the address at the time of writing stored in the buffer unit,
Said second control unit, when from the host system an access request to the resource to the subsystems, with reference to whether the data of the address is stored in the buffer unit,
When the address is not stored in the buffer unit, the bus of the lower bus is released, and the resource of the lower system is accessed,
When the address is stored in the buffer unit,
If the access from the higher system to the lower system is read, the data stored in the buffer unit is read and returned to the higher system,
When the access from the higher system to the lower system is writing,
If the data to be written does not match the data stored in the buffer unit, write processing to the resource of the lower system,
When the data to be written coincides with the data stored in the buffer unit, it functions so as not to perform the writing process.

  The bus control device of the present invention prepares, as a buffer, an address and data for accepting a request from a higher system in a bus interface of a lower system in a system composed of a higher system having a higher bus and a lower system having a lower bus. In addition, when there is an access, the buffered data at the relevant address is passed to the host system, so that the lower-level system occupies the lower-level bus as much as possible. There is an effect that can be avoided.

  Hereinafter, the bus control device of the present invention will be described in detail with reference to the drawings.

As shown in FIG. 1, the bus control device of the present invention has a host system 11 having a host bus 12 for connecting to the host system 17, a function for connecting to the host bus 12, and via the host bus 13. And a lower system 17 having a bus interface 16 for controlling transmission / reception and control of data with the microprocessor 13 and the memory 15.
The lower system 17 includes a plurality of systems, each of which is connected to the upper bus 12 to transmit / receive data to / from the higher system 11 and to transmit / receive data to / from another lower system 17.

  The lower system 17 includes at least a lower bus 13, and a bus interface 16 connected to the upper bus 12, a microprocessor 14, and a memory 15 that is a resource are connected via the lower bus 13. To release, a bus release request (BREQ) is output from the bus interface 16, and when the bus release response (BACK) is received from the microprocessor 14, the lower bus 13 is released, and the bus interface 16 sends data to the memory 15. Access is possible.

  As shown in FIG. 2, when the resource is accessed, the bus interface 16 accesses a buffer unit 18 including an area for storing the address and an area for storing data corresponding to the address. A first control unit that functions to store the time address and data, and a second control unit that has a function of referring to the buffer unit, the first control unit and the second control unit Is configured to operate individually.

  The first control unit is a “mechanism for monitoring resource update and storing it in the buffer unit 18”, and as shown in FIG. 3, it always accesses the resource (memory 15) of the lower system 17. Monitoring and comparing with the address of the buffer unit 18, when there is a write to the corresponding address of the lower system 17, it functions to rewrite the data of the buffer unit 18 at the same time (steps ST21 and ST22).

The second control unit is a “mechanism for referring to the buffer unit 18”. When the access request to the resource (memory 15) from the higher system 11 to the lower system 17 is made, as shown in FIG. In addition, it is confirmed whether the data at the address is buffered in the buffer unit 18 (steps ST31, ST32, ST33).
If the address is not buffered in step ST33, a conventional bus release request (BREQ) for the lower level bus 13 is made, and a bus release response (BACK) from the microprocessor 14 is awaited (steps ST38 and ST39). .
If there is a bus release response in step ST39, then the resources of the lower system 17 are accessed, the bus is released, the address of the target buffer is updated, and a series of read or write processing is performed. Completion (steps ST40, ST41, ST36).

If the address is buffered in step ST33 and the access is read, the data buffered in the buffer unit 18 is read and returned to the host system 11 (steps ST34, ST35, ST36).
In step ST34, when the access is a write and the data to be written does not match the buffered data, the data is written to the resource (memory 15) of the lower system 17 by the conventional access method (steps ST38, ST39, ST40). , ST41).
If the buffered data and the write data match in step ST37, the write process is not performed, the above process is executed according to the buffer state and the access type, and the buffer address is updated and monitored. It adds to an address (step ST36).

  As described above, in this method, when accessing the resource (memory 15) of the lower system 17, the microprocessor 14 of the lower system 17 releases the bus and stops it. There is no need to open the bus except when there is no buffered data or when the buffered data is rewritten to a different value, and the deterioration of the operating efficiency of the lower system 17 can be reduced.

  Prepare an address and data for accepting requests from the host system in the bus interface of the lower system, and when the access is made, pass the data at that address to the host system to occupy the lower bus of the lower system. Provided is a bus control device that avoids deterioration of the operating efficiency of both the host system and the lower system by eliminating as much as possible.

It is a block diagram of the bus control device of the present invention It is explanatory drawing which showed the structure of the buffer part similarly. 3 is a flowchart showing a mechanism of resource update monitoring and buffer update. 3 is a flowchart showing the operation of the bus interface of the lower system. It is a block diagram of the bus control apparatus in a prior art. It is the flowchart which showed operation | movement of the bus interface of the low-order system in a prior art.

Explanation of symbols

11 Host system 12 Upper bus 13 Lower bus 14 Microprocessor 15 Memory 16 Bus interface 17 Lower system 18 Buffer section.

Claims (1)

A host system with a host bus;
A lower system having a lower level bus connected to a memory as a resource and a bus interface having an interface function with the upper level bus, and
The bus interface is
The buffer unit having an area for storing an address when accessing the resource and an area for storing data corresponding to the address functions to store the address and data at the time of access. 1 control unit;
A second control unit having a function of referring to the address and data stored in the buffer unit,
The first control unit constantly monitors access to the resource of the lower system, compares an address stored in the buffer unit with an address when the resource is accessed, and In the case of writing to an address to function, it functions to rewrite the data corresponding to the address at the time of writing stored in the buffer unit,
Said second control unit, when from the host system an access request to the resource to the subsystems, with reference to whether the data of the address is stored in the buffer unit,
When the address is not stored in the buffer unit, the bus of the lower bus is released, and the resource of the lower system is accessed,
When the address is stored in the buffer unit,
If the access from the higher system to the lower system is read, the data stored in the buffer unit is read and returned to the higher system,
When the access from the higher system to the lower system is writing,
If the data to be written does not match the data stored in the buffer unit, write processing to the resource of the lower system,
A bus control device which functions so as not to perform a writing process when data to be written coincides with data stored in the buffer unit.

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