JP4462473B2 - High frequency circuit board and semiconductor device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high-frequency circuit board and a semiconductor device using the same.
[0002]
[Prior art]
In recent years, with the improvement in performance of semiconductor devices, electronic devices using millimeter-wave band radio waves, which have been difficult in the past, are becoming reality. In such an electronic device, a semiconductor element such as an LSI is mounted on a high-frequency circuit board. However, if the frequency used is high, attention should be paid to the structure of the high-frequency circuit board.
[0003]
An enlarged plan view of such a conventional high-frequency circuit board is shown in FIG. As shown in the figure, the high-frequency circuit board includes a polyimide film 1, and the first transmission line 2 and the first conductive ground layer 3 have a coplanar structure on one surface of the polyimide film 1. Formed. A circular first conductive pad 2 a is formed at the end of the first transmission line 2, and an opening 3 a surrounding the first transmission line 2 and the first conductive pad 2 a is formed in the first conductive ground layer 3. It is formed.
[0004]
When this high-frequency circuit board is viewed from the other main surface side, it is as shown in FIG. As shown in the figure, in this plane, the second transmission line 4 and the second conductive ground layer 5 are formed on the polyimide film 1 so as to have a coplanar structure, and the end of the second transmission line 4 is formed. A circular second conductive pad 4a is formed.
[0005]
A cross section of the high-frequency circuit board is shown in FIG. FIG.1 (c) is sectional drawing which follows the II line | wire of Fig.1 (a). As shown, via holes 1a are formed in the polyimide film 1, and the first and second conductive pads 2a and 4a on the front and back are electrically connected to each other through the via holes 1a. The high-frequency signal flows from the first conductive line 2 through the via hole 1a to the second conductive line 4 (or its reverse path).
[0006]
[Problems to be solved by the invention]
By the way, as shown in FIG. 1A, the first conductive pad 4a and the opening 3a of the first conductive ground layer 3 are formed in this high-frequency circuit board. The diameter of the second conductive pad 4a is not particularly specified, and the diameters of the opening 3a and the second conductive pad 4a differ depending on process restrictions such as processing accuracy of the via hole 1a. There may be an overlap portion where the conductive pad 4a and the first conductive ground layer 3 overlap. When the overlap portion exists in this way, as shown in FIG. 1C, the stray capacitance C composed of the second conductive pad 4a and the first conductive ground layer 3 is generated in the vicinity of the via hole 1a. It will be.
[0007]
However, when the stray capacitance C exists in this way, the characteristic impedance of the line in the portion where the stray capacitance C exists is smaller than that in the other portions, so the characteristic impedance of the line varies depending on the location, and the first conductive line 2 The characteristic impedance of the line from to the second conductive line 4 becomes mismatched, and as a result, the high-frequency signal may be reflected in the line and the signal transmission loss may increase.
[0008]
Further, as shown in FIG. 1A, in the above-described coplanar structure, the first transmission line 2 and the first conductive ground layer 3 are always formed in a pair so that a capacitance is formed between them. And the characteristic impedance of the first conductive line 2 is set to a desired value based on the capacitance value and the inductance of the line.
[0009]
However, this coplanar structure is useful for a portion where a high-frequency signal flows in one plane, but in the inside of the first via hole 1a, a pair is formed with the line (second conductive pad 4a) in the via hole 1a. Since there is no ground layer to be made nearby, the capacitance value between the line and the ground layer becomes smaller than other parts, and the characteristic impedance of the line increases.
[0010]
As described above, even in the via hole 1a, the characteristic impedance cannot be matched and the transmission loss as described above may increase.
[0011]
The present invention was created in view of the problems of the related art, and a high-frequency circuit board in which mismatching of characteristic impedance of a line in and near a hole of a dielectric base material was improved and the same were used. An object is to provide a semiconductor device.
[0012]
[Means for Solving the Problems]
The above-described problems are formed on a dielectric substrate and the dielectric substrate. Has a tapered shape A hole, a first transmission line formed on one surface of the dielectric substrate, a first conductive pad provided on the first transmission line to close the hole and having a circular planar shape; A conductive ground layer formed on one surface of the dielectric substrate and having an opening surrounding the first transmission line and the first conductive pad; and on the other surface of the dielectric substrate. The formed second transmission line, provided on the second transmission line, electrically connected to the first conductive pad through the hole, and having a circular planar shape A larger area than the first conductive pad. A high-frequency circuit board comprising: a second conductive pad, wherein the second conductive pad is accommodated in the opening of the conductive ground layer when viewed from above the dielectric base material. Solved by.
[0013]
Next, the operation of the present invention will be described.
[0014]
According to the present invention, when viewed from above the dielectric substrate, the second conductive pad is accommodated in the opening of the conductive ground layer, so that the second conductive pad is overlaid between the second conductive pad and the conductive ground layer. Wrapping part does not occur. As a result, stray capacitance due to the overlap portion does not occur, so that the characteristic impedance of the line through which the high-frequency signal passes is prevented from being mismatched in the vicinity of the hole in the dielectric substrate, and the transmission loss of the high-frequency signal is lower than before. Is also reduced.
[0015]
Further, instead of the above dielectric base material, a laminated body formed by sequentially laminating a first dielectric base material, a conductive intermediate ground pattern, and a second dielectric base material is used. When viewed from above the dielectric base material, it may be made to approach toward the hole of the dielectric base material while overlapping with either the first transmission line or the second transmission line. If it does in this way, the 1st conduction line-> 2nd by the opposing capacity formed between a conductive middle ground pattern and each conductive member (the 1st, 2nd conductive line, and the 2nd conductive pad). The characteristic impedance is constant in the path from the conductive pad to the second conductive line, and mismatching of the characteristic impedance of the line in the hole is prevented.
[0016]
Further, the hole is tapered so that the second conductive pad side has a wide diameter, and a recess reflecting the tapered shape is formed in the second conductive pad, and an external connection terminal is joined to the recess. May be. If it does in this way, since an external connection terminal is automatically guided toward the bottom part of a crevice by gravity, alignment with an external connection terminal and the 2nd conductive pad is performed easily.
[0017]
The semiconductor device according to the present invention is mounted on the above-described high-frequency circuit board, and the characteristic impedance mismatch in the high-frequency circuit board is improved as described above. Will be improved accordingly.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
(1) First embodiment
FIG. 2 is an enlarged perspective view of the high-frequency circuit board according to the first embodiment of the present invention.
[0020]
In this high-frequency circuit board, a high-frequency signal having a frequency of 1 GHz or more flows. When the frequency is high in this way, it is necessary to design the circuit so that each transmission line has a desired characteristic impedance value. Thus, in this embodiment, a coplanar transmission is performed by forming a gold plating layer of about 30 μm thickness on one surface of a polyimide film (dielectric substrate) 10 of about 50 μm thickness and patterning it. A first conductive ground layer 12 and a first transmission line 11 constituting the line are formed.
[0021]
The first conductive ground layer 12 is formed in a solid shape to reduce the resistance.
[0022]
In addition, a circular first conductive pad 11a having a diameter of about 200 μm is provided at the end of the first transmission line 11, and an opening 12a surrounding the first conductive pad 11a and the first transmission line has a first conductive property. Formed on the ground layer 12.
[0023]
The first transmission line 11 is formed in a linear shape having a width of about 70 μm at a distance of about 50 μm from the first conductive ground layers 12 on both sides in the middle of the first conductive pad 11a. When the line width, the distance between the lines, and the film thickness of each layer have the above values, the characteristic impedance of the coplanar transmission line is about 50Ω.
[0024]
FIG. 3A is an enlarged plan view of this high-frequency circuit board when viewed from the same main surface side as FIG. 2, and FIG. 3B is a view when viewed from the main surface opposite to the above. It is an enlarged plan view.
[0025]
As shown in FIG. 3B, the second transmission line 13 and the solid second conductive ground layer are formed on one surface of the polyimide film 10 by patterning a gold plating layer having a thickness of about 50 μm. 14 are formed. A circular second conductive pad 13a having a diameter of about 400 μm is formed at the end of the second transmission line 13, and an opening 14a surrounding the second conductive pad 13a and the second conductive line 13 is a second conductive ground. Formed in layer 14
The second transmission line 13 is formed in a line shape having a width of about 70 μm and separated from the second conductive ground layers 14 on both sides in the middle of the second conductive pad 13a. A coplanar transmission line is formed together with the layer 14.
[0026]
FIG. 4 is a cross-sectional view taken along the line II of FIG. As shown in FIG. 4, a via hole 10a having a wide diameter on the second conductive pad 13a side is formed in the polyimide film 10, and the opening end on the narrow diameter side is closed by the first conductive pad 11a. . The diameter of the via hole 10a on the narrow diameter side is about 150 μm, and the diameter on the wide diameter side is about 400 μm. The second conductive pad 13a is formed on the inner surface of the via hole 10a and is electrically connected to the first conductive pad 11a via the via hole 10a. As a result, the high-frequency signal passes through the path from the first conductive line 11 to the second conductive line 13 via the second conductive pad 13a (or the reverse path).
[0027]
Reference is again made to FIG. As shown in the figure, when viewed from above the polyimide film 10, the opening 12a of the first conductive ground layer 12 has a diameter larger than the diameter of the second conductive pad 13a, and the second conductive pad 13a is It is formed to fit in it.
[0028]
Accordingly, in the present embodiment, since the overlap portion between the first conductive ground layer 12 and the second conductive pad 13a as in the conventional example does not occur, the stray capacitance caused by the overlap portion can be eliminated. . Therefore, since the characteristic impedance of the line is prevented from being locally reduced due to the stray capacitance, the characteristic impedance of the line through which the high-frequency signal passes does not become mismatched in the vicinity of the via hole 10a, and the transmission loss of the high-frequency signal is lower than before. Can also be reduced.
[0029]
Next, the manufacturing process of the high-frequency circuit board according to the present embodiment will be described with reference to FIGS.
[0030]
First, as shown in FIG. 5A, a polyimide film 10 having a thickness of about 50 μm is prepared. An alumina substrate may be used instead of the polyimide film 10.
[0031]
Next, steps required until a sectional structure shown in FIG. First, a photoresist is applied on one surface of the polyimide film 10, and is exposed and developed to form a resist pattern (not shown) having a wiring-shaped opening. Next, a gold plating layer having a thickness of about 30 μm is formed by electroless plating or electrolytic plating on the polyimide film 10 exposed in the opening of the resist pattern, and then the resist pattern is removed, thereby making the gold plating layer the first conductive layer. The line 11 and the first conductive ground layer 12 are left. A first conductive pad 11 a is formed in the first conductive line 11, and an opening 12 a is formed in the first conductive ground layer 12.
[0032]
Instead of the gold plating layer, the first conductive line 11 and the first conductive ground layer 12 may be configured by a copper plating layer.
[0033]
Next, as shown in FIG. 5C, the polyimide film 10 is irradiated with a laser to evaporate the portion of the polyimide irradiated with the laser, and a via hole 10a having a diameter of about 150 μm is formed under the first conductive pad 11a. Form. Alternatively, a via hole 10a is formed by dry-etching the polyimide film 10 using a resist pattern formed on the main surface of the polyimide film 10 on the side where the first conductive line 11 is not formed and using the resist pattern as an etching mask. It may be formed.
[0034]
When an alumina substrate is used instead of the polyimide film 10, a resist pattern is formed in the same manner as described above, and etching is performed with an HF (hydrofluoric acid) solution while using the resist pattern as an etching mask, or dry etching. Via hole 10a is formed.
[0035]
In any of the above methods, the formed via hole 10a has a tapered shape.
[0036]
Next, steps required until a sectional structure shown in FIG. First, a photoresist is coated on the main surface of the polyimide film 10 on the side where the first conductive line 11 is not formed, and is exposed and developed to form a resist pattern (not shown) having a wiring-shaped opening. Form. Next, a gold plating layer having a thickness of about 30 μm is formed on the polyimide film 10 exposed in the opening of the resist pattern by electroless plating or electrolytic plating, and then the resist pattern is removed, whereby the gold plating layer is second conductive. The line 13 and the second conductive ground layer 14 are left. A second conductive pad 13 a is formed in the second conductive line 13, and an opening 14 a is formed in the second conductive ground layer 14.
[0037]
With the above, the high-frequency circuit board according to the present embodiment is completed.
[0038]
(2) Second embodiment
FIG. 6 is an enlarged perspective view of the high-frequency circuit board according to the second embodiment of the present invention. In the figure, the members described in the first embodiment are denoted by the same reference numerals as in the first embodiment, and the description thereof is omitted below.
[0039]
In the high-frequency circuit board according to the present embodiment, a first polyimide film (first dielectric substrate) 20, a conductive intermediate ground pattern 21, and a second polyimide film (second dielectric substrate) 22 are laminated in this order. Thus, the laminate 23 is formed. The thicknesses of the first and second polyimide films 20 and 22 are both about 50 μm, and the conductive intermediate ground pattern 21 is formed by patterning a gold plating layer having a thickness of about 30 μm.
[0040]
The first transmission line 11 and the first conductive ground layer 12 described above are formed on one main surface of such a laminate 23 as shown in the drawing, thereby constituting a coplanar transmission line.
[0041]
The conductive intermediate ground pattern 21 is also formed in the first via hole 22 a of the second polyimide film 22, and is electrically connected to the first conductive ground layer 12 there. Similarly, the second conductive ground layer 14 is also formed in the second via hole 20 a of the first polyimide film 20, and is electrically connected to the conductive intermediate ground pattern 21 there.
[0042]
FIG. 7A is an enlarged plan view of the high-frequency circuit board when viewed from the same main surface side as FIG. 6, and FIG. 7B is a view when viewed from the main surface opposite to the above. It is an enlarged plan view. As shown in FIG. 7B, the second conductive line 13 and the second conductive ground layer 14 described above are formed on the other main surface of the laminate 23 so as to form a coplanar transmission line. Is done.
[0043]
As shown in FIG. 7A, in this embodiment as well, the second conductive pad 13a is accommodated in the opening 12a. Therefore, the second conductive pad 13a and the first conductive ground layer 12 are overloaded. Since the wrap portion does not occur and the stray capacitance due to the overlap portion can be eliminated, the transmission loss of the high frequency signal can be reduced as compared with the conventional case.
[0044]
FIG. 8 is a cross-sectional view taken along the line II of FIG. As understood from the figure, the stacked body 23 is formed with a third via hole 23a, the second conductive pad 13a is formed on the inner surface of the third via hole 23a, and the third via hole 23a is interposed therebetween. Are electrically connected to the first conductive pads 11a.
[0045]
In the present embodiment, when viewed from above the stacked body 23, a part 21 a of the conductive intermediate ground pattern 21 is directed to the third via hole 23 a while overlapping the first and second conductive lines 11 and 13. To approach. The part 21a preferably protrudes into the opening 12a and approaches the third via hole 23a when viewed from above the stacked body 23. Further, the distance d between the part 21a and the third via hole 23a. ₀ D ₁ (Distance between edge of first conductive pad 11a and via hole 23a) + d ₂ The distance is preferably equal to or less than (distance between the first conductive pad 11a and the opening 12a). In this embodiment, d ₁ Is about 25 μm and d ₂ Is about 70 μm, so d ₀ Is preferably about 95 μm or less. d ₀ The value of 95 μm or less depends on what value the characteristic impedance in the third via hole 23a described later is designed.
[0046]
According to the above structure, the counter capacitance C as shown in the figure. ₁ ~ C _Four Is formed, and the capacitance of the lines near the third via hole 23a (first and second conductive lines 11, 13) and the internal lines (second conductive pads 13a) increase, so that the characteristic impedance of the line decreases. It becomes like this. As a result, the characteristic impedance can be kept constant in the path of the first conductive line 11 → the second conductive pad 13a → the second conductive line 13, thereby preventing the mismatch of the characteristic impedance in the third via hole 23a. Thus, reduction in signal transmission loss can be prevented.
[0047]
In addition, as shown in FIG. 9, it is also conceivable that the conductive intermediate ground pattern 21 is approached toward the via hole 23a so as not to overlap with the first and second conductive lines 11 and 13. However, in this case, the opposing capacitance C between the conductive intermediate ground pattern 21 and the first conductive line 11 (or the second conductive line 13). ₁ (C _Four ) Is not obtained, the above advantages cannot be obtained, which is not preferable. Furthermore, this structure is not preferable because the overlap portion between the second conductive pad 13a and the conductive intermediate ground pattern 21 becomes a mere stray capacitance.
[0048]
Next, the manufacturing process of the high-frequency circuit board according to the present embodiment will be described with reference to FIGS. 10 (a) to 10 (d) and FIGS. 11 (a) to 11 (b).
[0049]
First, steps required until a structure shown in FIG. First, a resist pattern (not shown) having a wiring-shaped opening is formed on a second polyimide film 22 having a thickness of about 50 μm, and a gold plating layer is electrolessly formed on the surface of the second polyimide film 22 exposed from the opening. It is formed to a thickness of about 30 μm by plating or electrolytic plating. Thereafter, the resist pattern is removed, and the remaining gold plating layer is used as the first conductive line 11 and the first conductive ground layer 12. A first conductive pad 11 a is formed in the first conductive line 11, and an opening 12 a is formed in the first conductive ground layer 12.
[0050]
Next, as shown in FIG. 10B, the main surface of the second polyimide film 22 on the side where the first conductive ground layer 12 is not formed is irradiated with a laser to evaporate the polyimide at the irradiated portion. Thus, the first via hole 22a having a depth reaching the first conductive ground layer 12 is formed.
[0051]
In order to form the first via hole 22a, for example, a resist pattern (not shown) is formed on the main surface of the second polyimide film 22, and the second polyimide film 22 is dry-etched using the resist pattern as an etching mask. May be.
[0052]
Next, steps required until a structure shown in FIG. First, a resist pattern (not shown) having an opening in the form of a wiring pattern is formed on the second polyimide film 22 on the side where the first conductive ground layer 12 is not formed. Then, a gold plating layer is formed on the surface of the second polyimide film 22 exposed from the opening of the resist pattern and the inner surface of the first via hole 22a to a thickness of about 30 μm by electroless plating or electrolytic plating. Next, the resist pattern is removed, and the remaining gold plating layer is used as the conductive intermediate ground pattern 21. As shown in the drawing, the conductive intermediate ground pattern 21 has a part 21a protruding from the other part, but this part is a part that approaches the already-described third via hole 23a. The conductive intermediate ground layer 21 is also formed in the first via hole 22a, and is electrically connected to the first conductive ground layer 12 there.
[0053]
Next, as shown in FIG. 10D, a first polyimide film 20 having a thickness of about 50 μm is bonded onto the second polyimide film 22 and the intermediate ground pattern 21. This joining is performed via an adhesive (not shown).
[0054]
Subsequently, as shown in FIG. 11A, the first polyimide film 20 is irradiated with laser, and the polyimide at the irradiated portion is evaporated to form the second via hole 20a and the third via hole 23a. Among these, the second via hole 20 a has a depth reaching the conductive intermediate ground pattern 21. On the other hand, the third via hole 23a is formed to a depth that penetrates through the second polyimide fill 22 and reaches the first conductive pad 11a.
[0055]
Instead of using a laser as described above, a resist pattern (not shown) is formed on the first polyimide film 20, and the second via hole 20a and the third via hole 23a are formed by dry etching using the resist pattern as an etching mask. And may be formed.
[0056]
Next, steps required until a structure shown in FIG. First, a resist pattern (not shown) having a wiring pattern shape opening is formed on the first polyimide film 20. A gold plating layer having a thickness of about 30 μm is formed on the surface of the first polyimide film 20 exposed from the opening of the resist pattern and on the inner surfaces of the second and third via holes 20a and 23a by electroless plating or electrolytic plating. To form. Thereafter, the resist pattern is removed, and the remaining gold plating layer is used as the second conductive ground layer 14 and the second conductive line 13. The second conductive ground layer 14 is formed with an opening 14 a and also in the second via hole 20 a, where it is electrically connected to the conductive intermediate ground layer 21. Further, a second conductive pad 13a is formed on the second conductive line 13, and the second conductive pad 13a is also formed in the third via hole 23a, where it is electrically connected to the first conductive pad 11a. Is done.
[0057]
Thus, the high frequency circuit board according to the present embodiment is completed.
[0058]
(3) Third embodiment
12 (a) to 12 (b) are cross-sectional views illustrating the manufacturing process of the high-frequency circuit board according to the third embodiment of the present invention. 12A and 12B, the members already described above are denoted by the same reference numerals as those described above, and the description thereof is omitted below.
[0059]
In this embodiment, as shown in FIGS. 12A to 12B, solder bumps 20 are joined as external connection terminals to the high-frequency circuit board created in the first embodiment. Normally, the solder bump 20 is provided with a pad for bonding it to the second conductive line 13, but in the present embodiment it is bonded to the second conductive pad 13a.
[0060]
As shown in FIG. 12A, the second conductive pad 13a has a recess 13b reflecting the tapered shape of the via hole 10a formed on the surface thereof, so that the solder bump 20 is placed on the second conductive pad 13a. The solder bump 20 is automatically guided toward the bottom of the recess 13b by gravity. As a result, as shown in FIG. 12B, the centers of the solder bumps 20 and the second conductive pads 13a can be automatically aligned.
[0061]
By the way, since the solder bump 20 has a property similar to that of an open stub (Open Stub), if the size is too large, it becomes difficult to pass a signal having a high frequency.
[0062]
According to the present embodiment, for example, even a small solder bump 20 having a diameter of about 100 μm is automatically aligned with the second conductive pad 20 as described above, so that the difficulty associated with alignment is overcome. Can do.
[0063]
Even if the high-frequency circuit board created in the second embodiment is used, the same advantages as described above can be obtained.
[0064]
(4) Application example of the present invention
FIG. 13 is a perspective view of a semiconductor device according to an application example of the present invention.
[0065]
Although there are various application examples of the present invention, a case where the present invention is applied as a substrate for mounting a semiconductor element will be described below.
[0066]
The semiconductor device shown in FIG. 13 has the semiconductor element 30 mounted on the above-described high-frequency circuit board, and the electrode terminal (not shown) of the semiconductor element 30 and the first transmission line 11 are electrically connected via the gold post 31. Connected. The high-frequency circuit board used in this example may be any board described in the first to third embodiments. Furthermore, if necessary, an underfill resin (not shown) may be poured between the substrate and the semiconductor element 30 to absorb the difference in thermal shrinkage between the substrate and the semiconductor element 30. By doing so, it is possible to prevent the gold post 31 and the first transmission line 11 from being poorly connected.
[0067]
FIG. 14 is a cross-sectional view in the case where a metal cover 32 made of copper or the like is bonded to the high-frequency circuit board to protect the semiconductor element 30. Instead of the metal cover 32, a technique such as potting or transfer molding may be used to protect the semiconductor element 30 with resin.
[0068]
Further, in this example, as described in the third embodiment, the solder bump 20 and the second conductive pad are joined by joining the solder bump 20 as the external connection terminal to the concave portion 13b of the second conductive pad 13a. As a result, the position of the solder bump 20 can be reduced.
[0069]
Furthermore, in this example, since the gold post 31 that is easier to match impedance than the bonding wire and the high-frequency circuit board of the present invention are used in combination, a semiconductor device with reduced transmission loss and improved performance is provided. be able to.
[0070]
In the above description, the gold post 31 is electrically connected to the first transmission line 11. However, if the gold post is a ground terminal, it may be electrically connected to the first conductive ground layer 12.
[0071]
The features of the present invention are added below.
[0072]
(Supplementary note 1) a dielectric substrate;
Holes formed in the dielectric substrate;
A first transmission line formed on one surface of the dielectric substrate;
A first conductive pad provided on the first transmission line to block the hole;
A conductive ground layer formed on one surface of the dielectric substrate and having an opening surrounding the first transmission line and the first conductive pad;
A second transmission line formed on the other surface of the dielectric substrate;
A second conductive pad provided on the second transmission line and electrically connected to the first conductive pad through the hole;
The high-frequency circuit board, wherein the second conductive pad fits in the opening of the conductive ground layer when viewed from above the dielectric base material.
[0073]
(Additional remark 2) The laminated body formed by laminating | stacking a 1st dielectric base material, an electroconductive intermediate | middle ground pattern, and a 2nd dielectric base material in order,
Holes formed in the laminate;
A first transmission line formed on one surface of the laminate;
A first conductive pad provided on the first transmission line to block the hole;
A conductive ground layer having an opening formed on one surface of the laminate and surrounding the first transmission line and the first conductive pad;
A second transmission line formed on the other surface of the laminate;
A second conductive pad provided on the second transmission line and electrically connected to the first conductive pad through the hole;
When viewed from above the laminated body, a part of the conductive intermediate ground pattern approaches the hole while overlapping with one of the first transmission line and the second transmission line. A featured high-frequency circuit board.
[0074]
(Supplementary Note 3) The supplementary note 2 is characterized in that the part of the conductive intermediate ground pattern protrudes into the opening of the conductive ground layer and approaches the hole when viewed from above the stacked body. A high-frequency circuit board according to 1.
[0075]
(Supplementary note 4) The high frequency circuit board according to supplementary note 2 or supplementary note 3, wherein a part of the conductive intermediate ground pattern approaches the hole at a distance of 95 µm or less.
[0076]
(Supplementary note 5) The high frequency circuit board according to any one of Supplementary notes 2 to 4, wherein the second conductive pad is accommodated in the opening of the ground layer when viewed from above the laminate. .
[0077]
(Additional remark 6) The said hole is the taper shape from which the said 2nd conductive pad side becomes a wide diameter,
The second conductive pad has a recess reflecting the tapered shape,
6. The high frequency circuit board according to any one of appendix 1 to appendix 5, wherein an external connection terminal is joined to the recess of the second conductive pad.
[0078]
(Supplementary note 7) The semiconductor device according to any one of supplementary notes 1 to 6, wherein a signal having a frequency of 1 GHz or more flows through the first transmission line.
[0079]
(Supplementary note 8) A semiconductor element is mounted on the high-frequency circuit board according to any one of supplementary notes 1 to 7, and an electrode of the semiconductor element is provided at least on the first transmission line, the second transmission line, and the ground layer. A semiconductor device which is electrically connected to any one of the above.
[0080]
【The invention's effect】
As described above, according to the present invention, when viewed from above the dielectric substrate, the second conductive pad is placed within the opening of the conductive ground layer, so that the characteristics of the line through which the high-frequency signal passes can be obtained. Impedance can be prevented from being mismatched in the vicinity of the hole of the dielectric base material, and transmission loss of high-frequency signals can be reduced as compared with the prior art.
[0081]
In addition, a laminate in which a first dielectric substrate, a conductive intermediate ground pattern, and a second dielectric substrate are sequentially stacked is used, and the conductive intermediate ground pattern is used as the first transmission line and the second transmission. By making it approach toward the hole of a dielectric base material, making it overlap with either of a track | line, the mismatch of the characteristic impedance in a via hole can be prevented.
[0082]
Further, the external connection terminal is joined to the concave portion so that the hole has a tapered shape with a wide diameter on the second conductive pad side, and a concave portion reflecting the tapered shape is formed in the second conductive pad. Thus, the alignment between the external connection terminal and the second conductive pad can be easily performed.
[0083]
In addition, by mounting a semiconductor element on the above-described high-frequency circuit board to constitute a semiconductor device, the performance of the semiconductor device can be improved.
[Brief description of the drawings]
1A and 1B are enlarged plan views of a conventional high-frequency circuit board, and FIG. 1C is a cross-sectional view thereof.
FIG. 2 is an enlarged perspective view of the high-frequency circuit board according to the first embodiment of the present invention.
FIGS. 3A to 3B are enlarged plan views of the high-frequency circuit board according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view of the high-frequency circuit board according to the first embodiment of the present invention.
FIGS. 5A to 5D are cross-sectional views showing a manufacturing process of the high-frequency circuit board according to the first embodiment of the present invention.
FIG. 6 is an enlarged perspective view of a high-frequency circuit board according to a second embodiment of the present invention.
FIGS. 7A to 7B are enlarged plan views of a high-frequency circuit board according to a second embodiment of the present invention.
FIG. 8 is a cross-sectional view of a high-frequency circuit board according to a second embodiment of the present invention.
FIG. 9 is an enlarged plan view of a high-frequency circuit board according to a comparative example.
FIGS. 10A to 10D are enlarged perspective views (No. 1) showing the manufacturing process of the high-frequency circuit board according to the second embodiment of the present invention. FIGS.
FIGS. 11A to 11B are enlarged perspective views (No. 2) showing the manufacturing process of the high-frequency circuit board according to the second embodiment of the present invention. FIGS.
FIGS. 12A to 12B are cross-sectional views illustrating a manufacturing process of a high-frequency circuit board according to a third embodiment of the present invention.
FIG. 13 is a perspective view of a semiconductor device according to an application example of the invention.
FIG. 14 is a cross-sectional view of a semiconductor device according to an application example of the invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,10 ... Polyimide film, 1a, 10a, 23a ... Via hole, 2, 11 ... 1st conduction line, 2a, 11a ... 1st electroconductive pad, 3, 12 ... 1st Conductive ground layer, 3a, 12a, 14a ... opening, 4, 13 ... second conductive line, 5, 14 ... second conductive ground layer, 13b ... recess, 20 ... solder Bump, 30 ... semiconductor element, 31 ... gold post, 32 ... metal cover.

Claims (5)

A dielectric substrate;
A hole having a tapered shape formed in the dielectric substrate;
A first transmission line formed on one surface of the dielectric substrate;
A first conductive pad provided on the first transmission line to close the hole and having a circular planar shape;
A conductive ground layer formed on one surface of the dielectric substrate and having an opening surrounding the first transmission line and the first conductive pad;
A second transmission line formed on the other surface of the dielectric substrate;
A second conductive pad provided on the second transmission line, electrically connected to the first conductive pad via the hole, and having a circular planar shape and a larger area than the first conductive pad; Have
The high-frequency circuit board, wherein the second conductive pad fits in the opening of the conductive ground layer when viewed from above the dielectric base material. A laminate formed by sequentially laminating a first dielectric substrate, a conductive intermediate ground pattern, and a second dielectric substrate;
A hole having a tapered shape formed in the laminate;
A first transmission line formed on one surface of the laminate;
A first conductive pad provided on the first transmission line to close the hole and having a circular planar shape;
A conductive ground layer having an opening formed on one surface of the laminate and surrounding the first transmission line and the first conductive pad;
A second transmission line formed on the other surface of the laminate;
A second conductive pad provided on the second transmission line and having a circular planar shape electrically connected to the first conductive pad via the hole and having a larger area than the first conductive pad; Have
When viewed from above the laminate, a part of the conductive intermediate ground pattern approaches the hole while overlapping with one of the first transmission line and the second transmission line, and The high-frequency circuit board, wherein the second conductive pad is accommodated in the opening of the ground layer.   The portion of the conductive intermediate ground pattern protrudes into the opening of the conductive ground layer and approaches the hole when viewed from above the stacked body. High frequency circuit board. The hole has a tapered shape with a wide diameter on the second conductive pad side;
The second conductive pad has a recess reflecting the tapered shape,
4. The high-frequency circuit board according to claim 1, wherein an external connection terminal is bonded to the recess of the second conductive pad. 5.   A semiconductor element is mounted on the high-frequency circuit board according to claim 1, and an electrode of the semiconductor element is at least one of the first transmission line, the second transmission line, and the ground layer. A semiconductor device which is electrically connected.

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