JP4459855B2 - Digital protection relay device - Google Patents

Description

  The present invention relates to a digital protection relay device having a function of receiving a time signal based on an IRIG standard (InterRange Instrumentation Group standard) time code format and demodulating it as time data.

  Conventionally, a digital protection relay device samples and digitizes the amount of electricity (voltage value or current value) input from the power system at a predetermined cycle, and compares this digitized amount of electricity with a preset reference value. Determine the presence or absence. When an abnormality caused by a short circuit accident or the like occurs in the middle of the power system and the amount of electricity exceeds the reference value, measures such as shutting off the power system and ensuring safety are performed.

  In such a digital protection relay device, it is necessary to time-stamp so that it can be understood at what time the abnormality has occurred in future accident countermeasures and investigations. For this reason, an internal timer is provided in advance so as to register and hold the time counted by the internal timer when an abnormality is detected.

  Thus, in order to time stamp the time when an abnormality is detected, it is necessary to appropriately set the time measured by the internal timer in advance at the time of initialization of the apparatus. In that case, if the time of the internal timer is manually set from the outside, the set time varies, and accurate time setting cannot be performed. If there are a large number of devices, time setting is performed for each device. It takes a lot of effort to make it necessary.

  Thus, as a countermeasure, for example, it may be possible to make time adjustment easy by using a signal sent from a positioning system such as GPS (Global Positioning System) to reduce labor.

  In this case, when the signal sent from the positioning system by radio waves is directly received by the digital protection relay device, not only the reception antenna is required, but also the microcomputer included in the device receives time information from the received signal. It is necessary to individually provide a time signal generator for generating a time signal capable of reading the digital signal to each digital protection relay device, and the digital protection relay device itself becomes expensive.

  Therefore, a dedicated receiving device that receives a signal transmitted by radio waves from the positioning system and generates a time signal that can be read by the microcomputer included in each digital protection relay device based on the received signal. It is considered that a time signal is distributed from the receiving device to each digital protection relay device via a communication line.

  However, when a time signal generated from such a receiving device is distributed to each digital protection relay device via a communication line, the signal attenuation varies depending on the length of the signal transmission path from the receiving device to each digital protection relay device. When the signal attenuation is large, the time information cannot be extracted sufficiently, and it becomes difficult to set the time of the internal timer.

  For this reason, conventionally, an AGC circuit that performs automatic gain control is used to amplify or attenuate a time signal having an arbitrary peak value to a constant peak value, thereby compensating for signal attenuation and unknown peak value. Is provided so that the time signal can be received (see, for example, Patent Document 1).

  In addition, in the conventional technology, in the digital protection relay device, in order to accurately set the timing for sampling the amount of electricity input from the power system, the sampling timing is surely synchronized with the reference time information. It has been proposed (see, for example, Patent Document 2).

Japanese Patent Laid-Open No. 10-142313 JP 2004-120964 A

  However, when an AGC circuit is used to compensate for the attenuation of a time signal during transmission, the output fluctuates due to variations in element characteristics, aging, etc., because the AGC circuit continuously controls the voltage by an amplifying element. In such a case, it is difficult to demodulate and extract accurate time data. Further, in order to suppress the output fluctuation over a long period of time, it is necessary to select and use a high-cost part, resulting in an increase in cost.

  In the prior art described in Patent Document 2, the time signal generated by the time signal generator is not standardized, and therefore, it is difficult to share it with other digital protection relay devices. That is, in Patent Document 2, since the time signal generator is configured to simultaneously generate time data and an identification code for determining the reference timing in parallel at the same time and transmit them to the digital protection relay device, the standardized time There is a problem that it is difficult to apply to other digital protection relay devices programmed to handle signals. In addition, the technique of Patent Document 2 is a technique for synchronizing the sampling timing of the electric quantity with reference time information, and the microcomputer can reliably read the time signal attenuated in the middle of the signal transmission path. There is no specific suggestion of a technique for demodulating as much as possible.

  It is also possible to perform time adjustment using a standard radio clock signal. However, when using a standard radio clock signal, there are the following problems. That is, the digital protection relay device appropriately determines whether or not an abnormality has occurred in the power system. When the frequency of the power system is set to, for example, 50 Hz, the amount of power every 1.667 ms (electrical angle 30 °). The processing speed is programmed to perform sampling. However, since the transmission period of the standard radio clock signal is 60 seconds, it is much longer than the above processing speed and cannot be handled as it is. Therefore, it is necessary to separately provide a time signal generator for generating a time signal suitable for the processing speed in the apparatus from the received standard radio time signal, and the digital protection relay apparatus itself becomes expensive.

  The present invention has been made to solve the above-described problems, and is not affected by the characteristics and variations of the constituent elements, and without causing an extra cost increase, and the time code format of the IRIG standard. It is an object of the present invention to provide a digital protection relay device capable of reliably demodulating a time signal based on the time data into time data.

In order to achieve the above object, the digital protection relay device of the present invention includes a demodulating unit that demodulates an analog time signal based on the time code format of the IRIG standard as time data,
The demodulating means includes a peak value detecting means for detecting the maximum peak value of the received time signal, a threshold setting means for setting a predetermined threshold based on the maximum peak value detected by the peak value detecting means, and the threshold value It has a level separator means for performing level separation of the time signal based on a threshold set by the setting means, and a rectangular wave shaping means for generating a rectangular wave signal based on the level separated signals at this level separating means ,
The peak value detecting means sequentially includes a peak hold circuit that holds a peak value of a time signal, a first comparator that compares an output of the peak hold circuit with a determination value, and the determination value that the first comparator compares. And a means for determining whether or not the output of the comparator has changed, and determining a determination value at the time of the output change as a maximum peak value, wherein the threshold value setting means includes the maximum wave detected by the peak value detecting means. Based on the high value, a threshold value that can distinguish the mark value and the space value of the time signal is set, and the level separation means compares the input time signal with the threshold value set by the threshold value setting means. The rectangular wave shaping means comprises a second comparator for identifying the mark value and the space value of the time signal, and the rectangular wave shaping means shifts the output of the second comparator by a predetermined time. And Torejisuta, and a OR circuit which takes the logical sum of the outputs of the shift register of said second comparator, and characterized in that.

  According to the present invention, when an analog time signal based on the time code format of the IRIG standard is received, even if the peak value fluctuates due to signal attenuation, it is not affected by the characteristics and variations of the constituent elements, and The time data can be reliably demodulated without incurring an extra cost. As a result, accurate time setting is possible, and the time at the time of abnormality detection can be time stamped with high accuracy.

Embodiment 1 FIG.
Before describing the configuration of the digital protection relay device of the present invention, first, an analog time signal based on the time code format of the IRIG standard will be described with reference to FIG. 1 and FIG.

  The IRIG standard (IRIG Standard 205-87) time code format includes IRIG-A, IRIG-B, IRIG-D, IRIG-E, and so on depending on differences in frame length, bit rate, carrier frequency, etc. Each format is defined. In the first embodiment, in the digital protection relay device, the IRIG-B format is adapted so as to conform to the sampling frequency of the microcomputer that samples the amount of electricity input from the power system. Intended for time signals.

  FIG. 1 is a waveform diagram of a time signal in the IRIG-B format. Here, the time signal is a combination of two types of mark values Emk and space values Esp with different peak values of a sine wave carrier signal. In the time code format of the IRIG standard, only the ratio of the crest value between the mark value Emk and the space value Esp is defined as 3: 1, and the absolute value of the crest value is not defined.

  FIG. 2 shows IRIG-B format time signals corresponding to the numbers “0” and “1” and the marker symbol “P” (FIG. )), And the mutual relationship of the rectangular wave signal (FIG. 5C) when this time signal is digitized.

  As can be seen from FIG. 2, the number “0” indicates that the space value Esp continues for 8 ms after the mark value Emk of the time signal continues for 2 ms, and the number “1” indicates the space value Esp after the mark value Emk of the time signal continues for 5 ms. Is 5 ms, the marker symbol “P” corresponds to the case where the mark value Emk of the time signal continues for 8 ms and then the space value Esp continues for 2 ms. In the time signal of the IRIG-B format, the mark value Emk and the space value Esp are combined and changed in a time series, whereby the date, hour, minute and second encoded in binary coded decimal (BCD). And the like are transmitted.

  As described above, the IRIG standard only specifies that the ratio of the peak value of the mark value Emk to the space value Esp is 3: 1, and there is no definition of the peak value itself. Therefore, if the received analog time signal has any peak value, it can be accurately shaped into the rectangular wave signal shown in FIG. The computer can easily recognize the time.

  Next, the configuration of the digital protection relay device according to Embodiment 1 of the present invention will be described with reference to FIG.

  The digital protection relay device according to the first embodiment includes a demodulator 1 that takes in a time signal based on the IRIG-B format transmitted from a receiver (not shown) that receives time information of the GPS positioning system and demodulates it as time data. And a microcomputer 2 that performs various processes such as a power system protection operation based on time data demodulated and extracted by the demodulating means 1.

  The demodulating means 1 includes a full-wave rectifying circuit 3 that full-wave rectifies the received time signal, a peak value detecting means 4, a threshold setting means 2, a level separating means 5, and a rectangular wave shaping means 6.

  The full-wave rectifier circuit 3 performs full-wave rectification on the received IRIG-B format time signal. For example, the full-wave rectifier circuit 3 is a combination of a pair of light-emitting elements and light-receiving elements connected in reverse, or a diode bridge. It is configured by a circuit or the like.

  The peak value detecting means 4 detects the maximum peak value of the time signal after full-wave rectification, and the peak hold circuit 7 that holds the peak value of the time signal, the output of the peak hold circuit 7 and the judgment value are obtained. The first comparator 8 to be compared and the microcomputer 2 that sequentially changes the determination value to be compared by the first comparator 8. The microcomputer 2 monitors the output change of the first comparator 8 and determines the determination value at the time when the output changes as the maximum peak value.

  The threshold value setting means 2 is constituted by the microcomputer 2 in the first embodiment, and can distinguish the mark value Emk and the space value Esp of the time signal based on the maximum peak value detected by the peak value detection means 4. A predetermined threshold is set as described above.

  The level separation means 5 performs level separation of the time signal based on the threshold set by the microcomputer 2 as the threshold setting means, and compares the time signal after full wave rectification with the threshold to mark the time signal. It comprises a second comparator 9 that distinguishes the value Emk and the space value Esp.

  The rectangular wave shaping means 6 generates a rectangular wave signal based on the signal level-separated by the level separation means 5, and includes a shift register 10 for shifting the output of the second comparator 9 for a predetermined time, and a second comparator The OR circuit 11 takes the logical sum of the output of 9 and the output of the shift register 10.

  The microcomputer 2 is provided with an arithmetic processing unit (not shown) that performs processing such as sampling the amount of electricity input from the power system at a predetermined cycle to determine whether there is an abnormality, and shutting off the power system when an abnormality occurs. An internal timer unit 12 for time stamping the occurrence time at the time of abnormality and a DA converter unit 13 for outputting a necessary voltage signal to the first and second comparators 8 and 9 are incorporated.

  Next, the operation of the digital protection relay device having the above configuration will be described with reference to the signal waveform diagram shown in FIG. 4A to 4E correspond to the signals A to E in FIG. 3, respectively.

  An analog time signal based on the IRIG-B format is generated from the receiver that receives the time information of the GPS positioning system, and this time signal is received by the demodulator 1 via a signal transmission path (not shown).

  The received IRIG-B format time signal (see FIG. 4A) is full-wave rectified by the full-wave rectifier circuit 3 (see FIG. 4B) and then input to the peak hold circuit 7. At the same time, it is input to one input terminal (+) of the second comparator 9.

  Thereby, the peak hold circuit 7 holds the voltage level of the peak value of the time signal after full-wave rectification. The output of the peak hold circuit 7 is applied to one input terminal (+) of the first comparator 8 at the subsequent stage.

  At the time of device initialization, the microcomputer 2 outputs a voltage signal serving as a determination value from the DA converter 13 to the other input terminal (−) of the first comparator 8. In addition, the level of the voltage signal output from the DA converter 13 is sequentially changed stepwise.

  Here, when the voltage level of the DA converter 13 of the microcomputer 2 becomes equal to the voltage level of the peak value held by the peak hold circuit 7, the output of the first comparator 8 changes from “1” to “0”. Switch. Therefore, the output voltage of the DA converter 13 at the time of switching becomes the holding voltage of the peak hold circuit 7. The holding voltage of the peak hold circuit 7 corresponds to the mark value Emk of the received time signal.

  As described above, in the IRIG-B format, since the ratio of the peak value of the mark value Emk to the space value Esp is defined as 3: 1, the microcomputer 2 uses the mark value Emk detected as described above. A voltage corresponding to, for example, 1/2 of the corresponding voltage is set as the threshold Esh (= Emk / 2). Therefore, the mark value Emk and the space value Esp included in the time signal can be identified by the threshold value Esh. The threshold Esh is given from the DA converter 13 to the other input terminal (−) of the second comparator 9.

  Here, if the IRIG-B format time signal is continuously input for at least 10 ms, the mark value Emk can be detected (see FIG. 2). Therefore, the output hold time of the peak hold circuit 7 is set to 10 ms or more. In the meantime, the threshold value Esh can be determined by monitoring the output change of the first comparator 8 by stepwise changing the voltage level, which is the determination value output from the DA converter 13 by the microcomputer 2. The threshold Esh is not necessarily set to Emk / 2 as long as the mark value Emk and the space value Esp included in the time signal can be clearly identified.

  As described above, the time signal that has been full-wave rectified by the full-wave rectifier circuit 3 is input to one input terminal (+) of the second comparator 9, and the other input terminal (−) is as described above. Since the threshold value Esh is set, the second comparator 9 outputs “1” only when the peak value of the mark value Emk is indicated in the time signal of the IRIG-B format as shown in FIG. 4C. Will be.

  In this case, only by identifying the mark value Emk and the space value Esp by the threshold value Esh set in the second comparator 9, the output of the second comparator 9 becomes an intermittent rectangular wave as shown in FIG. . Therefore, as shown in FIG. 4D, the intermittent rectangular wave is shifted by the shift register 10 for a predetermined time (for example, shifted here by 0.067 ms). Then, the OR circuit 11 calculates the logical sum of the output of the second comparator 9 and the output of the shift register 10 and adds the rectangular waves, so that the intermittent portion can be eliminated as shown in FIG. .

  As a result, when a time signal in the IRIG-B format is input to the demodulating unit 1, the rectangular wave shaping unit 6 generates a rectangular wave whose H level continues during the period when the peak value of the mark value Emk is output. A rectangular wave that is generated and continues at the L level is generated during the period when the peak value of the space value Esp is output.

  As shown in FIG. 2, when the period when the rectangular wave signal output from the OR circuit 11 is H level is 2 ms, the time signal indicates “0”, and when the period when the rectangular wave signal is H level is 5 ms. When the time signal indicates “1” and the period during which the rectangular wave signal is at the H level is 8 ms, the time signal indicates “P”.

  In this digital protection relay device, when the amount of electricity input from the power system is sampled and digitized, the software of the microcomputer 2 is 1.667 ms when the electrical angle is 30 °, that is, the frequency of the power system is 50 Hz, for example. It is preset so as to operate every time (see FIG. 4F). Therefore, if the period during which the rectangular wave signal output from the OR circuit 11 is at the H level is 2 ms or longer, the microcomputer 2 can recognize “1” of the time signal without omission. Thereby, the microcomputer 2 can reliably identify whether the H-level pulse width of the rectangular wave signal is 2 ms, 5 ms, or 8 ms.

  Thus, the microcomputer 2 determines whether the H-level pulse width of the rectangular wave signal is 2 ms, 5 ms, or 8 ms, that is, whether the time signal is “0”, “1”, or “P”. Since it can be reliably identified, the time data of the year, month, day, hour, minute and second encoded in binary decimal number (BCD) in the time signal of the IRIG-B format is read, and the current time data is set in the internal timer unit 12 To do.

  In the configuration of the first embodiment, the peak hold circuit 7 and the first comparator 8 are used only for determining the threshold value Esh for discriminating the mark value Emk and the space value Esp in the steady state. There is no need to be. Therefore, it is not necessary to pay much attention to the characteristics and variations of the constituent elements, and it can be configured with inexpensive parts.

  As described above, according to the first embodiment, even if the peak value of an analog time signal based on the time code format of the IRIG standard is attenuated and fluctuated during signal transmission, the characteristics of the constituent elements and The time data can be reliably demodulated without being affected by variations. As a result, accurate time setting is possible, and the time at the time of abnormality detection can be time stamped with high accuracy.

  The peak value detecting means 4, the threshold setting means 2, the level separating means 5, and the rectangular wave shaping means 6 are simple circuit elements such as a peak hold circuit 7, comparators 8 and 9, a shift register 10 and an OR circuit 11. Therefore, the desired function can be realized without incurring an extra cost.

Embodiment 2. FIG.
FIG. 5 is a block diagram showing the configuration of the digital protection relay device according to the second embodiment of the present invention. Components corresponding to those of the first embodiment shown in FIG.

  In the second embodiment, the microcomputer 2 periodically outputs a reset signal to the peak hold circuit 7 so as to periodically reset the peak hold circuit 7. Therefore, the microcomputer 2 corresponds to the reset means in the claims.

  In the first embodiment, the threshold value is determined when the apparatus is initialized. However, in the second embodiment, the reset signal is periodically output from the microcomputer 2 to thereby output the peak hold circuit 7. Reset. In response to this, the peak value detection means 4 can re-detect the maximum peak value of the peak hold circuit 7, and accordingly, the microcomputer 2 constituting the threshold setting means determines the threshold from the re-detected maximum peak value. Can be corrected.

  As a result, when the time of the internal timer unit 12 is periodically corrected, the threshold value is corrected even if the time signal in the IRIG-B format attenuates in the middle of passing through the transmission path and the peak value fluctuates. Thus, the microcomputer 2 can accurately read the time data, set the current time data in the internal timer unit 12, and always perform appropriate time update.

  Since other configurations and operational effects are the same as those in the first embodiment, detailed description thereof is omitted here.

  In the first and second embodiments, the case where the time signal of the IRIG-B format is handled as the time code format of the IRIG standard has been described. However, the present invention is not limited to this, and digital protection is performed. In the relay device, another time code format can be selected and used as appropriate in accordance with the sampling frequency of the microcomputer 2 that samples the amount of electricity input from the power system.

  In the first and second embodiments, the full-wave rectifier circuit 3 is provided. If the intermittent rectangular wave can be eliminated by the shift register 10 and the OR circuit 11, a half-wave rectifier circuit is provided. Can also be used.

It is a wave form diagram which shows an example of the time signal of IRIG-B format. Correlation between IRIG-B format time signals corresponding to the numbers "0" and "1" and the marker symbol "P" indicating the frame length delimiter, and the rectangular wave signal when this time signal is digitized It is explanatory drawing which shows. It is a block diagram of the digital protection relay apparatus in Embodiment 1 of this invention. It is a signal waveform diagram with which it uses for description of the signal processing operation | movement of the digital protection relay apparatus. It is a block diagram of the digital protection relay apparatus in Embodiment 2 of this invention.

Explanation of symbols

1 demodulation means, 2 microcomputer (threshold setting means), 3 full-wave rectifier circuit,
4 peak value detecting means, 5 level separating means, 6 rectangular wave shaping means,
7 peak hold circuit, 8 first comparator, 9 second comparator,
10 shift register, 11 OR circuit, 12 internal timer, 13 DA converter.

Claims (2)

Demodulating means for demodulating an analog time signal based on the time code format of the IRIG standard as time data, the demodulating means detects the maximum peak value of the received time signal, and detects the peak value Threshold setting means for setting a predetermined threshold based on the maximum peak value detected by the means, level separation means for performing level separation of the time signal based on the threshold set by the threshold setting means, and the level separation and a rectangular wave shaping means for generating a rectangular wave signal based on the level separated signals by means,
The peak value detecting means sequentially includes a peak hold circuit that holds a peak value of a time signal, a first comparator that compares an output of the peak hold circuit with a determination value, and the determination value that the first comparator compares. It consists of a means to monitor the output change of the comparator by changing, and determine the judgment value at the time of output change as the maximum peak value,
The threshold value setting means sets a threshold value capable of identifying the mark value and the space value of the time signal based on the maximum peak value detected by the peak value detecting means,
The level separation means comprises a second comparator that compares the input time signal and the threshold value set by the threshold value setting means to identify the mark value and the space value of the time signal,
The rectangular wave shaping means includes a shift register that shifts the output of the second comparator by a predetermined time, and an OR circuit that takes the logical sum of the output of the second comparator and the output of the shift register.
A digital protection relay device characterized by that. Reset means for periodically resetting the peak hold circuit, and in response to the reset operation of the reset means, the peak value detecting means redetects the maximum peak value of the peak hold circuit; 2. The digital protection relay device according to claim 1, wherein the threshold value is corrected based on a maximum peak value re-detected by a peak value detecting means .

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