JP2008211937A - Irig signal decoding circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive and small IRIG signal decoding circuit which can catch a signal change irrespective of a voltage level of an IRIG signal. <P>SOLUTION: The IRIG signal decoding circuit is provided with an external input insulating means 1 receiving only an AC component of the IRIG signal inputted from the outside, a peak holding circuit 2 holding a maximum amplitude value of the IRIG signal received by the external input insulating means 1, a 1/n-fold amplifying circuit 3 amplifying the maximum amplitude value held by the peak holding circuit 2 1/n-times, a comparator 4 comparing an output value of the 1/n-fold amplifying circuit 3 with an amplitude value of each IRIG signal, and an extracting means 5 extracting a marker code and a logic code from the IRIG signal by obtaining a rate of duration of the signal exceeding an output value of the 1/n-fold amplifying circuit 3, output from the comparator 4, and duration of the signal which does not exceed the output value of the 1/n-fold amplifying circuit 3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an IRIG signal decoding circuit for decoding a time code indicated by an IRIG (Inter Range Instrumentation Group) signal.

  The IRIG signal is a frame signal obtained by amplitude-modulating a carrier with a time code, and is used as a reference time signal in various fields such as a communication system, a data processing system, and a telemetry system. Specifically, for example, in Patent Document 1, when a state change occurs in the power system, the time synchronization of the internal clock of the digital protection relay is taken for the purpose of recording the state change information with an accurate generation time. Therefore, an example in which an IRIG signal which is a time reference signal is introduced from the outside is shown.

  The IRIG signal has no specific voltage level or waveform, but the level ratio between the signal portion having a large amplitude and the signal portion having a small amplitude is defined as 3.3: 1, and is continued when the amplitude is large. The logical code “1” “0” and the marker code “P” serving as the reference of the time frame are represented by the ratio of the time and the duration when the amplitude is small, and the marker code “P” is continued twice. Represents the beginning of the time frame.

  Specifically, if the voltage level when the amplitude is large is VH and the voltage level when the amplitude is small is VL, the duration of VH and the continuation of the subsequent VL are based on the time point when VL changes to VH. When the ratio to time is 5: 5, it represents the logical code “1”, when 2: 8, it represents the logical code “0”, and when it is 8: 2, it represents the marker code “P”. Yes.

  There are several types of IRIG signals, but IRIG-B signals having a carrier frequency of 1 kHz and a time frame period of 1 second are relatively frequently used. Here, referring to FIGS. The logic codes “1” and “0” and the marker code “P” defined by the −B signal will be described. 5 to 7 are waveform image diagrams illustrating the logic codes “0” and “1” and the marker code “P”.

  As shown in FIG. 5, the logical code “0” is represented by a ratio of 2 ms for the duration of VH and 8 ms for the duration of VL within the interval of 10 ms from the time when the voltage level changes from VL to VH. . As shown in FIG. 6, the logical code “1” is represented by a ratio of 5 ms for the duration of VH and 5 ms for the duration of VL within a period of 10 ms from the time when the voltage level changes from VL to VH. . As shown in FIG. 7, the marker code “P” is represented at a rate of 8 ms for the duration of VH and 2 ms for the duration of VL within a section of 10 ms from the time when the voltage level changes from VL to VH. .

  In short, one time frame of the IRIG-B signal has a structure in which the first 20 ms is the marker code “P”, and thereafter, the time code consisting of the combination of the logical codes “1” and “0” continues every 10 ms. The top timing of this frame gives a precise time update timing, and time code binary data consisting of a combination of logical codes “1” and “0” continuous every 10 ms gives time data.

  Patent Document 1 described above discloses a configuration example of a circuit that decodes a time code composed of a combination of logical codes “1” and “0” continuous every 10 ms in such an IRIG-B signal and inputs the decoded time code to a digital protection relay. Has been. In this method, VH and VL levels of an input IRIG-B signal are determined, and binary data of logical codes “1” and “0” are discriminated and extracted from the durations of VH and VL. Hereinafter, the outline will be described with reference to FIG. FIG. 8 is a block diagram showing a configuration example of a conventional IRIG signal decoding circuit.

  As shown in FIG. 8, the conventional IRIG signal decoding circuit includes an external input insulating means 21, a full-wave rectifying means 22, a smoothing means 23, an A / D converter 24, a memory 25, and a CPU 26. Composed.

  The operation will be briefly described. The external input insulating means 21 cuts the direct current component of the IRIG-B signal input from the external device and supplies only the alternating current component to the full-wave rectifying means 22. The full-wave rectifying means 22 applies full-wave rectification to the alternating current component of the IRIG-B signal input from the external input insulating means 21 and provides the smoothing means 23 with a rectified waveform signal in which all components are aligned on the positive electrode side. The smoothing means 23 smoothes the rectified waveform signal input from the full-wave rectifying means 22 and provides the A / D converter 24 with a stepped smoothing signal with little pulsation component. The A / D converter 24 samples the smoothed signal input from the smoothing means 23 at a predetermined timing, and stores each sample value in the memory 25. The number of sample values at the VH level and the number of sample values at the VL level correspond to the respective durations described above.

  Therefore, each time the sample value is read from the memory 25, the CPU 26 makes a determination between a high level (hereinafter referred to as “H level”) and a low level (hereinafter referred to as “L level”) by comparing with a threshold value. Based on the time when the level changes from the L level to the H level, the number of H levels and the number of L levels are respectively obtained to calculate the ratio of the duration, and the marker code “P” and the logical code “1” are calculated based on the calculation result. "0" is identified, and the time update timing and the set time data are obtained.

JP 2001-45646 A

  However, as described above, a specific voltage level and waveform of the IRIG signal are defined only by a level ratio of 3.3: 1 between a signal portion having a large amplitude and a signal portion having a small amplitude. In the conventional IRIBG signal decoding circuit having an A / D converter, it is necessary to select an A / D converter having a dynamic range adapted to the voltage level of the IRIG signal to be handled, and lacks versatility. Even if the dynamic range of the A / D converter is increased to some extent so that an IRIG signal having an arbitrary voltage level can be flexibly dealt with, the voltage level of the IRIG signal depends on the generation source (external device). Therefore, it is difficult to select an appropriate dynamic range.

  Further, in the conventional IRIBG signal decoding circuit described above, it is difficult to reduce the cost and reduce the size because a high-cost component with a large mounting area such as a memory and a CPU is used in addition to the A / D converter.

  The present invention has been made in view of the above, and an object of the present invention is to obtain an IRIG signal decoding circuit that can detect a signal change regardless of the voltage level of the IRIG signal, and can be reduced in cost and size. And

  In order to achieve the above-described object, the present invention provides an external input insulating means for taking in only an AC component of an IRIG signal inputted from the outside, and a peak hold for holding the maximum amplitude value of the IRIG signal taken in by the external input insulating means. A circuit, a 1 / n-times amplifier that amplifies the maximum amplitude value held by the peak hold circuit to 1 / n times, an output value of the 1 / n-times amplifier, and an amplitude value of each signal of the IRIG signal A comparator that performs a size comparison, a duration of a signal that exceeds the output value of the 1 / n-times amplifier, and a duration of a signal that does not exceed the output value of the 1 / n-times amplifier thereafter. And extracting means for extracting a marker code and a logical code from the IRIG signal.

  According to the present invention, the maximum amplitude value of the IRIG signal is amplified 1 / n times to generate a threshold value that is smaller than the maximum amplitude value of the IRIG signal and larger than the minimum amplitude value. It is possible to capture signal changes regardless of the level. In addition, since high-cost parts requiring a large mounting area are not used as in the conventional example, the cost and size can be reduced.

  According to the present invention, there is an effect that versatility that is not related to the voltage level of the IRIG signal can be realized, and that cost and size can be reduced.

  Exemplary embodiments of an IRIG signal decoding circuit according to the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG.
1 is a block diagram showing a configuration of an IRIG signal decoding circuit according to a first embodiment of the present invention. As shown in FIG. 1, the IRIBG signal decoding circuit according to the first embodiment includes an external input insulating means 1, a peak hold circuit 2, a 1 / n-times amplification circuit 3, a comparator 4, and an extracting means 5. I have.

  Next, the operation of the IRIBG signal decoding circuit according to the first embodiment configured as described above will be described with reference to FIGS. FIG. 2 is a diagram showing output waveforms of each part of the IRIG signal decoding circuit shown in FIG.

  The IRIG signal input from the external device to the external input insulating means 1 is assumed to be the IRIG-B signal shown in FIGS. The external input insulation means 1 is electrically insulated from external equipment and takes in the signal W1 of only the AC component of the IRIG-B signal (FIG. 2 (W1)). The IRIG signal W1 is input to the peak hold circuit 2 and the comparator 4.

  The peak hold circuit 2 holds the maximum value among the amplitude values of each signal in the IRIG signal W1. As shown in FIGS. 5 to 7, the IRIG-B signal has a section in which a signal having a large amplitude continues at an equal amplitude and a section in which a signal having a small amplitude continues at an equal amplitude within a period of 10 ms. Therefore, the signal W2 output from the peak hold circuit 2 shows an amplitude value of a signal having a small amplitude immediately before the start of the 10 ms period of the IRIG-B signal that is input first. This is a waveform that shows the amplitude value in a large signal interval and holds it in the signal interval with a smaller amplitude thereafter (FIG. 2 (W2)). Then, in each subsequent 10 ms period, a waveform of a certain level that maintains the amplitude value held in the first 10 ms period is shown.

  In the 1 / n multiplication circuit 3 that amplifies the peak hold signal W2 by 1 / n times, the level ratio between when the amplitude of the IRIG signal is large and when the amplitude is small is defined as 3.3: 1. , N is configured as 1 <n <3. Therefore, in the 1 / n-times amplifying circuit 3, a signal W3 having a waveform of a predetermined constant level that is smaller than a signal having a large amplitude and larger than a signal having a small amplitude is obtained within a period of 10 ms (FIG. 2 (W3)). ).

  The comparator 4 uses the output signal W3 of the 1 / n-times amplification circuit 3 as the threshold 6 in each 10 ms period of the IRIG-B signal W1 from the external input insulating means 1, and outputs the output within the period exceeding the threshold 6 to the H level. To. Therefore, as shown in FIG. 2 (W4), in the comparison result signal W4, in each 10 ms period, in a continuous section of a signal having a large amplitude, an H level predetermined width pulse signal continues for each signal, and the amplitude of the subsequent signal In a continuous section of a small signal, a waveform with continuous L level is shown.

  The extraction means 5 receives the comparison result signal W4, obtains the ratio between the time interval in which the H level predetermined width pulse signal continues and the time interval in which the L level continues thereafter, and the marker code with the ratio of 8: 2. For every 10 ms section from the beginning of a time frame in which “P” and the marker code “P” are continuous twice, a logical code “1” with a ratio of 5: 5 and a logical code “0” with a ratio of 2: 8 Are extracted and output.

  The IRIG signal decoding circuit shown in FIG. 1 can be realized by an FPGA, an ASIC, or the like, but can also be configured as shown in FIG. 3, for example. FIG. 3 is a circuit diagram showing a specific example of the IRIG signal decoding circuit shown in FIG. However, in FIG. 3, up to the comparator 4 is shown.

  In FIG. 3, the external input insulating means 1 is composed of a transformer, and the peak hold circuit 2 is composed of a rectifier circuit 2a using an operational amplifier, a peak hold capacitor 2b, and a voltage buffer 2c using an operational amplifier. Is configured as an inverting amplifier circuit using an operational amplifier. In the comparator 4, the output of the 1 / n-times amplifier circuit 3 is applied to the negative phase input terminal (−), and the output of the external input insulating means 1 is the positive phase input terminal (+). It is comprised with the operational amplifier applied to.

  According to the configuration shown in FIG. 3, since the operational amplifiers of the respective circuit units can be integrated in one package, it is possible to reduce the mounting area.

  As described above, according to the first embodiment, the maximum amplitude of the IRIG signal introduced from the outside is held, and the threshold is generated by amplifying it by 1 / n times, and the threshold and the IRIG introduced from the outside are generated. Compared with the signal, the duration of the signal that exceeds the threshold and the duration of the signal that does not exceed the threshold can be specified, so the signal change can be detected regardless of the voltage level of the IRIG signal introduced from the outside. The marker code “P” and the logic codes “1” and “0” can be extracted (decoded). Therefore, an IRIG signal decoding circuit having versatility can be obtained.

  Also, unlike the conventional example (FIG. 8), high cost and large mounting parts (A / D converter, memory, CPU) are not required, so that an IRIG signal decoding circuit that can be reduced in cost and size can be provided. can get.

Embodiment 2. FIG.
FIG. 4 is a block diagram showing a configuration of an IRIG signal decoding circuit according to the second embodiment of the present invention. In FIG. 4, the same or similar components as those shown in FIG. 1 (Embodiment 1) are denoted by the same reference numerals. Here, the description will be focused on the portion related to the second embodiment.

  In the second embodiment, a configuration example for further miniaturization is shown. That is, in FIG. 1 (Embodiment 1), the voltage level of the IRIG signal is substantially indefinite because there is no clear definition, so it is almost impossible to use a photocoupler for the external input insulating means 1. A transformer is used as shown in FIG.

  As described in the first embodiment, in the present invention, the threshold value obtained by amplifying the maximum amplitude value of the IRIG signal by 1 / n times is compared with the IRIG signal, so that the output level of the comparator 4 is the comparator 4. It will be determined within the allowable range.

  Therefore, as shown in FIG. 4, the IRIG signal decoding circuit according to the second embodiment eliminates the external input insulating means 1 which is a large component from the configuration shown in FIG. And an extracting means 5 are provided with an electrical insulating means 10 composed of a photocoupler.

  According to this configuration, the electrical insulating means 10 can convert the output voltage level of the comparator 4 to an arbitrary level and transmit it to the extracting means 5. Thus, the extraction means 5 is configured as a digital circuit that operates at a low voltage (for example, 3.3 V) or an analog circuit that operates at a high voltage (for example, 12 V / 15 V) regardless of the output voltage level of the comparator 4. This increases the degree of design freedom.

  As described above, according to the second embodiment, in the configuration shown in the first embodiment, the external input insulating means that is a large component is deleted, and an electrical insulating means is provided between the comparator and the extracting means. Therefore, the IRIG signal decoding circuit having versatility can be further reduced in cost and size. In addition, the degree of freedom in design can be increased.

  As described above, the IRIBG signal decoding circuit according to the present invention has versatility that is not related to the voltage level of the IRIG signal, and is useful for cost reduction and size reduction. Is suitable for flexibly responding to application scenes.

It is a block diagram which shows the structure of the IRIG signal decoding circuit by Embodiment 1 of this invention. It is a figure which shows the output waveform of each part of the IRIG signal decoding circuit shown in FIG. FIG. 2 is a circuit diagram showing a specific example of an IRIG signal decoding circuit shown in FIG. 1. It is a block diagram which shows the structure of the IRIG signal decoding circuit by Embodiment 2 of this invention. It is a waveform image diagram explaining the logic code “0” of the IRIG-B signal. It is a waveform image diagram explaining the logic code “1” of the IRIG-B signal. It is a wave form image figure explaining marker code "P" of an IRIG-B signal. It is a block diagram which shows the structural example of the conventional IRIG signal decoding circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 External input insulation means 2 Peak hold circuit 2a Rectifier circuit 2b Peak hold capacitor 2c Voltage buffer 3 1 / n times amplification circuit 4 Comparator 5 Extraction means 6 Threshold 10 Electrical insulation means

Claims (2)

External input insulation means for capturing only the AC component of the IRIG signal input from the outside;
A peak hold circuit for holding the maximum amplitude value of the IRIG signal captured by the external input insulating means;
A 1 / n-times amplifier that amplifies the maximum amplitude value held by the peak hold circuit to 1 / n times;
A comparator for comparing the magnitude of the output value of the 1 / n amplifier and the amplitude value of each signal of the IRIG signal;
By determining the ratio between the duration of the signal that exceeds the output value of the 1 / n-times amplifier output from the comparator and the duration of the signal that does not exceed the output value of the subsequent 1 / n-times amplifier, An IRIG signal decoding circuit comprising: extraction means for extracting a marker code and a logic code from the IRIG signal. A peak hold circuit that holds the maximum amplitude value of the IRIG signal input from the outside;
A 1 / n-times amplifier that amplifies the maximum amplitude value held by the peak hold circuit to 1 / n times;
A comparator for comparing the magnitude of the output value of the 1 / n amplifier and the amplitude value of each signal of the IRIG signal;
Electrical insulation means for taking electrical insulation and transmitting the output of the comparator to a subsequent stage;
Determining a ratio between a duration of a signal that exceeds the output value of the 1 / n-times amplifier and a duration of a signal that does not exceed the output value of the 1 / n-times amplifier that is output by the electrical insulation means; An IRIG signal decoding circuit comprising: extraction means for extracting a marker code and a logic code from the IRIG signal.

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