CN106341212B - It is a kind of to realize polymorphic type time signal from the device and method for recognizing and detecting - Google Patents
It is a kind of to realize polymorphic type time signal from the device and method for recognizing and detecting Download PDFInfo
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- CN106341212B CN106341212B CN201610735252.8A CN201610735252A CN106341212B CN 106341212 B CN106341212 B CN 106341212B CN 201610735252 A CN201610735252 A CN 201610735252A CN 106341212 B CN106341212 B CN 106341212B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
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- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
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Abstract
It is a kind of to realize polymorphic type time signal from the device and method for recognizing and detecting, including sequentially connected level shifting circuit, signal identification unit, signal demodulation unit, pulse quadruplex and temporal information comparing unit and framing output unit, signal identification unit includes sequentially connected edge sampling unit, counts accumulator element, count comparator unit and serial ports receiving module；Count comparator unit duration and failing edge duration between according to the high level lasting time of measured signal, the low level duration, rising edge, judge the type of measured signal；Serial ports receiving module carries out data to measured signal and continuously receives, and whether is made of the baud rate for determining measured signal fixed character according to received data character.The present invention can recognize measurement multichannel input signal simultaneously, and each drive test examination is mutually indepedent, is independent of each other.
Description
Technical field
The present invention relates to the technical field of time synchronization, in particular to a kind of realization polymorphic type time signal is from identification and examines
The device and method of survey.
Background technique
With the development of scientific and technological level and the raising of the degree of automation, clock synchronization system is in electric power, the neck such as communication
Domain plays vital effect, is power grid and the basis that communication network operates normally.And clock synchronization system operate normally and
Daily maintenance be unable to do without frequency time signal detection device.The common time signal of clock synchronization system mainly has pulse per second (PPS), divides
Pulse, IRIG-B code, DCF77 code and serial time message etc..
A. as shown in Figure 1, pulse per second (PPS) 1PPS(1 pulse per second) i.e. time interval is 1 second pulse signal；
Sectors rushes 1PPM(1pulse per minute) i.e. time interval is 1 minute pulse signal；When pulse 1PPH(1pulse
Per hour) i.e. time interval is 1 hour pulse signal.
B.IRIG (Inter Range Instrumentation Group) is the abbreviation of U.S. target range instrument group, IRIG
Code is a kind of time standard that the U.S. target range commandant committee formulates.IRIG-B code have carry contain much information, high-resolution,
Nuclear interface standardizing and international feature are suitable for remote information transmission, have DC mode and two kinds of AC mode
Transmission mode.As shown in Fig. 2, IRIG-B code is the time string code of one frame per second, each code element width is 10ms, a cycle
It is pulsewidth coding including 100 symbols." punctual " reference point of symbol is its pulse front edge, and the reference mark of time frame is by one
A position distinguishing mark and adjacent reference symbols sn composition, width 8ms；Every 10 symbols have a position identification mark
Will: P1, P2, P3 ..., P9, P0, they are 8ms width；PR is frame reference point；One time format frame is from frame with reference to mark
Will starts, therefore continuous two 8ms broad pulses show the beginning of second.
C. DCF77 code is located in the standard pair that the frequency of the longwave transmissions platform transmitting of Frankfurt, Germany is 77.5kHz
When signal, include the complete absolute time information such as year, month, day, hour, min, week.As shown in figure 3, DCF77 code is a kind of length
Wave time signal: its carrier frequency is 77.5kHz, is transmitted per minute by 59 (0 to 58) complete time-division date etc.
Temporal information.Other than the 59th second, starting per second, carrier amplitude is reduced to 25% to continue 0.1 second or 0.2 second.DCFF77 waveform
Failing edge indicates the beginning of second, with pulse per second (PPS) Phase synchronization.Minute mark is the previous second signal lacked.It is passed in second gap
Defeated temporal information low level, which continues 100ms, indicates binary system ' 0 ', and low level, which continues 200ms, indicates binary system ' 1 '.Coding rule
It is shown in Table 1, check bit P1, P2, P3 are extended to 3 main paragraph (7 expression minutes, 6 expression hours, 22 tables of timing code
Show the date).
| Position | Code | Explanation | Content |
| 0 | Minute mark will | Minute mark, normal 0 | |
| 1~14 | Retain | Civilian alarm | |
| 15 | R | Antenna position | 0b is normal, and 1b indicates to use emergency antenna |
| 16 | A1 | Daylight-saving time advance notice | Daylight-saving time advance notice notifies that 1 changes for one hour in advance |
| 17 | Z1 | Daylight-saving time 1 | It the use of the daylight-saving time is 1 |
| 18 | Z2 | Daylight-saving time 2 | It is 1 without using the daylight-saving time |
| 19 | A2 | Leap second advance notice | Leap second advance notice notifies, 1 leap second for one hour in advance |
| 20 | S | Start bit | Timing code start bit, normal 1 |
| 21~27 | M | Minute position | Minute (0 ~ 59) |
| 28 | P1 | Check bit 1 | To 21 ~ 28 even parity checks |
| 29~34 | H | Hour position | Hour (0 ~ 23) |
| 35 | P2 | Check bit 2 | To 29 ~ 35 even parity checks |
| 36~41 | DM | Day | The number of days (0 ~ 31) at place month |
| 42~44 | DW | Day | The number of days (1 ~ 7) in place week |
| 45~49 | MN | Month | Months (01 ~ 12) |
| 50~57 | Y | Year | Year (00 ~ 99) in century |
| 58 | P3 | Check bit 3 | To 36 ~ 57 even parity checks |
| 59 | Minute mark will | Minute mark, normal 0 |
1 DCF77 code coding key of table
D. serial time message is the serial data stream comprising temporal information started in second on-time point, and common baud rate is
1200~19200bps.Serial time message meets asynchronous serial communication protocol, and data are transmitted as unit of character, " to rise
Beginning position " start, step-by-step transmission, " stop position " terminate.Start bit is low level (logic ' 0 '), and stop position and free segment are all high
The transmission of level (logic ' 1 '), i.e. data is started in the failing edge of signal.5 ~ 8 times of transmitting terminals are used when serial ports receives
Baud rate receive serial message when, started according to asynchronous serial communication protocol failing edge flag transmission, the character data of transmission
Position first is logic ' 1 ', then the character that receiving end receives is respectively 0xf0,0xe0,0xc0, x80；The character data position of transmission
First is logic ' 0 ', then what receiving end received is that character is 0x00, according to this feature, when serial ports receiving end is continuously received
The data arrived by 0xf0,0xe0,0xc0, x80 wherein one group of character and 0x00 are formed when, that is, can determine whether transmitting terminal be baud rate
The 1/n(n of receiving end baud rate is arbitrary integer in 5 ~ 8), realize the automatic identification to serial ports message and baud rate.Such as Fig. 4, figure
Shown in 5, when serial ports, which is received, receives serial message using the baud rate of 8 times of transmitting terminals, according under asynchronous serial communication protocol
Drop starts along flag transmission, and the character data position first of transmission is logic ' 1 ', then the character that receiving end receives is 0x80；It passes
Defeated character data position first is logic ' 0 ', then the character that receiving end receives is 0x00.With should baud rate be x it is serial
When the character that data reception module continuously receives is made of 0xf0 and 0x00,0xe0 and 0x00,0xc0 and 0x00 respectively, then
Measured signal is the serial message that baud rate is x/5, x/6, x/7.According to this feature, may be implemented to serial ports message and baud
The automatic identification of rate.
Currently used time signal detection device, which can only be realized, detects the signal of specified type.And it answers at the scene
In, the not clear beacon signal type of some time service device output signals needs first to fill time service before using or detecting
The time signal set carries out type identification.
Summary of the invention
In view of this, realizing polymorphic type time signal from the dress for recognizing and detecting the object of the present invention is to provide a kind of
It sets and method, knowledge signal type is debated in easy rapidly detection, while being provided a great convenience for laboratory worker.
The object of the present invention is achieved in the following manner:
A kind of device for realizing polymorphic type time signal and recognizing and detecting certainly, including sequentially connected level shifting circuit,
Signal identification unit, signal demodulation unit, pulse quadruplex and temporal information comparing unit and framing output unit, signal identification list
Member includes sequentially connected edge sampling unit, counts accumulator element, count comparator unit and serial ports receiving module；
Level shifting circuit converts the level of input measured signal, obtains the measured signal of unified electric type；
Edge sampling unit carries out edge sampling to measured signal；
The rising edge that accumulator element is counted in measured signal triggers the low level duration accumulator and rising edge simultaneously
The duration accumulator between triggers measured signal high level lasting time accumulator under in the failing edge of measured signal simultaneously
Drop is along the duration accumulator between；
Count comparator unit is according to the high level lasting time of measured signal, the low level duration, rising edge between
Duration and the failing edge duration between, judge the type of measured signal；
Serial ports receiving module carries out data to measured signal and continuously receives, and detects the received number of each serial received module institute
According to whether being made of any one in 0x80 and 0x00,0xc0 and 0x00,0xe0 and 0x00 or 0xf0 and 0x00；If baud rate
The data received for the serial received module of x are 0x80 and 0x00,0xc0 and 0x00,0xe0 and 0x00 or 0xf0 and 0x00
In any one, then the baud rate of measured signal be x/8, x/7, x/6 or x/5 in corresponding one；
Signal demodulation process unit carries out demodulation dissection process according to measured signal type, to measured signal, extracts or again
Build on-time point id signal, extracting time information；According to the frame structure of timing code, reference symbols sn position is determined, after demodulation
Data are arranged to obtain temporal information, and compensate reconstruction to on-time point id signal；
Pulse quadruplex and temporal information comparing unit to the on-time point id signal of reference time signal and measured signal into
The processing of row phase demodulation, and the measured signal temporal information obtained after demodulation is compared with reference time information；
Framing output unit will measure and comparison result carries out framing, be exported test result to host computer by serial ports.
Preferably, serial ports receiving module carries out data company in 9600 ~ 153600bps of baud rate scope simultaneously to measured signal
Continued access is received.
Preferably, when the comparison information of pulse quadruplex and temporal information comparing unit includes, minute, second, leap second TOD information.
A method of realizing that polymorphic type time signal from recognizing and detecting, includes the following steps:
1) it is converted by level of the level shifting circuit to input measured signal, obtains the tested of unified electric type
Signal；
2) edge sampling is carried out to the measured signal after switching levels, starting accumulator counts signal along, obtains
To measured signal high level lasting time, the low level duration, rising edge duration and failing edge between continue between
Time；
3) according to the high level lasting time of measured signal, the low level duration, rising edge along between the duration and
Failing edge duration between, judge the type of measured signal；
Specifically comprise the following steps:
A. measured signal high level lasting time is detected, if high level lasting time is equal to 8ms, detects next high electricity
The flat duration, if next high level lasting time is also equal to 8ms, measured signal is IRIG-B code；
B. detection measured signal rising edge duration between, if measured signal rising edge duration between is 1 second,
Then measured signal is 1PPS pulse per second (PPS)；If measured signal rising edge duration between is 1 minute, measured signal is 1PPM points
Pulse；
C. measured signal the low level duration is detected, if monitoring the low level of lasting 1s, the starting second, which counts, adds up,
When second counting accumulator is equal to 20, starting high level lasting time detection, if high level durations are 800ms, tested letter
Number be DCF77 code；
D. failing edge detection is carried out to measured signal, it is continuous to carry out data to measured signal by multiple serial received modules
It receives；Detect each serial received module received data whether by 0x80 and 0x00,0xc0 and 0x00,0xe0 and 0x00 or
Any one composition in 0xf0 and 0x00；If the data that receive of serial received module that baud rate is x be 0x80 and
Any one in 0x00,0xc0 and 0x00,0xe0 and 0x00 or 0xf0 and 0x00, then the baud rate of measured signal is x/8, x/
7, corresponding one in x/6 or x/5；
4) according to signal type, demodulation dissection process is carried out to measured signal, extracts or rebuilds on-time point id signal, mention
Take temporal information；According to the frame structure of timing code, reference symbols sn position is determined, the data after demodulation are arranged to obtain the time
Information, and reconstruction is compensated to on-time point id signal；
5) tracking a reference source is received, reference time signal and temporal information are obtained；It counts by sampling and between to benchmark
Time signal and the on-time point id signal of measured signal carry out phase demodulation；Simultaneously to a reference source temporal information and measured signal time
Processing is compared in information；
6) it will measure and comparison result carries out framing, be exported test result to host computer by serial ports.
Preferably, in step 1, incoming level RS485, RS232 or TTL, output level CMOS.
Preferably, in step 2, by receiving Beidou or GPS satellite time or taming local clock, when generating high-precision
Mark.
Preferably, in step 3, between being counted the edge of signal and pulsewidth counts lasting record, if counted between the edge of signal and
Pulsewidth counting continuously meets corresponding signal feature, then judges the signal for legal signal and provide differentiation result；If the edge of signal
Between count and pulsewidth counting occurs not meeting corresponding signal feature, then empty to counting latch, and judge that the signal is illegal,
Restart counting to latch, restarts to judge.
Preferably, in step d, the baud rate scope of multiple serial received modules is 9600 ~ 153600bps.
Compared with the existing technology, sampling clock built in the present invention carries out edge sampling, summary counter pair to measured signal
Signal edge interval after sampling is counted, by comparing and judging whether the edge gap periods of measured signal continuously meet
The feature of nominal time signal, determines the type of measured signal, to realize pulse per second (PPS), sectors punching, IRIG-B code, DCF77 code
With the automatic identification of the time signals such as serial time message.And parsing and accurate detection are carried out according to its type to time signal,
The result is intuitive, without conversion.The present invention can recognize measurement multichannel input signal simultaneously, and the examination of each drive test is not mutually indepedent, mutually not
It influences.
Detailed description of the invention
Fig. 1 is 1PPS signal waveform schematic diagram.
Fig. 2 is IRIG-B code frame structure schematic diagram.
Fig. 3 is DCF77 coding rule schematic diagram.
Fig. 4 is 8 times of baud rate Serial data receiving schematic diagrames (data bit first is ' 1 ').
Fig. 5 is 8 times of baud rate Serial data receiving schematic diagrames (data bit first is ' 0 ').
Fig. 6 is the device of the invention system structure diagram.
Fig. 7 is time signal identification and overhaul flow chart of the invention.
Specific embodiment
As shown in fig. 6, the present apparatus include sequentially connected level shifting circuit, signal identification unit, signal demodulation unit,
Pulse quadruplex and temporal information comparing unit and framing output unit, signal identification unit include that sequentially connected edge sampling is single
Member counts accumulator element, count comparator unit and serial ports receiving module.Electricity of the level shifting circuit to input measured signal
It is flat to be converted, obtain the measured signal of unified electric type.Edge sampling unit carries out edge sampling to measured signal, counts
Accumulator element triggers the low level duration accumulator and the rising edge duration between in the rising edge of measured signal respectively
It is lasting between to trigger measured signal high level lasting time accumulator and failing edge in the failing edge of measured signal respectively for accumulator
Time totalizer, count comparator unit is according to the high level lasting time of measured signal, the low level duration, rising edge edge
Between duration and the failing edge duration between, judge the type of measured signal；Serial ports receiving module is same to measured signal
When 9600 ~ 153600bps of baud rate scope carry out data continuously receive, detect each serial received module received data
Whether it is made of any one in 0x80 and 0x00,0xc0 and 0x00,0xe0 and 0x00 or 0xf0 and 0x00；If baud rate is
The data that the serial received module of x receives are in 0x80 and 0x00,0xc0 and 0x00,0xe0 and 0x00 or 0xf0 and 0x00
Any one, then the baud rate of measured signal be x/8, x/7, x/6 or x/5 in corresponding one.Signal demodulation process list
Member carries out demodulation dissection process according to measured signal type, to measured signal, extracts or rebuild on-time point id signal, when extraction
Between information；According to the frame structure of timing code, reference symbols sn position is determined, the data after demodulation are arranged to obtain time letter
Breath, and reconstruction is compensated to on-time point id signal.Pulse quadruplex unit is punctual to reference time signal and measured signal
Point identification signal carries out phase demodulation processing, carries out edge sampling to the timing signal of measured signal and reference time scale respectively, is rising
Along latch accumulator count and ask poor, as the time delay of measured signal and fiducial time.After temporal information comparing unit will demodulate
Obtained measured signal temporal information is compared with reference time information, including when, minute, second, the TOD information comparison such as leap second.
Framing output unit will measure and comparison result carries out framing, be exported test result to host computer by serial ports.
As shown in fig. 7, realizing recognizing and detecting certainly for frequency time signal by following steps:
1) it is converted by level of the level shifting circuit to input measured signal, obtains the tested of unified electric type
Signal；Incoming level can be the types such as RS485, RS232 or TTL, be converted to CMOS to varying level input.
2) edge sampling is carried out to the measured signal after switching levels, starting accumulator counts signal along；
In step 2, high-precision markers is provided, by receiving Beidou/GPS/IRIG-B code, when receiving Beidou or GPS satellite
Between, generate high-precision markers.Local clock is tamed simultaneously, and equipment can also provide in the case where no external reference time source
Split-second precision standard.
Edge sampling is carried out to measured signal, accumulator is triggered in the rising edge of measured signal, latches under measured signal
Drop latches the count value of accumulator when the next rising edge of measured signal arrives along the count value of accumulator output when arriving；?
The failing edge of measured signal triggers accumulator, and the count value of accumulator output, is latched when latching the rising edge arrival of measured signal
The count value of accumulator when the next failing edge of measured signal arrives；Measured signal high level lasting time is obtained, low level is held
Continuous time, rising edge duration and failing edge duration between.
3) according to the high level lasting time of measured signal, the low level duration, rising edge along between the duration and
Failing edge duration between, judge the type of measured signal；
Specific step is as follows:
E. judge measured signal high level lasting time.According to the signal characteristic and data frame structure of time signal, if by
The high pulse width for surveying signal is equal to 8ms, triggers accumulator in next rising edge, latches meter when next failing edge arrives
Numerical value, the next high pulse width of measured signal are equal to 8ms, and measured signal is IRIG-B code.
F. judge measured signal high level lasting time and the rising edge duration between.According to the signal of time signal
Feature and data frame structure, if the measured signal rising edge period is 1s, measured signal is 1PPS pulse per second (PPS)；If measured signal rises
It is 1min along the period, measured signal is the punching of 1PPM sectors.
G. judge measured signal the low level duration.If monitoring the low level of lasting 1s, the starting second counts cumulative.Second
When counting accumulator equal to 20, starting high level lasting time judgement, if high level durations are 800ms, measured signal
For DCF77 code.
H. failing edge detection is carried out to measured signal, by multiple serial received modules to measured signal simultaneously in baud rate
9600 ~ 153600bps of range carries out data and continuously receives；Each serial received module received data is detected whether by 0x80
With any one composition in 0x00,0xc0 and 0x00,0xe0 and 0x00 or 0xf0 and 0x00；If baud rate is the serial interface of x
It is any one in 0x80 and 0x00,0xc0 and 0x00,0xe0 and 0x00 or 0xf0 and 0x00 for receiving the data that module receives
, then the baud rate of measured signal is corresponding one in x/8, x/7, x/6 or x/5.
I. continuously whether the cycle count value of record and the tested sampled signal of judgement continuously meets pulse per second (PPS), sectors rushes,
The signal characteristic of IRIG-B code, DCF77 code judges the type for determining input signal.
Consider the interference introduced in systematic error and transmission process, counting the edge of signal and pulsewidth can be counted and be continued
Record.It is counted between the edge of signal and pulsewidth counting continuously meets corresponding signal feature, if signal rising edge cycle count was in 5 seconds companies
It is continuous to be equal to 1s, then judge the signal for 1PPS.Signal characteristic is not met if there is counting, then counting latch is emptied, and
Judge that the signal is illegal, restarts counting and latch, restart to judge.
4) according to signal type, demodulation dissection process is carried out to measured signal, extracts or rebuilds on-time point id signal, mention
Take temporal information；According to the frame structure of timing code, reference symbols sn position is determined, the data after demodulation are arranged to obtain the time
Information, and reconstruction is compensated to on-time point id signal.
In step 4, judged according to signal type, IRIG-B code signal, DCF77 code and serial time message signals are carried out
Demodulation process determines reference symbols sn position according to IRIG-B code data frame structure, rebuilds punctual point identification in punctual reference mark
Signal；Wherein time information data is extracted according to IRIG-B code coding rule, the data after demodulation are arranged to obtain the time
Information, and on-time point id signal is compensated.According to the waveform configuration of DCF77, waveform counting period between is more than 1S, really
Fixed next failing edge is reference symbols sn position when reaching, and rebuilds on-time point id signal；According to DCF77 code coding rule, mention
Take time information data in carrier wave, arranged to obtain temporal information to the data after demodulation, and to on-time point id signal into
Row compensation.According to the baud rate of identification, reception and data demodulation are carried out to serial time message, the data after demodulation are carried out whole
Reason obtains temporal information；It determines data start bit position, rebuilds on-time point id signal in failing edge, and compensate.
5) tracking a reference source (the events source such as Beidou, GPS, B code) is received, reference time signal and temporal information are obtained；It is logical
Over-sampling and on-time point id signal progress phase demodulation of the counting to reference time signal and measured signal between；Simultaneously to a reference source
Processing is compared with measured signal temporal information in temporal information.
In step 5, the on-time point id signal phase demodulation of reference time signal and measured signal is handled, respectively to measured signal
Timing signal and reference time scale carry out edge sampling, latched in rising edge and accumulator count and ask poor, as measured signal and
The time delay of fiducial time.Measured signal temporal information will be obtained after demodulation simultaneously to be compared with reference time information, including when,
Minute, second, leap second etc. TOD information comparison.
6) it will measure and comparison result carries out framing, be exported test result to host computer by serial ports.
What has been described above is only a preferred embodiment of the present invention, it is noted that for those skilled in the art,
Without depart from that overall concept of the invention, several changes and improvements can also be made, these also should be considered as of the invention
Protection scope.
Claims (8)
1. a kind of realize polymorphic type time signal from the device for recognizing and detecting, it is characterised in that: including sequentially connected level
Conversion circuit, signal identification unit, signal demodulation unit, pulse quadruplex and temporal information comparing unit and framing output unit,
Signal identification unit includes that sequentially connected edge sampling unit, counting accumulator element, count comparator unit and serial ports connect
Receive module；
Level shifting circuit converts the level of input measured signal, obtains the measured signal of unified electric type；
Edge sampling unit carries out edge sampling to measured signal；
It counts accumulator element and triggers the low level duration accumulator and rising edge simultaneously between in the rising edge of measured signal
Duration accumulator triggers measured signal high level lasting time accumulator and failing edge in the failing edge of measured signal simultaneously
The duration accumulator between；
Count comparator unit continues between according to the high level lasting time of measured signal, the low level duration, rising edge
Time and the failing edge duration between, judge the type of measured signal；
Serial ports receiving module carries out data to measured signal and continuously receives, and detecting each serial received module received data is
The no any one by 0x80 and 0x00,0xc0 and 0x00,0xe0 and 0x00 or 0xf0 and 0x00 forms；If baud rate is x
The data that receive of serial received module be in 0x80 and 0x00,0xc0 and 0x00,0xe0 and 0x00 or 0xf0 and 0x00
Any one, then the baud rate of measured signal be x/8, x/7, x/6 or x/5 in corresponding one；
Signal demodulation unit carries out demodulation dissection process according to measured signal type, to measured signal, extracts or rebuild on-time point
Id signal, extracting time information；According to the frame structure of timing code, reference symbols sn position is determined, the data after demodulation are carried out
Arrangement obtains temporal information, and compensates reconstruction to on-time point id signal；
Pulse quadruplex reflects to reference time signal and the on-time point id signal of measured signal with temporal information comparing unit
Phase processor, and the measured signal temporal information obtained after demodulation is compared with reference time information；
Framing output unit will measure and comparison result carries out framing, be exported test result to host computer by serial ports.
2. according to claim 1 realize polymorphic type time signal from the device for recognizing and detecting, it is characterised in that: serial ports
Receiving module carries out data in 9600 ~ 153600bps of baud rate scope simultaneously to measured signal and continuously receives.
3. according to claim 1 realize polymorphic type time signal from the device for recognizing and detecting, it is characterised in that: pulse
When the comparison information of phase demodulation and temporal information comparing unit includes, minute, second, leap second TOD information.
4. a kind of realize polymorphic type time signal from the method for recognizing and detecting, characterized by the following steps:
Step 1: being converted by level of the level shifting circuit to input measured signal, obtain the tested of unified electric type
Signal；
Step 2: edge sampling being carried out to the measured signal after switching levels, starting accumulator counts signal along, obtains
To measured signal high level lasting time, the low level duration, rising edge duration and failing edge between continue between
Time；
Step 3: according to the high level lasting time of measured signal, the low level duration, rising edge along between the duration and
Failing edge duration between, judge the type of measured signal；
Specifically comprise the following steps:
Step a: detection measured signal high level lasting time detects next high level if high level lasting time is equal to 8ms
Duration, if next high level lasting time is also equal to 8ms, measured signal is IRIG-B code；
Step b: detection measured signal rising edge duration between, if measured signal rising edge duration between is 1s,
Measured signal is 1PPS pulse per second (PPS)；If measured signal rising edge duration between is 1min, measured signal is 1PPM sectors
Punching；
Step c: detection measured signal the low level duration, if monitoring the low level of lasting 1s, the starting second counts cumulative, the second
When counting accumulator equal to 20, starting high level lasting time detection, if high level durations are 800ms, measured signal
For DCF77 code；
Step d: carrying out failing edge detection to measured signal, and it is continuous to carry out data to measured signal by multiple serial received modules
It receives；Detect each serial received module received data whether by 0x80 and 0x00,0xc0 and 0x00,0xe0 and 0x00 or
Any one composition in 0xf0 and 0x00；If the data that receive of serial received module that baud rate is x be 0x80 and
Any one in 0x00,0xc0 and 0x00,0xe0 and 0x00 or 0xf0 and 0x00, then the baud rate of measured signal is x/8, x/
7, corresponding one in x/6 or x/5；
Step 4: according to signal type, demodulation dissection process being carried out to measured signal, extracts or rebuilds on-time point id signal, mention
Take temporal information；According to the frame structure of timing code, reference symbols sn position is determined, the data after demodulation are arranged to obtain the time
Information, and reconstruction is compensated to on-time point id signal；
Step 5: receiving tracking a reference source, obtain reference time signal and temporal information；It counts by sampling and between to benchmark
Time signal and the on-time point id signal of measured signal carry out phase demodulation；Simultaneously to a reference source temporal information and measured signal time
Processing is compared in information；
Step 6: measurement and comparison result being subjected to framing, exported test result to host computer by serial ports.
5. according to claim 4 realize polymorphic type time signal from the method for recognizing and detecting, it is characterised in that: step
In 1, incoming level RS485, RS232 or TTL, output level CMOS.
6. according to claim 4 realize polymorphic type time signal from the method for recognizing and detecting, it is characterised in that: step
In 2, by receiving Beidou or GPS satellite time or taming local clock, high-precision markers is generated.
7. according to claim 4 realize polymorphic type time signal from the method for recognizing and detecting, it is characterised in that: step
In 3, lasting record is counted between the counting along of signal and pulsewidth, is continuously met accordingly if the counting between of signal and pulsewidth count
Signal characteristic judges the signal then for legal signal and provides differentiation result；If being counted between the edge of signal and pulsewidth counting and occurs
Corresponding signal feature is not met, then counting latch is emptied, and judge that the signal is illegal, counting is restarted and latches, open again
Begin to judge.
8. according to claim 4 realize polymorphic type time signal from the method for recognizing and detecting, it is characterised in that: step
In d, the baud rate scope of multiple serial received modules is 9600 ~ 153600bps.
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| CN111090234B (en) * | 2019-12-30 | 2022-02-15 | 郑州威科姆华大北斗导航科技有限公司 | Satellite anti-spoofing processing method based on time synchronization device |
| CN112422363A (en) * | 2020-10-27 | 2021-02-26 | 成都航空职业技术学院 | Automatic detection device and method for asynchronous serial port communication baud rate |
| CN114173296B (en) * | 2021-11-16 | 2023-05-05 | 万通智控科技股份有限公司 | Monitoring method and device based on radio frequency technology |
| CN115329822B (en) * | 2022-10-12 | 2023-01-20 | 深圳市恒运昌真空技术有限公司 | Pulse identification method and device |
| CN116577809A (en) * | 2023-04-06 | 2023-08-11 | 郑州威科姆华大北斗导航科技有限公司 | Universal GNSS satellite receiving module automatic test software and method |
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