JP4459276B2 - Method for detecting phase difference of digital signal - Google Patents

Description

  The present invention relates to a phase difference detection method for a digital signal, and more particularly to a phase difference detection method suitable for use in tracking servo technology in an optical disc apparatus.

  FIG. 19 shows an example of a conventional tracking servo mechanism using a DPD (Differential Phase Detection) method. This tracking servo mechanism is often used for DVD (Digital Versatile Disc).

  The optical pickup 100 condenses and irradiates the signal recording surface of the optical disc 102 with the laser beam LB, detects the reflected light beam from the signal recording surface, performs photoelectric conversion, and generates a high-frequency wave having a waveform corresponding to the concavo-convex pattern of the pit row. An electric signal, that is, an RF signal is generated. Here, the photoelectric conversion unit 104 of the optical pickup 100 includes, for example, four light receiving areas A, B, C, and D made of photodiodes. Although not shown, these light receiving areas A, B, C, and D are slanted. They are divided and arranged so as to face each other. The RF signals A and C obtained from the light receiving areas A and C located on one diagonal line are substantially in phase with each other, and the RF signals obtained from the light receiving areas B and D located on the other diagonal line, respectively. B and D have a substantially in-phase relationship with each other, and the RF signals A and C and the RF signals B and D have a relationship in which the mutual phase difference varies according to the tracking error. Although the photoelectric conversion unit 104 is actually inside the optical pickup 100, FIG. 19 shows the photoelectric conversion unit 104 taken out from the optical pickup 100 for convenience of explanation.

  The tracking servo circuit includes a front-stage analog front end unit 106 made of an analog circuit and a back-stage digital front end unit 108 made of a digital circuit. Both front end portions 106 and 108 are often formed on separate semiconductor chips.

  In the analog front end unit 106, gain control amplifiers (GCAs) 110, 112, 114, and 116 adjust the amplitudes of the RF signals A, B, C, and D from the photoelectric conversion unit 104 of the optical pickup 100, respectively. Equalizers (EQ) 118, 120, 122, and 124 perform waveform shaping and noise cut by high frequency emphasis on RF signals A, B, C, and D, respectively. The offset / cancellation circuits 126, 128, 130, and 132 remove the offset so as to align the center levels (zero levels) of the RF signals A, B, C, and D, respectively. The zero cross detectors (ZRC) 134, 136, 138, 140 are each composed of a comparator made up of operational amplifiers, and as shown in FIG. 20, the reference signal level where the voltage levels of the RF signals A, B, C, D are zero is shown. Is detected, and a binary signal corresponding to the timing of each zero cross is output for each rising edge and each falling edge.

  One phase difference detector 142 includes a binary signal (A) from the zero-cross detector (ZRC) 134 corresponding to the RF signal A and a binary signal (ZRC) 136 corresponding to the RF signal B ( B) and a pulse signal having a variable pulse width corresponding to the phase difference between the binary signals (A) and (B) or the first phase difference signal φAB is output as shown in FIG. . The first phase difference signal φAB is output with a positive polarity when the phase of the binary signal (A) is advanced with respect to the binary signal (B), and is binary with respect to the binary signal (B). When the phase of the signal (A) is delayed, it is output with negative polarity.

  The other phase difference detector 144 includes a binary signal (C) from the zero cross detector (ZRC) 138 corresponding to the RF signal C and a binary signal (ZRC) 140 from the zero cross detector (ZRC) 140 corresponding to the RF signal D. D) is input, and a pulse signal having a variable pulse width corresponding to the phase difference between the binary signals (C) and (D) or the second phase difference signal φCD is output. The second phase difference signal φCD is output with a positive polarity when the phase of the binary signal (C) is advanced with respect to the binary signal (D), and is binary with respect to the binary signal (D). When the phase of the signal (C) is delayed, it is output with negative polarity.

  The first and second phase difference signals φAB and φCD output from the phase difference detectors 142 and 144 as described above are added together by an adder 146 formed of an operational amplifier. Basically, the sum signal φAB / CD output from the adder 146 can be used as a DPD tracking error signal. However, normally, in order to extract an error component necessary for the tracking servo, the output signal φAB / CD of the adder 146 is averaged through a low-pass filter (LPF) 148 (FIG. 21), and further a gain control amplifier (GCA) The gain adjusted through 150 is supplied to the digital front end unit 108 as a tracking error signal.

  The digital front end unit 108 is responsive to an analog-to-digital (A / D) converter 152 for converting an analog tracking error signal from the analog front end unit 106 into a digital tracking error signal, and in response to the tracking error signal. A servo processor (for example, DSP: Digital Signal Processor) 154 is provided that provides a control signal for controlling the position of the optical pickup 100 in the radial direction of the optical disk 102 to the feed mechanism or actuator 156.

  When the beam spot of the laser beam LB deviates from the center of the track in the radial direction on the signal recording surface of the optical disc 102, the phase difference between the RF signals A and B and the interval between the RF signals C and D according to the magnitude of the tracking deviation. Of the phase difference between the output signals φAB and φCD of the phase difference detectors 142 and 144, the output signal φAB / CD of the adder 146, and the phase difference information included in the output signal of the low pass filter (LPF) 148, that is, tracking. Error information is fed back to the servo DSP 154. The servo DSP 154 controls the position of the optical pickup 100 in the radial direction through the feeding mechanism 156 in accordance with the feedback tracking error information, so that tracking servo for causing the beam spot of the laser beam LB to follow the track is applied. A digital-analog (D / A) converter (not shown) may be provided between the servo DSP 154 and the feed mechanism 156.

  The conventional tracking servo circuit as described above has a two-chip (106, 108) configuration, and the areas of the equalizers (EQ) 118 to 124 and the low-pass filter (LPF) 148 are particularly large. The problem is that the circuit scale of 106 is large. Therefore, it is desired to reduce the circuit area and to make the entire tracking servo circuit into one chip by digitizing the analog front end unit 106.

  However, since the zero-crossing time obtained from the outputs of the zero-crossing detectors (ZRC) 134 to 140 composed of comparators takes a time continuous value, the zero-crossing detectors (ZRC) 134 to 140 and the phase difference detectors 142 and 144 are used. If it is to be configured with a synchronous digital circuit as it is, the measurement accuracy of the zero crossing time depends on the clock frequency. Therefore, in order to obtain the same accuracy as an analog circuit, a clock frequency of tens of thousands of GHz and such a clock frequency Requires very high speed digital circuits that are almost impossible to achieve with current digital technology. Since the zero-cross detectors (ZRC) 134 to 140 and the phase difference detectors 142 and 144 cannot be realized by a digital synchronous circuit in this way, even if only the equalizer (EQ) 118 to 124 and the low-pass filter (LPF) 148 are digitized, it is It is difficult to connect digitally to this circuit. After all, the current state of the prior art is that all the functions in the front-end front end unit 106 must be implemented by analog circuits.

  The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a method capable of detecting a phase difference of a digital signal with high accuracy by a relatively low-speed and small-scale digital circuit. And

To achieve the above object, a digital signal phase difference detection method according to the present invention detects a phase difference between a first digital signal and a second digital signal which are discrete data streams having the same period. A method of maintaining the polarity and value of a first digital value of a first digital signal relative to a first reference value; and the first reference of a second digital value of the first digital signal. Holding a polarity and a value for a value; holding a polarity and a value for a second reference value of a first digital value of the second digital signal; and a second digital value of the second digital signal Holding a polarity and a value with respect to the second reference value, and a polarity of the first digital value of the first digital signal and the first digital signal The relationship between the polarity of the second digital value, the relationship between the polarity of the first digital value of the second digital signal and the polarity of the second digital value of the second digital signal, and The relationship between the polarity of the first digital value of the first digital signal and the polarity of the first digital value of the second digital signal or the polarity of the second digital value of the first digital signal The pattern of the first digital signal corresponding to the pattern divided based on the relationship of the polarity of the second digital value of the second digital signal or the relationship of the pattern and the immediately preceding pattern . 1 digital value, the second digital value of the first digital signal, the first digital value of the second digital signal, the second digital value, The value of the second digital value of the digital signal, the difference between the value of the first digital value of the first digital signal and the value of the second digital value of the first digital signal, the second An operation is performed on the difference between the value of the first digital value of the digital signal and the value of the second digital value of the second digital signal, and the operation result is calculated as the first digital value and the second digital value. Providing as a phase difference between the first digital signal and the second digital signal between the first and second digital values .

  In this phase difference detection method, according to a preferred aspect, the calculation corresponding to the pattern includes the value of the first digital value of the first digital signal and the first digital signal of the first digital signal. The difference between the value of the digital value and the value of the second digital value of the first digital signal, the value of the second digital value of the first digital signal, and the first digital signal The difference between the first digital value of the first digital signal and the second digital value of the first digital signal; the first digital value of the second digital signal; The second digital value of the second digital signal is divided by the difference between the value of the first digital value of the second digital signal and the value of the second digital value of the second digital signal. And the value of Serial is performed based on dividing the difference between the value of the second digital value of the second digital signal of said first digital value value and the second digital signal.

  According to the present invention, with the above-described configuration, it is possible to detect a phase difference of a digital signal with high accuracy by a relatively low-speed and small-scale digital circuit.

  Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS.

  FIG. 1 shows the configuration of a DVD tracking servo mechanism to which a digital signal phase difference detection method according to an embodiment of the present invention can be applied. In the drawing, the configurations and functions of the optical pickup 100, the optical disk 102, the photoelectric conversion unit 104, the servo DSP 154, and the feeding mechanism 156 are the same as the corresponding ones in FIG. 19, and thus detailed descriptions thereof are omitted.

  The tracking servo circuit 10 in this embodiment can be configured as a one-chip circuit in which an analog circuit and a digital circuit are mixedly mounted on one semiconductor chip. Among these, the analog circuits are only low-pass filters (LPF) 12 to 18 and gain control amplifiers (GCAs) 20 to 26 at the input section, and are circuits or offsets after the analog-digital (A / D) converters 28 to 34. Cancel circuit 36 to 42, equalizer (EQ) 44 to 50, first and second phase difference detectors 52 and 54, adder 56, low pass filter (LPF) 58, gain control amplifier (GCA) 60 and servo DSP 154 All are composed of digital circuits.

  Low-pass filters (LPF) 12, 14, 16, and 18 are anti-aliasing filters, and noises of high-frequency components included in the RF signals A, B, C, and D from the photoelectric conversion unit 104 of the optical pickup 100. Are removed respectively. Gain control amplifiers (GCAs) 20, 22, 24, and 26 adjust the amplitudes of the RF signals A, B, C, and D, respectively. The analog-to-digital (A / D) converters 28, 30, 32, and 34 respectively apply the RF signals A, B, C, and D to a predetermined sampling frequency (for example, when the channel clock frequency is 4.36 MHz, six times that). (26.16 MHz) is converted into a digital signal. The offset / cancellation circuits 36, 38, 40, and 42 remove the offsets included in the RF signals A, B, C, and D, respectively, to make the center level (zero level) uniform. Equalizers (EQ) 44, 46, 48 and 50 perform waveform shaping and noise cut by applying high frequency emphasis by digital arithmetic processing to the RF signals A, B, C and D, respectively.

  One phase difference detector 52 receives the digital signal (A) from the equalizer (EQ) 44 corresponding to the RF signal A and the digital signal (B) from the equalizer (EQ) 46 corresponding to the RF signal B. The zero crossing time points of the RF signals A and B are detected by digital arithmetic processing described later, and a first phase difference signal ΦAB representing the time difference between the corresponding zero crosses between the RF signals A and B is generated.

  The other phase difference detector 54 inputs the digital signal (C) from the equalizer (EQ) 48 corresponding to the RF signal C and the digital signal (D) from the equalizer (EQ) 50 corresponding to the RF signal D. Then, the respective zero crossing time points between the RF signals C and D are detected by digital arithmetic processing described later, and the second phase difference signal ΦCD representing the time difference between the corresponding zero crosses between the RF signals C and D is generated. .

  The first and second phase difference signals ΦAB and ΦCD output from both phase difference detectors 52 and 54 are added by an adder 56. Basically, the sum signal ΦAB / CD (ΦAB + ΦCD) output from the adder 56 can be used as a DPD tracking error signal. In this embodiment, in order to increase the stability and response speed of the tracking servo, the output signal ΦAB / CD of the adder 56 is averaged through a low-pass filter (LPF) 58 and further passed through a gain control amplifier (GCA) 60. Then, the gain adjusted is given to the servo DSP 154 as a tracking error signal.

Also in this embodiment, when the beam spot of the laser beam LB deviates in the radial direction from the center of the track on the signal recording surface of the optical disc 102, the phase difference between the RF signals A and B and the amount of tracking deviation The phase difference between the RF signals C and D changes, and is included in the output signals ΦAB and ΦCD of both the phase difference detectors 52 and 54 and the output signal ΦAB / CD of the adder 56 and thus the output signal of the low-pass filter (LPF) 58. Phase difference information, that is, tracking error information, is fed back to the servo DSP 154. The servo DSP 154 controls the position of the optical pickup 100 in the radial direction through the feeding mechanism 156 in accordance with the feedback tracking error information, so that tracking servo for causing the beam spot of the laser beam LB to follow the track is applied.
One of the features in this embodiment is an algorithm for generating the first and second phase difference signals ΦAB and ΦCD by the digital arithmetic processing in both phase difference detectors 52 and 54.

FIG. 2 shows a configuration example of the phase difference detector 52. This phase difference detector 52 is a zero-cross detector 62, 64 for detecting the zero-crossing time points of both RF signals A, B, and a phase difference calculation for obtaining a time difference between the corresponding zero-crosses between the RF signals A, B. Part 66. The zero-cross detector 62 monitors the sign of the digital value for each sampling interval of the digital signal (A) from the equalizer (EQ) 44 corresponding to the RF signal A, and before and after the sign changes as shown in FIG. by calculating a predetermined approximate expression for example first-order approximation formula (1) into a plurality example based on two digital values a _n-1, a _n, determined by interpolating the time point t _ZA zero crossing ZA in the RF signal a.
t _ZA = t _n-1 + | A _n-1 | TS / | A _n-1 −A _n | (1)

Here, t _n-1 is the sampling time immediately before the sign is changed, and TS is the sampling period. When normalizing the time within the sampling period, TS = 1 may be set.

Similarly, for the digital signal (B) from the equalizer (EQ) 46 corresponding to the RF signal B, the zero cross detection unit 64 monitors the sign of the digital value for each sampling section, and a plurality of, for example, two before and after the sign changes. Based on the digital values B _n−1 and B _n , the same approximate expression as the above expression (1) is calculated, and the time t _ZB of the zero cross ZB in the RF signal B is interpolated and obtained.

The phase difference calculation unit 66 obtains a time difference (t _ZA −t _ZB ) between the interpolated zero crosses corresponding (temporally adjacent) between the RF signals A and B, and this time difference, that is, a phase difference (t _ZA −t _ZB ) is output as a first phase difference signal ΦAB.

The other phase difference detector 54 has the same configuration (FIG. 2) as the phase difference detector 52, and has the same function (FIG. 3). Therefore, from the phase difference detector 54, a digital signal representing the time difference between the interpolated zero crosses corresponding in time (adjacent in time) between the RF signals C and D, that is, the phase difference (t _ZC −t _ZD ) is second. Is output as a phase difference signal ΦCD.

FIG. 4 shows a configuration of the phase difference detector 52 in the embodiment. The phase difference detector 52 includes 1-sample delay circuits or delay registers (Z ⁻¹ ) 70 and 72, a case determination unit 74, a phase difference calculation unit 76, and a multiplexer (MUX) 78.

The case determination unit 74 inputs the digital signals from the equalizers (EQ) 44 and 46 corresponding to both RF signals A and B and the digital signal one sample before from the delay registers (Z ⁻¹ ) 70 and 72, A pattern of a sign relationship between a set of digital values (A _n−1 , B _n−1 , A _n , B _n ) obtained at two sampling points (t _n−1 , t _n ) that are continuous for each sampling interval Is determined. As shown in FIGS. 5 to 14, there are nine cases 0 (0-0, 0) in the sign relation pattern between these sets of digital values (A _n , B _n , A _n−1 , B _n−1 ). -1), 1, 2, 3, 4, 5, 6, 7.

Case 0, as shown in FIG. 5, different code of the code and B _n of _{A n (signA n ≠ signB n} ), different codes of A _n-1 symbols as _{A n (signA n-1 ≠} signA _n ), when the code of B _n-1 is different from the code of B _n (signB _n-1 ≠ signB _n ). In this case 0, further, the zero cross ZA comes after the zero cross ZB as shown in FIG. 6 and the zero cross as shown in FIG. Cases 0 to 1 where ZA comes before the zero cross ZB.

Case 1, as shown in FIG. 8, different code of the code and B _n of _{A n (signA n ≠ signB n} ), different codes of A _n-1 symbols as _{A n (signA n-1 ≠} signA _n ), the code of B _n-1 is the same as the code of B _n (signB _n-1 = signB _n ).

Case 2, as shown in FIG. 9, different code of the code and B _n of _{A n (signA n ≠ signB n} ), A n-1 of the code of the code and A _n are the same (signA _n-1 = signA _n ), when the code of B _n-1 is different from the code of B _n (signB _n-1 ≠ signB _n ).

Case 3, as shown in FIG. 10, different codes of a code and B _n of _{A n (signA n ≠ signB n} ), A n-1 of the code of the code and A _n are the same (signA _n-1 = signA _n ), the code of B _n-1 is the same as the code of B _n (signB _n-1 = signB _n ).

Case 4, as shown in FIG. 11, the sign of the sign and B _n of A _n are the same (signA _n = signB _n), different codes of A _n-1 symbols as _{A n (signA n-1 ≠} signA _n ), when the code of B _n-1 is different from the code of B _n (signB _n-1 ≠ signB _n ).

Case 5, as shown in FIG. 12, the sign of the sign and B _n of A _n are the same (signA _n ≠ signB _n), different codes of A _n-1 symbols as _{A n (signA n-1 ≠} signA _n ), the code of B _n-1 is the same as the code of B _n (signB _n-1 = signB _n ).

Case 6, as shown in FIG. 13, A _n reference symbols in B _n is the same _{(signA n = signB n),} A n-1 of the code of the code and A _n are the same (signA _n-1 = signA _n ), when the code of B _n-1 is different from the code of B _n (signB _n-1 ≠ signB _n ).

Case 7, as shown in FIG. 14, A _n reference symbols in B _n is the same _{(signA n = signB n),} A n-1 of the code of the code and A _n are the same (signA _n-1 = signA _n ), the code of B _n-1 is the same as the code of B _n (signB _n-1 = signB _n ).

The phase difference calculation unit 76 also receives the digital signals from the equalizers (EQ) 44 and 46 corresponding to both RF signals A and B and the digital signal delayed by one sample from the delay registers (Z ⁻¹ ) 70 and 72. . Then, nine arithmetic expressions are executed for a set of four simultaneously inputted digital values (A _n−1 , B _n−1 , A _n , B _n ), and nine arithmetic outputs Q00n, Q01n, Q1n are executed. , Q2n, Q3n, Q4n, Q5n, Q6n, Q7n are generated.

The first calculation output Q00n is the calculation result of the following calculation expression (2), and is suitable for case 0-0 as shown in FIG. Here, T _A, T _B is the two RF signals A, period the sign of the two signals are different in the primary approximation B of the inner section _{(t n-1 ~t n)} .
Q00n = T _A + T _B
= | A _n | / | A _n-1 −A _n | + | B _n-1 | / | B _n-1 −B _n | (2)

The second calculation output Q01n is the calculation result of the following calculation formula (3), and is suitable for case 0-1 as shown in FIG. Again, T _A, T _B is the two RF signals A, period the sign of the two signals are different in the primary approximation B of the inner section _{(t n-1 ~t n)} .
_{Q01n = - (T A + T} B)
=-| A _n-1 | / | A _n-1 -A _n |-| B _n | / | B _n-1 -B _n | (3)

The third calculation output Q1n is the calculation result of the following calculation formula (4), and is suitable for case 1 as shown in FIG. Here, T _A is the two RF signals A, period the sign of the two signals are different in the primary approximation B of the inner section _{(t n-1 ~t n)} .
Q1n = T _A
= | A _n | / | A _n-1 −A _n | (4)

The fourth calculation output Q2n is the calculation result of the following calculation expression (5), and is suitable for case 2 as shown in FIG. Here, T _B is the two RF signals A, period the sign of the two signals are different in the primary approximation B of the inner section _{(t n-1 ~t n)} .
Q01n = -T _B
=-| _Bn | / | _Bn-1 - _Bn | (5)

The fifth calculation output Q3n is the calculation result of the following calculation formula (6), and is suitable for case 3 as shown in FIG. In this case, Q3 takes one of three values depending on the case of the immediately preceding section (t _{n-2 to} t _{n- 1} ).
Q3n = T _S = 1 (the immediately preceding section is case 0-0 or case 1)
Q3n = -T _S = -1 (just before the interval case 0-1 or Case 2)
Q3n = Q3n-1 (in cases other than the above) (6)

The sixth calculation output Q4n is the calculation result of the following calculation formula (7), and is suitable for case 4 as shown in FIG. Here, a (T _A -T _B) is a period having a different and the sign of the RF signal A-side of the sign and the RF signal B-side in a first approximation of the inner section _{(t n-1 ~t n)} .
Q4n = T _A -T _B
= | A _n | / | A _n-1 −A _n | − | B _n | / | B _n−1 −B _n | (7)

The seventh calculation output Q5n is the calculation result of the following calculation expression (8), and is suitable for case 5 as shown in FIG. Here, T _A is the two RF signals A, period the sign of the two signals differ in first approximation of B in the unit interval _{(t n-1 ~t n)} .
Q5n = -T _A
=-| A _n-1 | / | A _n-1 -A _n | (8)

The eighth calculation output Q6n is the calculation result of the following calculation expression (9), and is suitable for case 6 as shown in FIG. Here, T _B is the two RF signals A, period the sign of the two signals are different in the primary approximation B of the inner section _{(t n-1 ~t n)} .
Q6n = T _B
= | B _n-1 | / | B _n-1 −B _n | (9)

The ninth calculation output Q7n is the calculation result of the following calculation expression (10), and is suitable for case 7 as shown in FIG. In this case, both the RF signal A, a period in which the sign of the two signals are different in the primary approximation B of the inner section (t _n-1 ~t n) is impossible.
Q7n = 0 (10)

The nine calculation outputs Q00n to Q7n obtained simultaneously by the phase difference calculation unit 76 as described above are input to the multiplexer (MUX) 78 all at once. Among them, the significant or effective calculation output matches the pattern of the sign relationship between the current input digital values (A _n−1 , B _n−1 , A _n , B _n ), that is, the case determination unit 74. Is a calculation result of an arithmetic expression corresponding to the case determined by the above-described case, and is selected by a multiplexer (MUX) 78 by a control signal from the case determination unit 74. Accordingly, when the pattern of the sign relationship between one set or four input digital values (A _n−1 , B _n−1 , A _n , B _n ) obtained in an arbitrary sampling interval is, for example, Case 5, The seventh operation output Q5n is output from the multiplexer (MUX) 78 in the sampling period. FIG. 15 shows the correspondence between the cases 0-0, 0-1, 1, 2, 3, 4, 5, 6, 7 and the operation outputs Q00n, Q01n, Q1n, Q2n, Q3n, Q4n, Q5n, Q6n, Q7n. The relationship is shown in a list.

As described above, the calculation output Q corresponding to each case is a digital value in a period in which the signs of both the RF signals A and B in the section (t _{n-1 to} t _n ) are linearly approximated. To express. This corresponds to the period in which the signs of both RF signals A and B are different in the conventional analog signal processing method (FIG. 21) expressed by the pulse width of the logical value “1” in the output of the phase difference detector. . FIG. 16 and FIG. 17 show schematic waveforms for helping understanding of this correspondence.

FIG. 16 shows a case where the phase of the RF signal A is ahead of the phase of the RF signal B. The first section (t _{0 to} t ₁ ) is the pattern of case 4, and the above calculation formula (7) is applied, and the calculation output Q4n (value = 0.4) as the calculation result is the next section (t _1). To t ₂ ) from the multiplexer (MUX) 78.

The second section (t _{1 to} t ₂ ) is the pattern of case 7, and the above calculation formula (10) is applied, and the calculation output Q7n (value = 0.0) as the calculation result is the next section (t _2). To t ₃ ) from the multiplexer (MUX) 78.

The third section (t _{2 to} t ₃ ) is the pattern of case 1, and the above calculation formula (4) is applied, and the calculation output Q1n (value = 0.6) as the calculation result is the next section (t _3). To t ₄ ) from the multiplexer (MUX) 78.

The fourth section (t _{3 to} t ₄ ) is the pattern of case 6, and the above calculation formula (9) is applied, and the calculation output Q6n (value = 0.3) as the calculation result is the next section (t _4). To t ₅ ) from the multiplexer (MUX) 78.

The fifth section (t _{4 to} t ₅ ) is the pattern of case 1, and the above calculation formula (4) is applied, and the calculation output Q1n (value = 0.3) as the calculation result is the next section (t _5). To t ₆ ) from the multiplexer (MUX) 78.

The sixth section (t _{5 to} t ₆ ) is the pattern of case 3, and the above arithmetic expression (6) is applicable. Here, since the immediately preceding period is case 1, the operation output Q3n is given by Q3n = 1, output from the multiplexer (MUX) 78 in the next period (t ₆ ~t _7).

The seventh section (t _{6 to} t ₇ ) is the pattern of case 6, and the above calculation formula (9) is applied, and the calculation output Q6n (value = 0.4) as the calculation result is the next section (t _7). To t ₈ ) from the multiplexer (MUX) 78.

  In FIG. 16, the output of the phase difference detector obtained in the conventional analog signal processing method (FIG. 21) as a comparative example is also shown on the same time axis. Whereas the phase difference between the RF signals A and B is represented by the pulse width of the pulse that is continuous in time in the conventional method, the present invention represents the discrete digital value for each section (sampling period). Although the phase difference output timing is different from the conventional method in that the present invention is delayed by about one clock, the value (area) obtained by time-integrating the output (phase difference signal) of the phase difference detector is substantially the same or equivalent. It is.

  FIG. 17 shows a case where the phase of the RF signal A is delayed from the phase of the RF signal B. Except for the fact that the sign of the output of the phase difference detector is inverted, the same operation as in the case of FIG. 16 is achieved. Since this is clear from the illustration, a detailed description is omitted.

  Returning to FIG. 1, also in the second embodiment, the other phase difference detector 54 has the same configuration as the phase difference detector 52 (FIG. 4), and both RF signals C and D are the same as described above. Digital arithmetic processing (FIGS. 5 to 17) is performed. In principle, only one of the phase difference information ΦAB between the RF signals A and B or the phase difference information ΦCD between the RF signals C and D can be used as tracking error information.

  As described above, according to the present invention, the zero-crossing time detection unit mounted in the analog circuit in the conventional system is replaced with a digital circuit with a speed (MHz order) that can be easily realized, and is equivalent to the analog signal processing system. Tracking error detection and tracking servo can be performed with high accuracy, and not only the zero-crossing time detection unit but also many parts of the entire system (especially the equalizer and low-pass filter provided respectively before and after the phase difference detection unit) Can be replaced from an analog circuit to a digital circuit. As a result, the circuit area of the entire system can be reduced to a fraction of the conventional one, and a one-chip configuration can be easily realized. In addition, the power consumption can be reduced by reducing the area, and the accompanying effects that the digitalization leads to the ease of changing the circuit design accompanying the change of the semiconductor process and the shortening of the development time can be obtained.

The present invention is not limited to the above-described embodiment, and various modifications and changes can be made within the scope of the technical idea. For example, in order to obtain the time of zero crossing in each RF signal by interpolation, the first embodiment uses the linear approximation formula (1) based on two digital values (A _n−1 , A _n ) before and after the sign changes. Is, for example, three digital values (A _n-2 , A _n-1 , A _n ) or four digital values (A _n-2 , A _n-1 , A _n , A _{n + 1} ) before and after the sign changes. It is also possible to use a second-order approximation or a third-order approximation based on the above. Moreover, the said embodiment can be deform | transformed according to the variation of a DPD system. For example, as shown in FIG. 18, two sum signals (A + C) and (B + D) are generated from analog signals 80 and 82 from RF signals A, B, C and D, and both sum signals (A + C) and (B + D) are generated. The combined tracking error signal ΦAB / CD can be obtained from the phase difference detector 52 using the same signal processing circuit (12 to 54) as one system (for example, the A / B system) of the above embodiment. In addition, the anti-aliasing low-pass filter (LPF) 12 to 18, the gain control amplifier (GCA) 20 to 26, the A / D converters 28 to 34, and other circuits in the input unit are subjected to other signal processing (for example, focusing servo). It is also possible to use them together. The present invention is not limited to a DVD, and can be applied to other optical disc apparatuses such as a CD (Compact Disc).

It is a block diagram which shows the structure of the tracking servo mechanism for DVD which can apply the phase difference detection method of the digital signal in one Embodiment of this invention. It is a block diagram which shows the example of 1 structure of a phase difference detector. It is a figure which shows the algorithm of the zero cross interpolation in an Example. It is a block diagram which shows the structure of the phase difference detector in embodiment. It is a figure which shows one case (0) in the code | cord | chord relationship pattern between a set of digital values. It is a figure which shows one case (0-0) in the code | cord | chord relationship pattern between a set of digital values. It is a figure which shows one case (0-1) in the code | cord | chord relationship pattern between a set of digital values. It is a figure which shows one case (1) in the code | cord | chord relationship pattern between a set of digital values. It is a figure which shows one case (2) in the code | cord | chord relationship pattern between a set of digital values. It is a figure which shows one case (3) in the code | cord | chord relationship pattern between a set of digital values. It is a figure which shows one case (4) in the code | cord | chord relationship pattern between a set of digital values. It is a figure which shows one case (5) in the code | cord | chord relationship pattern between a set of digital values. It is a figure which shows one case (6) in the code | cord | chord relationship pattern between a set of digital values. It is a figure which shows one case (7) in the code | cord | chord relationship pattern between a set of digital values. It is a figure which shows the correspondence of each case and each calculation output obtained with the phase difference detector of an Example by a table | surface. It is a wave form diagram which shows the correspondence of the conventional analog signal processing system and the digital signal processing system of an Example. It is a wave form diagram which shows the correspondence of the conventional analog signal processing system and the digital signal processing system of an Example. It is a block diagram which shows the structure of the tracking servo mechanism by one modification. It is a block diagram which shows the structure of the conventional tracking servo mechanism. It is a wave form diagram which shows the zero cross detection method in a prior art. It is a wave form diagram which shows the signal processing method which the tracking error signal produces | generates in a prior art.

Explanation of symbols

10 Tracking servo circuit 12, 14, 16, 18 LPF for anti-aliasing
20, 22, 24, 26 Gain control amplifier (GCA)
28, 30, 32, 34 A / D converter 36, 38, 40, 42 Offset cancel circuit 44, 46, 48, 50 Equalizer (EQ)
52, 54 Phase difference detector 56 Adder 58 LPF for averaging
60 Gain Control Amplifier (GCA)
62, 64 Zero cross detection unit 66 Phase difference calculation unit 70, 72 Delay register 74 Case discrimination unit 76 Phase difference calculation unit 100 Optical pickup 102 Optical disc 154 Servo DSP
156 Feed mechanism A, B, C, D Photoelectric converter

Claims (2)

A method for detecting a phase difference between a first digital signal and a second digital signal which are discrete data streams of the same period, comprising:
Maintaining the polarity and value of the first digital value at the first time of the first digital signal relative to the first reference value;
Holding a polarity and a value of the second digital value at a second time after the first time of the first digital signal with respect to the first reference value;
Maintaining the polarity and value of the first digital value at the first time of the second digital signal relative to the second reference value;
Holding a polarity and a value of the second digital value at a second time after the first time of the second digital signal with respect to the second reference value;
The relationship between the polarity of the first digital value of the first digital signal and the polarity of the second digital value of the first digital signal and the first digital value of the second digital signal The relationship between the polarity and the polarity of the second digital value of the second digital signal, the polarity of the first digital value of the first digital signal, and the first digital value of the second digital signal A pattern divided based on the relationship between the polarity of the values or the relationship between the polarity of the second digital value of the first digital signal and the polarity of the second digital value of the second digital signal, or The value of the first digital value of the first digital signal and the second value of the first digital signal corresponding to the relationship between the pattern and the immediately preceding pattern. The value of the first digital value of the second digital signal, the value of the second digital value of the second digital signal, the first digital value of the first digital signal And the second digital value of the first digital signal, the first digital value of the second digital signal and the second digital signal of the second digital signal An arithmetic operation is performed on a difference between the first and second digital values, and an operation result is calculated as a phase difference between the first digital signal and the second digital signal between the first digital value and the second digital value. Supplying step ;
A method for detecting a phase difference of a digital signal. The operation corresponding to the above pattern is
A value of the first digital value of the first digital signal, a value of the first digital value of the first digital signal, and a value of the second digital value of the first digital signal. Excluding difference,
A value of the second digital value of the first digital signal; a value of the first digital value of the first digital signal; and a value of the second digital value of the first digital signal. Excluding difference,
A value of the first digital value of the second digital signal; a value of the first digital value of the second digital signal; and a value of the second digital value of the second digital signal. Excluding difference,
A value of the second digital value of the second digital signal; a value of the first digital value of the second digital signal; and a value of the second digital value of the second digital signal. Excluding difference ,
The method for detecting a phase difference of a digital signal according to claim 1 , which is performed based on

Images