JP2010218679A - Signal processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing apparatus capable of accurately generating signals without increasing sampling frequencies. <P>SOLUTION: The signal processing apparatus for generating signals on the basis of a plurality of signals in differential relationship or in phase relationship with respect to each other includes: a sampler 100 that repeatedly samples the plurality of signals in a prescribed order; and a processing circuit 200 that generates synthesized signals in phase or opposite phase with respect to the plurality of signals for each sampling timings by adding or subtracting sampling data of the plurality of signals with close sampling timings outputted from the sampler 100. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to digital signal processing technology applied to fields such as communication, measuring instruments, and servo control, and in particular, is used when sampling a plurality of differential or in-phase signals to generate a signal. The present invention relates to a signal processing apparatus.

  Conventionally, time division sampling using one A / D converter and a plurality of sample and hold circuits is generally performed as a method of sampling by converting a plurality of analog signals into digital signals. In the above time-division sampling method, since a plurality of input analog signals are digitally converted by a single A / D converter, variations due to analog elements are suppressed compared to the simultaneous sampling method using a plurality of A / D converters. In addition, the circuit scale can be reduced. In the time-division sampling method, a plurality of data are sampled by sequentially sampling A / D converted data by one of the sample and hold circuits performing a sample operation and the other sample and hold circuits performing a hold operation.

  As an apparatus using the time division sampling method, for example, there is an optical disk apparatus as described in Patent Document 1. FIG. 7 is a diagram showing the configuration of the optical disc apparatus 700 described in Patent Document 1.

  In the optical disc apparatus 700, an analog light reception signal from a pickup (not shown) is input to the input selection unit 701 as signals A to D. The input selection unit 701 switches the output signal in a time division manner based on control by the control unit 705. The output signal of the input selection unit 701 is offset adjusted by the offset adjustment unit 702, the gain is adjusted by the gain adjustment unit 703, and then A / D converted by the A / D converter 704. The A / D converted signals are respectively held by a plurality of sample and hold circuits 706 to 709. The servo signal processing unit 710 generates, for example, a focus error signal using all sampled and held values, and updates the calculated value of the focus error signal for each sampling period.

  FIG. 8 is a diagram showing the timing of sampling and calculation output by the optical disc apparatus 700. In FIG. In FIG. 8, (a) to (d) represent sampling timings of the signals A to D, and (e) represents an output signal of the servo signal processing unit 710. As shown in FIG. 8, in the A / D converter 704, the signal A is T1, the signal B is T2, the signal C is T3, and the signal D is T4, and each sampled data is sampled and held. The signals are held by circuits 706 to 709, respectively. The servo signal processing unit 710 generates and outputs a desired signal, for example, a focus error signal, using all sampling data up to T5 when the signal A is sampled next. As described above, in the optical disc apparatus 700, the output signal of the servo signal processing unit 710 is output every sampling period Ts.

JP 2002-298373 A

  However, when the signal generation is performed using the data sampled in time division after all the sampling of the plurality of signals is completed as in the optical disc apparatus described above, the sampling theorem indicates that the sampling frequency is ½ of the sampling frequency. Signal generation up to frequency was the limit. Further, when the sampling frequency is increased for high-speed signal generation, an increase in circuit scale, a performance limit of the A / D converter, and the like have been problems.

  The present invention has been made to solve the above-described problem, and performs sampling at all or part of the sampling timing by arbitrarily shifting sampling points of a plurality of signals each having a differential or in-phase relationship with each other. Accordingly, an object of the present invention is to provide a signal processing apparatus capable of generating a highly accurate signal without increasing the sampling frequency.

  In order to solve the above-described problem, a signal processing circuit according to claim 1 of the present invention is a signal processing device that generates a signal based on a plurality of signals that are differentially or in-phase with each other. Sampling in a predetermined order, and sampling data of the plurality of signals that are output from the sampling unit and have similar sampling timings are added or subtracted, respectively. And an arithmetic unit that generates a composite signal having a reverse phase at each sampling timing.

  According to a second aspect of the present invention, there is provided a signal processing circuit for generating a signal based on a plurality of signals having a differential or in-phase relationship with each other. A sampling unit that repeats sampling; an interpolation circuit that interpolates data at unsampled timing in the plurality of signals using a plurality of sampling data output from the sampling unit; and sampling timings of the plurality of signals And at every timing of the interpolation timing of the plurality of signals, the sampling data and the interpolation data output from the interpolation circuit are respectively added or subtracted, so that they are in phase or out of phase with the plurality of signals. And a calculation unit that generates a combined signal.

  A signal processing circuit according to a third aspect of the present invention is the signal processing device according to the first aspect, wherein the sampling unit is capable of arbitrarily setting signal amplitudes of a plurality of signals. Is further provided.

  A signal processing circuit according to a fourth aspect of the present invention is the signal processing device according to the first aspect, wherein the sampling unit includes an offset adjustment circuit capable of arbitrarily setting an offset amount of a plurality of signals. Furthermore, it is characterized by comprising.

  According to a fifth aspect of the present invention, there is provided the signal processing circuit according to the first aspect, wherein the arithmetic unit is capable of arbitrarily setting signal amplitudes of a plurality of signals. Is further provided.

  A signal processing circuit according to a sixth aspect of the present invention is the signal processing device according to the first aspect, wherein the calculation unit includes an offset adjustment circuit capable of arbitrarily setting an offset amount of a plurality of signals. Furthermore, it is characterized by comprising.

  The signal processing circuit according to claim 7 of the present invention is the signal processing device according to claim 1, wherein the arithmetic unit further includes an arithmetic selection unit capable of arbitrarily selecting a plurality of arithmetic methods. Features.

  The signal processing circuit according to an eighth aspect of the present invention is the signal processing device according to the second aspect, wherein the interpolation circuit includes a plurality of sampling data of a signal to be subjected to data interpolation among the plurality of signals. Is used to interpolate unsampled timing data of the signal to be interpolated.

  The signal processing circuit according to claim 9 of the present invention is the signal processing device according to claim 2, wherein the interpolation circuit includes a plurality of sampling data of a specific signal among the plurality of signals, and data interpolation. The sampling data of the signal that is the target of the interpolation is used to interpolate the unsampled timing data of the signal that is the target of the data interpolation.

  A signal processing circuit according to a tenth aspect of the present invention is the signal processing device according to the first aspect, wherein the sampling unit is capable of compensating a signal band of the plurality of signals at an arbitrary frequency. It further comprises a compensation circuit.

  According to the signal processing circuit of claim 1, in the signal processing device that generates signals based on a plurality of signals that are differentially or in phase with each other, each of the plurality of signals is sampled in a predetermined order. And a combined signal that is in phase with or out of phase with the plurality of signals by respectively adding or subtracting the sampling data of the plurality of signals that are output from the sampling unit and that have close sampling timing, Since a calculation unit that generates each sampling timing is provided, it is possible to generate a signal having a sampling frequency or higher and to generate a signal with high accuracy.

  According to the signal processing circuit of the second aspect, in the signal processing device that generates a signal based on a plurality of signals that are differentially or in phase with each other, each of the plurality of signals is sampled in a predetermined order. Using a plurality of sampling data output from the sampling unit, an interpolation circuit for interpolating unsampled timing data in the plurality of signals, a sampling timing of the plurality of signals, and the plurality of signals A combined signal that is in phase with or out of phase with the plurality of signals by adding or subtracting the sampling data and the interpolation data output from the interpolation circuit at every timing of the interpolation timing of the signal With a calculation unit that generates Data only in comparison with the case of performing signal generated using, enables more accurate signal generation.

  According to a signal processing circuit of a third aspect, in the signal processing device according to the first aspect, the sampling unit further includes a signal amplitude adjustment circuit capable of arbitrarily setting signal amplitudes of a plurality of signals. Therefore, it is possible to adjust the amplitude variation of a plurality of signals to a desired level, to effectively use the data bit width after the A / D converter, and to increase the scale of the arithmetic circuit Can be suppressed.

  According to a signal processing circuit of a fourth aspect, in the signal processing device according to the first aspect, the sampling unit further includes an offset adjustment circuit capable of arbitrarily setting an offset amount of a plurality of signals. As a result, it is possible to adjust the variation in the offset amount of a plurality of signals to a desired level, to effectively use the data bit width after A / D conversion, and to increase the scale of the arithmetic circuit Can be suppressed.

  According to a signal processing circuit of a fifth aspect, in the signal processing device according to the first aspect, the calculation unit further includes a signal amplitude adjustment circuit capable of arbitrarily setting signal amplitudes of a plurality of signals. Therefore, it is possible to adjust the amplitude variation of the plurality of signals to a desired level, to increase the calculation accuracy in the calculation unit, and to suppress an increase in the calculation circuit scale.

  According to a signal processing circuit of a sixth aspect, in the signal processing device according to the first aspect, the calculation unit further includes an offset adjustment circuit capable of arbitrarily setting an offset amount of the plurality of signals. As a result, it is possible to adjust the variation in the offset amount of the plurality of signals to a desired level, and it is possible to improve the calculation accuracy in the calculation unit and to suppress an increase in the scale of the calculation circuit. .

  According to the signal processing circuit of claim 7, in the signal processing device of claim 1, the arithmetic unit further includes an arithmetic selection unit capable of arbitrarily selecting a plurality of arithmetic methods. Calculation switching in a short time is possible.

  According to a signal processing circuit according to claim 8, in the signal processing device according to claim 2, the interpolation circuit uses a plurality of sampling data of a signal to be subjected to data interpolation among the plurality of signals. Since the data at the unsampled timing of the signal to be subjected to the data interpolation is interpolated, it is relatively easy to generate the interpolation signal by using only the sampling data of each signal itself for the data interpolation. Therefore, it is possible to generate a signal with higher accuracy than when signal generation is performed using only sampling data.

  According to a signal processing circuit according to claim 9, in the signal processing device according to claim 2, the interpolation circuit includes a plurality of sampling data of a specific signal among the plurality of signals, and a data interpolation target. The sampling data of the signal to be used is used to interpolate the unsampled timing data of the signal to be interpolated, so that an interpolated signal for signals other than that signal is generated immediately after sampling a certain signal. As compared with the case where signal generation is performed using only sampling data, more accurate signal generation is possible.

  According to a signal processing circuit according to claim 10 of the present invention, in the signal processing device according to claim 1, the sampling unit is a band capable of compensating the signal bands of the plurality of signals at an arbitrary frequency. Since the compensation circuit is further provided, it is possible to generate a signal with higher accuracy and less noise.

It is a block diagram of the signal processing apparatus which concerns on Embodiment 1 of this invention. It is a timing diagram of the signal processing of the signal processing apparatus according to the first embodiment of the present invention. It is a block diagram of the signal processing apparatus which concerns on Embodiment 2 of this invention. It is a timing diagram of the signal processing of the signal processing apparatus according to the second embodiment of the present invention. It is a timing diagram of the signal processing of the signal processing apparatus according to the third embodiment of the present invention. It is a block diagram of the signal processing apparatus which concerns on Embodiment 4 of this invention. It is a block diagram of the optical disk apparatus by the conventional time division sampling system. It is a timing diagram of the signal processing in the optical disk apparatus by the conventional time division sampling system.

(Embodiment 1)
FIG. 1 is a configuration diagram of a signal processing device according to the first embodiment.
The signal processing apparatus 300 according to the first embodiment performs an operation based on a sampling unit 100 that samples analog signals A, B, C, and D that are externally input, and a plurality of sampling data output from the sampling unit 100 An arithmetic circuit 200 that performs processing and generates a desired signal.

  The sampling unit 100 includes a first selection circuit 1, an amplifier (hereinafter referred to as “Amp”) 2, an A / D converter 3, a second selection circuit 4, a sampling control circuit 5, 1 to 4 registers 6 to 9, an amplitude adjustment circuit 10, and an offset adjustment circuit 11.

The first selection circuit 1 receives four analog signals A, B, C, and D that are differentially or in-phase with each other, and inputs one signal from these input signals A to D to the sampling control circuit 5. Based on the control, the selection is made in a predetermined order and at a predetermined timing and output. Amp2 adjusts the signal amplitude and the offset amount of the output signal of the first selection circuit 1. The A / D converter 3 converts the signal whose signal amplitude and offset amount are adjusted by Amp 2 into a digital signal. The sampling timing of the A / D converter 3 is arbitrarily set by the sampling control circuit 5. The second selection circuit 4 selects and outputs the output signal of the A / D converter 3 in a predetermined order and at a predetermined timing based on control by the sampling control circuit 5. The sampling control circuit 5 controls the timing of signal output in the first selection circuit 1 and the second selection circuit 4 and the order of signal selection, the control of the sampling timing in the A / D converter 3, and the first through first 4 controls the data holding / output timing of the registers 6-9. The first to fourth registers 6 to 9 hold sampling data output from the second selection circuit 4 for a certain period. The amplitude adjustment circuit 10 calculates an amplitude adjustment value for adjusting the amplitude of the input signals A to D using the sampling data held in the first to fourth registers 6 to 9. The offset adjustment circuit 12 calculates an offset adjustment value for adjusting the offset amount of the input signals A to D using the sampling data d1 to d4 held in the first to fourth registers 6 to 9. Is.
The arithmetic circuit 200 performs various calculations using the sampling data held in the first to fourth registers 6 to 9 of the sampling unit 100 to generate a desired signal.

  Next, the operation of the signal processing apparatus 300 according to the first embodiment will be described with reference to FIG. 1 and FIG. FIG. 2 is a diagram for explaining the operation timing of the signal processing apparatus 300 according to the first embodiment. 2, (a) to (d) represent the waveforms of signals A to D, and (e) represents the output signal of the arithmetic circuit 200. T1 to T8 represent sampling points of the signals A to D, respectively, and a1 to d2 represent sampling data of the signals A to D, respectively.

  The signals A, B, C, and D that are differentially or in-phase with each other are input to the first selection circuit 1 and then differ in a predetermined order under the control of the sampling control circuit 5. Output to Amp2 at timing. As shown in FIG. 2, in the first embodiment, the sampling control circuit 5 controls the first selection circuit 1 so that sampling is performed in the order of signal A, signal B, signal C, and signal D. .

  The signals A to D sequentially output from the first selection circuit 1 are input to the A / D converter 3 after their signal amplitude and offset amount are adjusted by Amp2, and are sequentially sampled at the sampling period Ts. . As shown in FIG. 2, the signal A is sampled at T1, the signal B is sampled at T2, the signal C is sampled at T3, and the signal D is sampled at T4. Also after T5, the signals A, B, C, and D are sampled at different timings.

  Here, the sampling point of each signal within the sampling period Ts, that is, the time (T2-T1) from the sampling of the signal A to the sampling of the signal B in FIG. (T3-T2), the time from sampling the signal C to sampling the signal D (T4-T3), and the time from sampling the signal D to sampling the signal A (T3-T2) The sampling period Ts- (T4-T1)) can be arbitrarily set by the sampling control circuit 5, and the set sampling timing is given to the first selection circuit 1 and the second selection circuit 4. Is set. The signal sampling order is not limited to A, B, C, and D as shown in FIG.

  The sampling data of the signals A to D is stored in the first to fourth registers 6 to 9 corresponding to the respective input signals A to D by the second selection means 4 under the control of the sampling control circuit 5. . The sampling data stored in the first to fourth registers 6 to 9 is held in each register until the corresponding signal is sampled next and new sampling data is output. For example, the data a1 sampled at T1 is held in the register 1 until T5. Similarly, for example, data d1 sampled at T4 is held in the register 4 until T8. The data stored in the registers 6 to 9 is output to the amplitude adjustment circuit 10, the offset adjustment circuit 11, and the arithmetic circuit 200 at a predetermined timing under the control of the sampling control circuit 5.

  The amplitude adjustment circuit 10 detects the amplitudes of the signals A to D in a certain period using the sampling data an to dn, and calculates an adjustment value so that the amplitudes of the signals A to D become arbitrary amplitudes. . The amplitude adjustment value is set to Amp2 at the timing given by the sampling control circuit 5. As described above, by adjusting the amplitude of the input signals A to D using the amplitude adjustment circuit 10, even if the amplitude of each of the input signals A to D varies, the range of the A / D converter 3. It is possible to make adjustment within the range, and it is possible to effectively use the in-circuit bit width for the digital data after A / D conversion, thereby improving the calculation accuracy. Further, by supplying the amplitude adjustment value for each of the input signals A to D to Amp2 at the timing given by the sampling control circuit 5, the amplitude of a plurality of signals can be adjusted by one Amp2, and the circuit scale is increased. The increase can be suppressed.

  In the offset adjustment circuit 11, the amount of offset from the reference potential of each signal A to D in a certain period is calculated as an adjustment value using the sampling data an to dn. The offset adjustment value is set to Amp2 at the timing given by the sampling control circuit 5. As described above, by adjusting the offset amount of the input signals A to D using the offset adjustment circuit 11, even if the offset amount of the input signals A to D varies, the range of the A / D converter 3. It is possible to make adjustment within the range, and it is possible to effectively use the in-circuit bit width for the digital data after A / D conversion, thereby improving the calculation accuracy. Further, by supplying the offset adjustment values for the input signals A to D to Amp2 at the timing given by the sampling control circuit 5, the offset adjustment of a plurality of signals can be performed with one Amp2, and the circuit scale Can be suppressed. The order of the amplitude adjustment and the offset adjustment described above does not matter.

  The arithmetic circuit 200 uses the sampling data an to dn (n = 1, 2,...) To perform a predetermined calculation at a speed higher than the sampling period Ts. In the first embodiment, calculation is performed for each sampling timing of the input signals A to D, and as a result, the calculation output is updated for each sampling point of the signals A to D. Specifically, when the arithmetic expression of the arithmetic circuit 200 in the first embodiment is given by A−B−C + D, in FIG. 2, at T5 which is the sampling point of the signal A, a2−b1−c1 + d1. The output signal is obtained, and at T6, which is the sampling point of the signal B, the output signal is obtained by a2-b2-c1 + d1, and thereafter, the operation output value is sequentially updated at each sampling point of the signals A to D. Is done.

  As described above, the signal processing device 300 according to the first embodiment samples each signal by arbitrarily shifting the sampling points of the plurality of signals A to D that are differentially or in-phase with each other. Since arithmetic processing is performed at all timings of the sampling timings of the input signals A to D, an output signal having a frequency higher than the sampling frequency can be generated with high accuracy.

  In the first embodiment, the description has been given using four input signals A to D. However, this is an example, and even when there are a plurality of signal inputs, the number of registers depends on the number of signal inputs. And by appropriately changing the control of the sampling control circuit 5, the same operations and effects as in the first embodiment can be obtained.

  Further, the sampling frequencies of the signals A to D are not necessarily the same, and if the sampling frequencies of the signals are in a relationship of n times, the same action as in the first embodiment. , You can get the effect. Further, the arithmetic device 200 may perform the operation at a part of the sampling timing of the signals A to D.

  In the first embodiment, the amplitude adjustment and offset adjustment of the input signals A to D are performed by feedback control by the amplitude adjustment circuit 10 and the offset adjustment circuit 11 provided in the sampling unit 100. The adjustment circuit 10 and the offset adjustment circuit 11 are provided in the arithmetic device 200, and the first to the first adjustments are performed using the amplitude adjustment value output from the amplitude adjustment circuit 10 and the offset adjustment value output from the offset adjustment circuit 11. The amplitude adjustment and offset adjustment of the input signals A to D may be performed by applying predetermined correction to the sampling data output from the registers 6 to 9 of No. 4.

(Embodiment 2)
FIG. 3 is a configuration diagram of the signal processing apparatus according to the second embodiment. The signal processing device 301 according to the second embodiment of the present invention includes an interpolation circuit 12 and a register 13 in the subsequent stage of the first to fourth registers 6 to 9 in the signal processing device 300 according to the first embodiment. 14, 15, and 16 are provided, and the other components are the same as those in the first embodiment, and thus description thereof is omitted.

  The interpolation circuit 12 uses the sampling data stored in the first to fourth registers 6 to 9 to generate interpolation data between sampling periods for each input signal. Interpolation timing in the interpolation circuit 12 is controlled by the sampling control circuit 5. The registers 13, 14, 15, and 16 hold the respective interpolation data generated for each of the input signals A to D.

  Next, the operation of the signal processing device 301 according to the second embodiment will be described with reference to FIG. The operations of the first selection circuit 1, Amp2, A / D conversion circuit 3, second selection circuit 4, and first to fourth registers 6 to 9 are the same as those in the first embodiment. Therefore, the description thereof is omitted.

  FIG. 4 is a diagram for explaining the operation timing of the signal processing device 301. 4, (a) to (d) represent the waveforms of the signals A to D, and (e) represents the output signal of the arithmetic circuit 200. T1 to T9 represent sampling points of the signals A to D, respectively, and a1 to d2 represent sampling data of the signals A to D, respectively.

  When the signals A, B, C, and D are sampled at T1 to T4, sampling data a1, b1, c1, and d1 are sequentially stored in the first to fourth registers 6 to 9, respectively. Then, when the signal A is sampled at T5 and stored in the register 6, the interpolation circuit 12 uses the sampling data a1 at T1 of the signal A and the sampling data a2 at T5 to obtain data between sampling points. Is interpolated. That is, interpolation data a1 ', a1 ", and a1" "that are T2, T3, and T4 data having no sampling data are generated from the sampling data a1 and a2 based on an interpolation method such as linear interpolation. These interpolation data are output to the register 13 at a predetermined timing under the control of the sampling control circuit 5. Similarly, for the signals B to D, the data between the sampling points is interpolated from the sampling data of two adjacent points, and is output to the registers 13 to 16.

  The arithmetic circuit 200 performs a desired operation using the data stored in the registers 13 to 16. For example, when the data c2 of the signal C is sampled at T7 in FIG. 4, the interpolation data c1 ′ at T4 is generated, and the interpolation data a1 ′ ″ of the signal A and the interpolation of the signal B are stored in the registers 13 to 16. Data b1 ″, interpolation data c1 ′ of signal C, and sampling data d1 of signal D are stored. At T7, the arithmetic circuit 200 uses these a1 "", b1 ", c1 ', d1 and outputs the calculation result at the time T4. Similarly, since the interpolation data d1 ′ of the signal D is generated at T8, the sampling data a2 of the signal A, the interpolation data b1 ′ ″ of the signal B, the interpolation data c1 ″ of the signal C, and the signal at T8. Using the sampling data d1 ′ of D, the calculation result at time T5 is output. Similarly, the calculation result is output using the interpolation data between the sampling points of the signals A to D.

  As described above, in the second embodiment, the sampling data between the sampling points of each signal is interpolated by the interpolation circuit 12, and calculation for signal generation is performed using the latest sampling data including the interpolation data. Therefore, it is possible to reduce an error from actual data due to sampling, and it is possible to generate a signal with higher accuracy. In particular, when the generated signal is considerably slow with respect to the sampling period and the output signal can be sufficiently absorbed even if it is delayed by one sample period, it is effective as a means for improving the generated signal accuracy.

  In the second embodiment, the interpolation data for each sampling timing of each signal is calculated and the arithmetic circuit 10 performs the arithmetic processing. However, it is necessary to calculate the interpolation data for every other signal sampling timing. Rather, by performing arithmetic processing using the latest sampling data stored in the registers 13 to 16, it is possible to generate a highly accurate signal using interpolation data.

(Embodiment 3)
In the third embodiment, a correction signal for interpolating another input signal is obtained from a plurality of sampling data of a certain input signal, and the other signal is calculated based on the correction signal and the sampling data of the other input signal. Data interpolation of the input signal is performed. In other words, since the input signals A to D are in a differential or in-phase relationship, the sampling data of each signal can be used as a correction signal for other signals. By interpolating data, it is possible to generate a signal with higher accuracy. Thus, the third embodiment differs from the second embodiment in the interpolation method, and the circuit configuration is the same as that shown in FIG.

FIG. 5 is a timing diagram of signal processing according to the third embodiment. Since the signal sampling method is the same as that in the first embodiment, the description thereof is omitted.
When the signals A, B, C, and D are sampled at T1 to T4, respectively, and then the signal A is sampled at T5, the interpolation circuit 12 performs sampling data a1 at T1 of the signal A and sampling data a2 at T5. Then, a correction signal αa for the signals B to D is generated. The correction signal αa can be obtained from a difference value between a1 and a2, or an inclination between a1 and a2. Then, the signal B is interpolated based on the latest sampling data b1 of the signal B and the correction signal αa to obtain the interpolation data ab2. Similarly, the signals C and D are also interpolated based on the latest sampling data c1 and d1 stored in the registers 8 and 9 and the correction signal αa to obtain the interpolation data ac2 and ad2. These interpolation data are stored in the registers 13-16.

  The arithmetic circuit 200 uses the data a2, ab2, ac2, ad2 stored in the registers 13 to 16 to output the arithmetic result at the time point T5. At T6, the signal B is sampled, and a correction signal αb for the signals A, C, and D is generated from the sampling data b1 at T2 of the signal B and the sampling data b2 at T6. As described above, the signals A, C, and D are interpolated based on the latest sampling data of the signals A, C, and D and the correction signal αb, and the output signal from the arithmetic circuit 200 is generated using the generated interpolation data. Is generated. In calculating the correction signal αk (k = a, b, c, d), the signal amplitude adjustment circuit 10 and the offset adjustment circuit 11 are used to make the signal amplitudes and offset amounts of the signals A to D the same. By adjusting, the correction signal αk can be calculated with higher accuracy.

  Thus, the signal processing apparatus according to the third embodiment obtains a correction signal for interpolating another signal from the sampling data of a certain input signal, and the latest sampling data of the correction signal and the other input signal Thus, the interpolation data of the other input signal is obtained, and the arithmetic circuit 200 performs the signal generation calculation using these interpolation data, so that the phase of the generated signal is not delayed and the value close to the actual data is obtained. Accurate signal generation is possible.

(Embodiment 4)
The fourth embodiment is an example in which the signal processing device 300 according to the first embodiment is applied to an optical disk device. FIG. 6 is a diagram illustrating a schematic configuration of the signal processing device 302 according to the fourth embodiment. In FIG. 6, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 6, input signals A to D are light detection signals received by a light receiving element in an optical pickup (not shown). The light receiving element is composed of a multi-split light detector, and a light detection signal as an output thereof is a plurality of differential or in-phase signals. Reference numerals 17 to 20 and 202 denote low-pass filters, and 203 denotes a binarization circuit. The arithmetic circuit 201 according to the fourth embodiment includes selection circuits 210 and 211 therein, and switches the arithmetic processing according to the input of the selection signal S. In the following, for the sake of simplification of explanation, a four-divided light detector will be described as an example, but the same effect can be obtained even if it is not a four-divided light detector.

Next, the operation of the signal processing device 302 according to the fourth embodiment will be described.
Since the photodetection signals A to D are very fine signals, they are easily affected by external factors such as noise, and a necessary signal band is limited. Therefore, the signal is input to the first selection circuit 1 through the low-pass filters 17 to 20 for band compensation. As in the first embodiment, under the control of the sampling control circuit 5, the light detection signals A to D are output from the first selection circuit 1 at different timings and input to Amp2. The light detection signals A to D have variations in signal amplitude and offset amount due to variations in pickup, but the signal amplitude adjustment circuit 10 that can arbitrarily set the amplitude and the offset amount of each signal are arbitrary. By the feedback control by the offset adjustment circuit 11 that can be set to, variations in the light detection signals A to D can be suppressed, and the data bit width after A / D conversion can be used effectively.

  The respective photodetection signals A to D A / D converted by the A / D converter 3 are synchronized with the A / D conversion by the second selection circuit 4 under the control of the sampling control circuit 5. The signal A is stored in the first register 6, the signal D is stored in the second register 7, the signal B is stored in the third register 8, and the signal C is stored in the fourth register 9.

The arithmetic circuit 201 uses the photodetection signals A to D stored in the first to fourth registers 6 to 9 to perform calculation at a timing faster than the sampling period. In the fourth embodiment, when the track cross signal is generated, the outputs of the selection circuits 210 and 211 are switched according to the selection signal S, and the calculation is performed by either the Push-Pull method or the 3 Beam method. For example, when the selection signal S is 0, arithmetic processing is performed by the 3 Beam method (AB), and when the selection signal S is 1, arithmetic processing is performed by the Push-Pull method ((A + D)-(B + C)). .
The output of the arithmetic circuit 201 passes through the low-frequency compensation filter 202 for band compensation of the output signal, is binarized by the binarization circuit 203, and is output as a track cross signal.

  As described above, according to the signal processing device 302 according to the fourth embodiment, the track cross signal used for the tracking control of the optical disc device can be generated with high accuracy without increasing the sampling frequency.

  The signal processing apparatus according to the present invention is useful in that a high-accuracy signal can be generated without increasing the sampling frequency when generating a digital signal from a plurality of differential or in-phase analog signals. . In particular, it can be applied to uses such as tracking control of an optical disc apparatus.

1 First selection circuit 2 Amp
3 A / D Converter 4 Second Selection Circuit 5 Sampling Control Circuit 6, 7, 8, 9 Register 10 Amplitude Adjustment Circuit 11 Offset Adjustment Circuit 12 Interpolation Circuit 13, 14, 15, 16 Register 17, 18, 19, 20 Low-frequency compensation filter 100, 101, 102 Sampling unit 200, 201 Arithmetic circuit 202 Low-frequency compensation filter 203 Binary circuit 701 Input selection unit 702 Offset adjustment unit 703 Gain adjustment unit 704 A / D converter 705 Control unit 706, 707 , 708, 709 Sample hold circuit 710 Servo signal processing circuit

Claims (10)

In a signal processing apparatus that performs signal generation based on a plurality of signals that are differentially or in-phase with each other,
A sampling unit that repeats sampling each of the plurality of signals in a predetermined order; and
Generates a combined signal that is in-phase with or out of phase with each of the plurality of signals by adding or subtracting the sampling data of the plurality of signals that are output from the sampling unit and have similar sampling timings, at each sampling timing. An arithmetic unit to perform,
A signal processing apparatus comprising: In a signal processing apparatus that performs signal generation based on a plurality of signals that are differentially or in-phase with each other,
A sampling unit that repeats sampling each of the plurality of signals in a predetermined order; and
An interpolation circuit for interpolating unsampled timing data in the plurality of signals using a plurality of sampling data output from the sampling unit;
The sampling data and the interpolation data output from the interpolation circuit are respectively added or subtracted for each of the sampling timing of the plurality of signals and the interpolation timing of the plurality of signals, thereby subtracting the plurality of signals. A calculation unit that generates a composite signal that is in phase or in phase with the signal;
A signal processing apparatus comprising: The signal processing device according to claim 1,
The sampling unit further includes a signal amplitude adjustment circuit capable of arbitrarily setting the signal amplitude of a plurality of signals.
A signal processing apparatus. The signal processing device according to claim 1,
The sampling unit further includes an offset adjustment circuit capable of arbitrarily setting an offset amount of a plurality of signals.
A signal processing apparatus. The signal processing device according to claim 1,
The arithmetic unit further includes a signal amplitude adjustment circuit capable of arbitrarily setting the signal amplitude of a plurality of signals.
A signal processing apparatus. The signal processing device according to claim 1,
The arithmetic unit further includes an offset adjustment circuit capable of arbitrarily setting an offset amount of a plurality of signals.
A signal processing apparatus. The signal processing device according to claim 1,
The calculation unit further includes a calculation selection unit capable of arbitrarily selecting a plurality of calculation methods.
A signal processing apparatus. The signal processing device according to claim 2,
The interpolation circuit interpolates unsampled timing data of the data interpolation target signal using a plurality of sampling data of the data interpolation target signal among the plurality of signals.
A signal processing apparatus. The signal processing device according to claim 2,
The interpolation circuit uses a plurality of sampling data of a specific signal among the plurality of signals and sampling data of a signal to be subjected to data interpolation, and the signal to be subjected to the data interpolation is not sampled. Interpolate timing data,
A signal processing apparatus. The signal processing device according to claim 1,
The sampling unit further includes a band compensation circuit capable of compensating a signal band of the plurality of signals at an arbitrary frequency.
A signal processing apparatus.

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