JP4458906B2 - Semiconductor device - Google Patents

Description

  The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a structure for cooling or radiating heat generated from a semiconductor element.

  2. Description of the Related Art Conventionally, a technique for efficiently radiating heat generated from a semiconductor integrated circuit using a material having high thermal conductivity (for example, a metal such as copper) called a heat spreader is known. In this case, a plate-like heat spreader is sealed so as to come into contact with the back surface of the semiconductor chip housed in an LSI (large scale integration) package. Thereby, the heat generated in the semiconductor chip is radiated to the outside of the package via the heat spreader.

  In the case of a semiconductor integrated circuit that generates a larger amount of heat, a metal part (such as aluminum or copper) that has a fin shape for heat dissipation called a heat sink on the backside of a ceramic chip or flip chip mounted semiconductor chip. Are often made of a high-performance material), and heat radiation by air cooling or liquid cooling is performed. However, when package sealing is performed using a plastic mold resin, heat dissipation by natural air cooling in a state of being mounted on a printed board is a prerequisite. In particular, in the case of a microprocessor for PC (personal computer) or EWS (engineering workstation), since heat generation is large, either a forced air cooling in which a heat sink and an electric fan are combined or a cooling method by flowing a liquid refrigerant through the heat sink Is adopted.

The power consumption in the chip of the semiconductor integrated circuit is the sum of (1) due to transient through current, (2) due to charge / discharge of load capacitance, and (3) due to transistor junction leakage and subthreshold current. You can think of it. Of these, (1) and (2) increase in proportion to the operating frequency of the semiconductor device, and (3) tends to increase as the transistor becomes finer. The generation of heat is mainly due to Joule heat, and is proportional to the product of the square of the current I and the resistance R (Q∝I ² × R).

  For this reason, inside the semiconductor chip, specific parts such as IO (input / output) pads, bus buffers, and multipliers through which a large current flows are sources of heat, and high temperature parts (hot spots) It has become. When heat conduction in the semiconductor chip is considered, heat generated from these hot spots is diffused to other parts in the chip.

  For example, Japanese Laid-Open Patent Publication No. 2000-306998 (Patent Document 1), Japanese Laid-Open Patent Publication No. 11-17072 (Patent Document 2), Japanese Laid-Open Patent Publication No. 7-22547 (Patent Document 1) Patent Document 3), Japanese Patent Application Laid-Open No. 2001-291793 (Patent Document 4), Japanese Patent Application Laid-Open No. 8-12592 (Patent Document 5), Japanese Patent Application Laid-Open No. 10-199882 (Patent Document 6), and Japanese Patent Application Laid-Open No. 2000-243826. Japanese Patent Laid-Open No. 8-222700 (Patent Document 8), Japanese Patent Laid-Open No. 2003-258165 (Patent Document 9), Japanese Patent Laid-Open No. 5-166849 (Patent Document 10), Japanese Patent Laid-Open No. 8- No. 274226 (Patent Document 11), Japanese Patent Application Laid-Open No. 2002-289552 (Patent Document 12), Japanese Patent Application Laid-Open No. 2003-188342 (Patent Document 13) and It disclosed in JP-A 9-283697 (Patent Document 14).

Further, Non-Patent Document 1 below discloses a semiconductor device provided with a heat sink made of silicon material separately from the chip for the purpose of cooling the integrated circuit chip. The heat sink is formed with a microchannel for passing and circulating the refrigerant.
JP 2000-306998 A JP-A-11-17072 Japanese Patent Laid-Open No. 7-22547 JP 2001-291793 A JP-A-8-125092 JP-A-10-199882 JP 2000-243826 A JP-A-8-222700 JP 2003-258165 A Japanese Patent Laid-Open No. 5-166849 JP-A-8-274226 JP 2002-289552 A JP 2003-188342 A Japanese Patent Laid-Open No. 9-283697 Ken Goodson, Thermal Management of Advanced Electronic Systems, ISSCC 2003 Workshop

  The main heat dissipation paths from the semiconductor integrated circuit formed on the semiconductor chip include a path that dissipates heat from the back surface of the chip through the heat spreader by heat conduction and a path that dissipates heat from the chip to the mounting substrate through the terminals. Exists. In the case of using wire bonding, heat is radiated through the terminals by transferring heat from the package terminals to the mounting substrate through the lead frames and bumps through the bonding wires. In the case of a flip chip type semiconductor chip, metal bumps such as solder are formed on the electrode pads of the chip, and the chip is directly connected to the mounting substrate with the metal bumps sandwiched therebetween. For this reason, heat from the semiconductor chip is directly transmitted from the metal bumps to the mounting substrate, and heat is radiated.

  In general, electrode pads and bonding pads formed on the surface of a semiconductor chip are arranged at the periphery of the chip. For this reason, it is necessary to efficiently transmit the heat generated in the central portion of the semiconductor chip to these pads and dissipate heat. However, in a state-of-the-art microprocessor and system LSI, the chip area is further increased due to high integration, and heat dissipation toward the periphery of the chip is gradually becoming difficult.

  In addition, when local heat is generated inside the semiconductor chip and the heat is not sufficiently dissipated, the semiconductor integrated circuit may be thermally destroyed or the performance of the transistor may be deteriorated. Furthermore, in recent years, the situation where the upper limit of the operating frequency and integration degree of a semiconductor chip is determined by power consumption is becoming a reality, and it is strongly desired to solve these problems related to heat dissipation of the semiconductor chip.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problems, and to provide a semiconductor device that can efficiently cool a generated semiconductor element and can quickly dissipate heat transmitted from the semiconductor element to the outside.

A semiconductor device according to the present invention includes a semiconductor substrate having a main surface, a semiconductor element formed on the main surface of the semiconductor substrate, and an interlayer insulation formed on the main surface of the semiconductor substrate so as to cover the semiconductor element A film, and a cooling path formed in the interlayer insulating film for flowing a cooling fluid. The cooling path is formed so as to circulate inside the interlayer insulating film. The cooling path includes one end to which the cooling fluid is supplied and the other end from which the cooling fluid is discharged. The semiconductor device further includes a multilayer metal wiring layer formed inside the interlayer insulating film. The cooling path is constituted by a groove formed by patterning a multilayer metal wiring layer.

  According to the present invention, it is possible to provide a semiconductor device that efficiently cools a semiconductor element that has generated heat and quickly dissipates heat transmitted from the semiconductor element to the outside.

  Embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
1 is a perspective view showing a semiconductor device according to Embodiment 1 of the present invention. Referring to FIG. 1, a semiconductor device is formed on a semiconductor substrate 1 having a main surface 1a, a semiconductor element (not shown) formed on main surface 1a that generates heat when driven, and main surface 1a. And an interlayer insulating film 2 covering a semiconductor element (not shown). A cooling path 3 is formed inside the interlayer insulating film 2. Cooling path 3 has one end 4 and the other end 5 that are opened at different positions on top surface 2 a of interlayer insulating film 2. Cooling path 3 extends from one end 4 toward the other end 5 so as to pass through the vicinity of the semiconductor element formed on main surface 1a.

  The semiconductor substrate 1 is formed from, for example, a silicon substrate. The semiconductor element (not shown) is typically a variety of transistor elements, but is not limited thereto, and may be any element that uses a semiconductor. The interlayer insulating film 2 is formed of, for example, a silicon oxide film, PSG (phosphosilicate glass), BSG (borosilicate glass), BPSG (borophosphosilicate glass), TEOS (tetra etyle orthosilicate), SOG (spin on glass), and the like. ing. Further, a low dielectric constant material (Low-k material) may be used as the interlayer insulating film 2.

  A liquid or gas (cooling fluid) for cooling the semiconductor element flows from the one end 4 and is collected from the other end 5 to the cooling path 3. Examples of the gas supplied to the cooling path 3 include nitrogen gas, Freon gas, and inert gases such as helium and argon. Moreover, when the inner wall which comprises the cooling path 3 is coat | covered with the passivation film and the countermeasure with respect to oxidation is fully taken, dry air can also be used. Water (pure water) or chlorofluorocarbon can be used as the liquid.

  FIG. 2 is a perspective view showing a semiconductor package provided with the semiconductor device shown in FIG. In the drawing, in order to show the inside of the semiconductor package, a part is drawn through.

  Referring to FIG. 2, a semiconductor package 20 covers a semiconductor chip 10 constituted by the semiconductor device shown in FIG. 1, a heat spreader (heat sink) 12, a pump chip 13 described in detail later, and these members. Package resin 11. The heat spreader 12 is made of, for example, copper, iron-nickel alloy, solder, or the like.

  Inside the package resin 11, a cooling path 14 having both ends connected to one end 4 and the other end 5 of the cooling path 3 provided in the semiconductor chip 10 is formed. In the middle of the path of the cooling path 14, there is provided a portion that is positioned relatively closer to the other end 5 and that changes its direction at every predetermined distance. A heat spreader 12 is disposed in the vicinity of the portion. A pump chip 13 is provided in the middle of the cooling path 14 so as to be positioned relatively closer to the one end 4.

  FIG. 3 is a cross-sectional view showing the structure of the pump chip in FIG. Referring to FIG. 3, the pump chip 13 includes a pump structure fabricated on a silicon chip by micromachine technology. The pump structure includes a valve cylinder 24 and a valve portion 26 including a valve piston 25 disposed in the valve cylinder 24, and a pump portion including a pump cylinder 21 and a pump piston 22 disposed in the pump cylinder 21. 23. The valve cylinder 24 is connected by a flow path 28 to the cooling path 14 extending from the other end 5 side. The valve cylinder 24 and the pump cylinder 21 are connected to each other by a flow path 27. The pump cylinder 21 is connected to the cooling path 14 extending from the one end 4 side by a flow path 29.

  With reference to FIGS. 1 to 3, the pump piston 22 and the valve piston 25 are reciprocated with a predetermined phase difference by using an electrostatic actuator or the like using an electrostatic force between the electrodes. A cooling fluid is circulated through the cooling path 3 provided.

  The cooling fluid supplied from the pump chip 13 to the one end 4 of the cooling path 3 flows through the cooling path 3 provided in the semiconductor chip 10. At this time, the cooling fluid takes heat generated from the semiconductor element formed on the main surface 1a, and is then recovered to the other end 5 side. The recovered cooling fluid releases heat to the heat spreader 12 when passing through the vicinity of the heat spreader 12. The heat is radiated to the outside of the semiconductor package 20 through the package resin 11.

  The means for circulating the cooling fluid is not limited to the mechanism shown in FIG. 2. For example, a tube through which air / liquid cooling fluid is directly connected is connected to the package resin 11, and the tube and the outside are connected to the outside. A mechanism that connects to the provided pump may be used. However, as shown in FIG. 2, if the entire cooling system including the pump chip 13 as well as the heat spreader 12 is sealed in the package resin 11, the semiconductor chip 20 can be miniaturized and the semiconductor chip 10 can be dissipated. It can be performed efficiently.

  A semiconductor device according to a first embodiment of the present invention includes a semiconductor substrate 1 having a main surface 1a, an interlayer insulating film 2 formed on main surface 1a and covering a semiconductor element provided on main surface 1a, and an interlayer insulating film 2 and a cooling path 3 as a first cooling path through which a cooling fluid flows. The cooling path 3 is formed so as to circulate inside the interlayer insulating film 2. The cooling path 3 includes one end 4 to which a cooling fluid is supplied and the other end 5 to which the cooling fluid is discharged.

  A semiconductor package 20 as a semiconductor device includes a semiconductor chip 10 including a semiconductor substrate 1, an interlayer insulating film 2 and a cooling path 3, a package resin 11 as a resin member formed so as to cover the semiconductor chip 10, and a package resin 11. A pump chip 13 serving as a pump unit provided inside and a heat spreader 12 serving as a heat radiating unit made of a metal material are provided. The pump chip 13 is connected to one end 4 and the other end 5 to circulate a cooling fluid in the cooling path 3. The heat spreader 12 radiates the heat of the cooling fluid discharged from the other end 5.

  4 to 7 are cross-sectional views showing respective steps of a method for manufacturing a cooling path in an interlayer insulating film. The cooling path 3 having the tunnel structure shown in FIG. 1 is a layered structure of an interlayer insulating film and a metal wiring layer deposited on the semiconductor substrate 1 by a semiconductor process, and removes part of the interlayer insulating film later. Can be produced. This manufacturing method will be described below with reference to FIGS.

  Referring to FIG. 4, similar to a normal semiconductor process, an interlayer insulating film 31p and a metal wiring layer 32p are formed on main surface 1a of semiconductor substrate 1 by using a chemical vapor deposition (CVD) method and a sputtering method, respectively. Are sequentially formed. Further, an interlayer insulating film 31q is formed so as to cover the metal wiring layer 32p. Referring to FIG. 5, metal interconnection layer 32q including metal plugs 35m and 35n reaching metal interconnection layer 32p is formed on interlayer insulating film 31q. At this time, the interlayer insulating film 33 remains between the metal plug 35m and the metal plug 35n. Metal interconnection layer 32q is patterned to form grooves 34m and 34n at positions spaced apart from each other.

  Referring to FIG. 6, interlayer insulating film 31r filling trenches 34m and 34n is formed on metal wiring layer 32q. After planarizing the interlayer insulating film 31r by a CMP (chemical mechanical polishing) step, a metal wiring layer having metal plugs 35m and 35n reaching the metal wiring layer 32q on the interlayer insulating film 31r, as in the step shown in FIG. 32r is formed. The metal wiring layer 32r is patterned, and grooves 34m and 34n are formed again at positions spaced apart from each other.

  Referring to FIG. 7, the process shown in FIG. 6 is repeated, and interlayer insulating film 31s and metal wiring layer 32s having a predetermined shape are sequentially formed on interlayer insulating film 31r. Thereafter, by performing wet etching using hydrofluoric acid (HF), the interlayer insulating film 33 left between the metal plug 35m and the metal plug 35n is removed. Through the above steps, the cooling path 37 having a tunnel structure can be produced in the laminated structure of the interlayer insulating film and the metal wiring layer.

  4 to 7, the description has been given of the case where the cooling path is formed in a laminated structure of an interlayer insulating film and a metal wiring layer. However, the present invention is not limited to this. For example, an interlayer insulating film formed by a CVD method and By applying the same manufacturing method to the laminated structure with the silicon film, a cooling path for flowing a cooling fluid can be formed.

  FIG. 8 is a perspective view showing a modification of the semiconductor device shown in FIG. In the drawing, a cross section of the semiconductor device is shown. Referring to FIG. 8, in this modification, a via hole 41 is formed as a cooling path shown in FIG. 1 from the top surface 2 a side of the interlayer insulating film 2 to the back surface 1 b side of the semiconductor substrate 1. Via hole 41 is formed so that the area of a cross section cut along a plane parallel to main surface 1a decreases as it goes from top surface 2a to back surface 1b.

  FIG. 9 is a perspective view showing another modification of the semiconductor device shown in FIG. In the drawing, a cross section of the semiconductor device is shown. Referring to FIG. 9, in the present modification, a via hole 42 is formed as a cooling path shown in FIG. 1 from the top surface 2 a side of the interlayer insulating film 2 to the back surface 1 b side of the semiconductor substrate 1. Via hole 42 is formed such that the area of a cross section cut along a plane parallel to main surface 1a increases as it goes from top surface 2a to back surface 1b. Although not shown in FIGS. 8 and 9, in these modified examples, the flow path for circulating and passing the cooling fluid extending from the via holes 41 and 42 is provided on the back surface 1 b side of the semiconductor substrate 1. It is comprised by the package resin to cover.

  According to the semiconductor device configured as described above, by flowing the cooling fluid through the provided cooling path, the heat generated from the semiconductor element on the main surface 1a can be efficiently radiated to the outside of the semiconductor device. Thereby, a semiconductor element can be protected from the influence of heat and desired semiconductor characteristics can be obtained. Further, the upper limit of the operating frequency of the semiconductor chip and the processing performance of the circuit as determined from the temperature rise due to heat generation can be reduced, and a higher performance semiconductor integrated circuit can be realized.

  In addition, by forming the cooling path 3 inside the interlayer insulating film 2, the cooling path can be arranged in a narrow region. Thereby, it becomes easy to provide the cooling path 3 in the vicinity of the semiconductor element which is a heating element. The cooling path 3 has one end 4 and the other end 5 to which a cooling fluid is supplied and recovered. The cooling path 3 is located between the one end 4 and the other end 5 inside the package resin 11. A heat spreader 12 that dissipates heat from the cooling fluid is disposed. For this reason, the cooling fluid whose temperature has been lowered is successively supplied to the cooling path 3. Thereby, more efficient heat dissipation can be performed.

(Embodiment 2)
FIG. 10 is a sectional view showing a part of the semiconductor device according to the second embodiment of the present invention. The semiconductor device in this embodiment further includes a cooling structure described with reference to FIG. 10 in addition to the cooling structure included in the semiconductor device described in Embodiment 1. In the figure, the same or corresponding members are denoted by the same reference numerals as compared with the semiconductor device described in the first embodiment.

  Referring to FIG. 10, transistor element 45 as a semiconductor element is formed on main surface 1 a of semiconductor substrate 1. On the main surface 1 a, the interlayer insulating film 2 is deposited in multiple layers so as to cover the transistor element 45. In the interlayer insulating film 2, a wiring 43 that is connected to the transistor element 45 and actually functions as an electric signal wiring or a power supply wiring is formed. The wiring 43 is composed of a metal wiring 46 provided in each layer of the interlayer insulating film 2 and a via wiring 47 connected to the metal wiring 46. The metal wiring 46 and the via wiring 47 provided in each layer of the interlayer insulating film 2 are formed continuously between the multilayers of the interlayer insulating film 2. The via wiring 47 formed in the uppermost layer of the interlayer insulating film 2 is formed so as to be exposed from the top surface 2 a of the interlayer insulating film 2. Bonding pad 16 is formed so as to be in contact with the exposed via wiring 47. A bonding wire 50 is connected to the bonding pad 16.

  In the interlayer insulating film 2, wirings 44 for cooling purposes are formed in addition to the wirings 43 necessary and sufficient for the current capacity of the signal / power supply. Similar to the wiring 43, the wiring 44 includes a metal wiring 51 and a via wiring 52 that are continuous between the multilayers of the interlayer insulating film 2. Metal pad 17 is formed so as to contact via wiring 52 exposed from top surface 2a. A heat spreader 49 connected to the metal pad 17 via the metal bump 48 is provided at a position spaced from the top surface 2 a of the interlayer insulating film 2.

  The transistor element 45 is disposed between the wiring 43 and the wiring 44. The wiring 43 and the wiring 44 can be formed from, for example, metals such as copper, aluminum, titanium, tungsten, cobalt, and tantalum, alloys thereof, materials obtained by adding silicon to these, silicide, and the like. These materials have a higher thermal conductivity than materials such as a silicon oxide film that forms the interlayer insulating film 2.

  In addition, a material mainly composed of aluminum and copper is used for the metal wiring constituting the wiring 43 and the wiring 44, and tungsten or copper is particularly used for the via wiring. A metal such as cobalt or titanium is used as a salicide wiring in which silicide is formed at the interface with silicon or a lower layer film of a wiring layer provided as a barrier metal.

  The semiconductor device according to the second embodiment of the present invention is formed in interlayer insulating film 2 and has a wiring 43 as a first heat dissipation member having a relatively high thermal conductivity with respect to the thermal conductivity of interlayer insulating film 2 and The wiring 44 is further provided. The wiring 43 and the wiring 44 include via wirings 47 and 52 and metal wirings 46 and 51 as metal wirings. The wiring 43 and the wiring 44 are exposed from the top surface 2 a as the surface of the interlayer insulating film 2. The semiconductor device further includes a heat spreader 49 as a second heat dissipating member that is disposed outside the interlayer insulating film 2 and is connected to the wiring 43 and the wiring 44 exposed from the top surface 2 a of the interlayer insulating film 2.

  According to the semiconductor device configured as described above, the wiring 43 and the wiring 44 having higher thermal conductivity than the interlayer insulating film 2 can function as a cooling structure in the interlayer insulating film 2. Thereby, the heat generated from the transistor element 45 can be efficiently radiated. Further, since the wiring 43 and the wiring 44 are formed so as to be exposed on the top surface 2 a, heat does not stay in the interlayer insulating film 2. In addition, since the wiring 44 is connected to the heat spreader 49 on the top surface 2a, the heat transmitted to the top surface 2a through the wiring 44 can be efficiently radiated to the outside.

  Note that all or a part of the wirings that are provided as electric / signal wirings and power supply wirings but are not actually used may be used as the above-described heat dissipation structure.

  FIG. 11 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. Referring to FIG. 11, in the present modification, trench 56 is formed in interlayer insulating film 2 so as to open on the top surface 2 a side. The surface of the trench 56 is covered with a metal wiring film 57. The inside of the trench 56 is formed by plating and filled with a heat dissipation member 58 made of, for example, copper. On the top surface 2 a of the interlayer insulating film 2, the top surface of the heat radiation member 58 extending to a position protruding from the top surface 2 a and the heat spreader 49 are connected. FIG. 12 is a cross-sectional view showing another modification of the semiconductor device shown in FIG. Referring to FIG. 12, in the present modification, metal bumps 48 are interposed between heat dissipation member 58 and heat spreader 49 in the cooling structure shown in FIG.

  Also with these configurations, the same effects as those obtained with the semiconductor device shown in FIG. 10 can be obtained. The trench 56 shown in FIGS. 11 and 12 may be formed so as to reach from the top surface 2 a side of the interlayer insulating film 2 to the back surface 1 b side of the semiconductor substrate 1.

(Embodiment 3)
FIG. 13 is a cross-sectional view showing a part of the semiconductor device according to the third embodiment of the present invention. The semiconductor device in this embodiment further includes a cooling structure described with reference to FIG. 13 in addition to the cooling structure included in the semiconductor device described in Embodiment 1. In the figure, the same or corresponding members are denoted by the same reference numerals as compared to the semiconductor device already described.

  Referring to FIG. 13, wirings 66, 67, 68 and 69 corresponding to wiring 43 or wiring 44 in the second embodiment are formed in interlayer insulating film 2 at a predetermined interval. Further, a trench 63 is formed in the interlayer insulating film 2 so as to be located between the wirings 66, 67 and 68 and open to the top surface 2 a side. The trench 63 is filled with a heat radiating member 64 made of, for example, copper. The heat dissipation member 64 is in contact with the metal pad 17 formed on the top surface 2 a of the interlayer insulating film 2. In the interlayer insulating film 2, a trench 62 is formed which is located between the metal wirings 68 and 69 and opens to the top surface 2 a side. A cooling liquid passes and circulates in the trench 62.

  Such a trench can be formed by a dry etching process normally used in a semiconductor wafer manufacturing process. Further, when it is desired to form an opening having a larger diameter, for example, by applying anisotropic wet etching of a silicon substrate using a potassium hydroxide solution (KOH), a quadrangular pyramidal hole based on the pattern shape is formed. Can be formed.

  According to the semiconductor device configured as described above, in addition to the wirings 66 to 69 formed in the interlayer insulating film 2, the cooling liquid flowing in the heat dissipation member 64 and the trench 62 filling the trench 63 is used for cooling. Function. For this reason, the efficiency of heat dissipation can be further improved.

(Embodiment 4)
FIG. 14 is a perspective view showing a semiconductor device according to the fourth embodiment of the present invention. The semiconductor device in this embodiment further includes a cooling structure described with reference to FIG. 14 in addition to the cooling structure included in the semiconductor device described in Embodiment 1. In the figure, the same or corresponding members are denoted by the same reference numerals as compared to the semiconductor device already described.

  Referring to FIG. 14, the semiconductor device in the present embodiment forms a high-frequency integrated circuit. On the top surface 2a of the interlayer insulating film 2, an inductor 74 bent and extended in an L shape and an antenna 73 bent and extended in a spiral shape are formed. The inductor 74 and the antenna 73 are made of a material mainly composed of aluminum or copper, for example. Semiconductor elements 71 and 72 are formed on main surface 1a. In the interlayer insulating film 2, a wiring 43 including a metal wiring 46 and a via wiring 47 connected to the semiconductor elements 71 and 72 is formed. The inductor 74 and the antenna 73 are connected to the wiring 43.

  In the semiconductor device according to the fourth embodiment of the present invention, the second heat radiating member includes at least one of an inductor 74 as an inductor element and an antenna 73 as an antenna element.

  According to the semiconductor device configured as described above, in addition to the wiring 43, the inductor 74 and the antenna 73 can function as a cooling structure. For this reason, the heat transmitted to the top surface 2a of the interlayer insulating film 2 through the wiring 43 can be further efficiently radiated to the outside.

(Embodiment 5)
FIG. 15 is a perspective view showing a semiconductor device according to the fifth embodiment of the present invention. In the drawing, a cross section of the semiconductor device is shown. The semiconductor device in this embodiment further includes a heat insulating structure described with reference to FIG. 15 in addition to the cooling structure included in the semiconductor device described in Embodiment 1. In the figure, the same or corresponding members are denoted by the same reference numerals as compared to the semiconductor device already described.

  Referring to FIG. 15, semiconductor element 81 is formed on main surface 1 a of semiconductor substrate 1. The semiconductor substrate 1 is formed with a trench 82 that opens to the main surface 1 a side and extends to surround the semiconductor element 81. The trench 82 is filled with a heat insulating member 85 made of, for example, a silicon oxide film or a silicon nitride film. The material constituting these heat insulating members 85 has a smaller thermal conductivity than silicon or the like constituting the semiconductor substrate 1.

  The semiconductor element 81 is a semiconductor element for which the influence of heat is desired to be kept small, for example, a semiconductor element constituting an analog circuit. When a semiconductor element having a large calorific value is formed around the semiconductor element 81 with the heat insulating member 85 interposed therebetween, it is possible to suppress heat generated from the semiconductor element from being transmitted to the semiconductor element 81. Thereby, it is possible to prevent the value of the current flowing through the semiconductor element 81 from fluctuating greatly due to a temperature change.

  Further, the semiconductor element 81 and a semiconductor element having a large heat generation amount may be formed in a region surrounded by the heat insulating member 85. In this case, heat from the semiconductor element formed outside the region surrounded by the heat insulating member 85 can be cut off, and the temperature inside the region surrounded by the heat insulating member 85 can be kept constant. Also by this, the same effect as the above-mentioned effect can be obtained.

  In the semiconductor device according to the fifth embodiment of the present invention, a trench 82 is formed in the semiconductor substrate 1 as a recess opening on the main surface 1a side so as to surround the semiconductor element 81.

  FIG. 16 is a perspective view showing a modification of the semiconductor device shown in FIG. 17 is a cross-sectional view taken along the line XVII-XVII in FIG. Referring to FIGS. 16 and 17, in the present modification, two trenches 82 having an L-shaped shape are formed at positions facing each other with semiconductor element 81 interposed therebetween. As described above, the trench formed in the semiconductor substrate 1 may not be formed so as to completely surround the semiconductor element 81.

  FIG. 18 is a perspective view showing another modification of the semiconductor device shown in FIG. FIG. 19 is a cross-sectional view along the line XIX-XIX in FIG. Referring to FIGS. 18 and 19, in this modification, the semiconductor substrate 1 has four trenches 87 extending in one direction on the main surface 1 a and extending from the main surface 1 a side to the back surface 1 b side of the semiconductor substrate 1. Is formed. The four trenches 87 are respectively arranged on the four sides surrounding the semiconductor element 81. By forming such a trench 87 and separating the semiconductor element 81 from its surroundings, the same effect as described above can be obtained. The trench 87 may be filled or filled with a cooling fluid.

  According to the semiconductor device configured as described above, it is possible to suppress a heat change locally generated in the semiconductor substrate 1 from reaching the semiconductor element 81 that is easily affected by the heat change.

(Embodiment 6)
FIG. 20 is a cross sectional view showing a part of the semiconductor device according to the sixth embodiment of the present invention. The semiconductor device in this embodiment further includes a cooling structure described with reference to FIG. 20 in addition to the cooling structure included in the semiconductor device described in Embodiment 1. In the drawing, the same or corresponding members are denoted by the same reference numerals as compared to the semiconductor device already described.

  Referring to FIG. 20, semiconductor element 90 is formed on main surface 1 a of semiconductor substrate 1. On the main surface 1a, an interlayer insulating film 2 formed by laminating a plurality of layers 2p to 2s is formed. In the interlayer insulating film 2, a wiring 44 including a metal wiring 51 and a via wiring 52 is formed. The interlayer insulating film 2 further includes a Peltier element 92 located on the layer 2q and made of two different metals (such as aluminum, copper, tungsten, titanium, and cobalt) or semiconductors of different conductivity types (such as silicon and germanium). And 93 are alternately arranged in a direction parallel to the main surface 1a. The metal wiring 51 formed in the layer 2r and the metal wiring 51 formed in the layer 2q are alternately connected to connect the Peltier elements 92 and 93 to each other at adjacent positions. A heat spreader 49 is provided on the top surface 2 a of the interlayer insulating film 2. The heat spreader 49 and the metal pad 17 in contact with the via wiring 52 are connected via the metal bump 48.

  FIG. 21 is an explanatory diagram for explaining the Peltier effect obtained in the semiconductor device shown in FIG. Referring to FIGS. 20 and 21, it is assumed that Peltier elements 92 and 93 are made of n-type silicon and p-type silicon, respectively, and a current flows in the direction shown in the drawing. In this case, an endothermic effect is generated on the side where the current is directed from the Peltier element 92 to the Peltier element 93, and a heat dissipation effect is generated on the side where the current is directed from the Peltier element 93 to the Peltier element 92. As a result, the heat generated in the semiconductor element 90 formed on the main surface 1a is absorbed to the position where the Peltier elements 92 and 93 are provided, and further radiated to the top surface 2a of the interlayer insulating film 2. The heat is radiated from the heat spreader 49 to the outside through the metal bumps 48.

  The semiconductor device according to the sixth embodiment of the present invention further includes Peltier elements 92 and 93 formed in interlayer insulating film 2.

  According to the semiconductor device configured as described above, a current in a predetermined direction is supplied to the Peltier elements 92 and 93 to obtain the Peltier effect, thereby obtaining a specific portion (in this embodiment, the semiconductor element 90 on the main surface 1a. ) Can be cooled. Thereby, in addition to the effect by the wiring 44, the efficiency of heat dissipation can be further improved.

(Embodiment 7)
FIG. 22 is a perspective view showing a semiconductor device according to the seventh embodiment of the present invention. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. The semiconductor device in this embodiment further includes a cooling structure described with reference to FIG. 22 in addition to the cooling structure included in the semiconductor device described in Embodiment 1.

  Referring to FIGS. 22 and 23, a semiconductor package 101 includes a semiconductor chip 10 formed from the semiconductor device shown in FIG. 1, a heat spreader 104 arranged at a predetermined interval from the semiconductor chip 10, and a semiconductor chip. 10 and a package resin 110 that covers the heat spreader 104. Inside the package resin 110, a cooling path 105 having a first end 106 to which a cooling fluid is supplied and a second end 107 for collecting the cooling fluid is formed. The cooling path 105 extends from one end 106 toward the other end 107 in the vicinity of the heat spreader 104 while changing the direction for each predetermined distance.

  A semiconductor package 101 as a semiconductor device according to the seventh embodiment of the present invention includes a semiconductor chip 10 including a semiconductor substrate 1, an interlayer insulating film 2 and a cooling path 3, and a resin member formed so as to cover the semiconductor chip 10. A package resin 110 and a cooling path 105 formed in the package resin 110 and serving as a second cooling path through which a cooling fluid flows are provided.

  According to the semiconductor package 101 configured as described above, the heat released to the outside of the chip by the cooling structure provided in the semiconductor chip 10 is transmitted to the heat spreader 104 through the package resin 110. In the present embodiment, since the cooling path 105 is formed close to the heat spreader 104, the heat released outside the chip is efficiently radiated further out of the package through the cooling fluid flowing through the cooling path 105. be able to.

(Embodiment 8)
24 is a cross sectional view showing a semiconductor device according to the eighth embodiment of the present invention. The semiconductor device in this embodiment further includes a cooling structure described with reference to FIG. 24 in addition to the cooling structure included in the semiconductor device described in Embodiment 1.

  Referring to FIG. 24, semiconductor chip 10 constituted of the semiconductor device shown in FIG. 1 has surface 10a on which a plurality of square pyramid-shaped holes 116 are formed. The bottom surface of the hole 116 is formed in or penetrates the chip. By such holes 116, the surface 10a of the semiconductor chip 10 is formed in an uneven shape.

  In the semiconductor chip 10 according to the eighth embodiment of the present invention, the surface 10a of the semiconductor chip 10 is formed in an uneven shape.

  According to the semiconductor chip 10 configured as described above, the surface area of the surface 10a can be increased. Thereby, the heat generated in the semiconductor element arranged inside the semiconductor chip 10 can be efficiently radiated to the outside of the chip.

  FIG. 25 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. Referring to FIG. 25, in this modification, the surface 10a of the semiconductor chip 10 is roughened into a concavo-convex shape by being mechanically roughened. The semiconductor chip 10 is provided with a heat dissipation member 121 made of, for example, copper, iron-nickel alloy, solder, or the like so as to contact the roughened surface 10a. With such a configuration, the contact area between the heat dissipation member 121 and the semiconductor chip 10 can be increased, and efficient heat dissipation can be realized.

  As another modification, in a semiconductor process for manufacturing a semiconductor chip, an HSG (hemispherical silicon grain) oxidation step may be performed on a partial region of the polysilicon film deposited for the gate electrode. In this case, an amorphous (amorphous) silicon thin film is further deposited on the deposited polysilicon film. Thereafter, heat treatment is performed at a temperature of about 550 ° C. to grow granular silicon on the polysilicon film. Through these steps, a hemispherical uneven shape can be formed on the surface of the polysilicon film.

(Embodiment 9)
FIG. 26 is a sectional view showing a semiconductor device according to the ninth embodiment of the present invention. Referring to FIG. 29, a semiconductor package 131 is a multi-chip type semiconductor package in which a plurality of semiconductor chips 132 are mounted. The semiconductor package 131 includes a plurality of semiconductor chips 132 (132a, 132b, and 132c) that are positioned at predetermined intervals, metal bumps 133 that connect the plurality of semiconductor chips 132, and a plurality of semiconductor chips 132. And a heat dissipating member 135 made of, for example, copper, disposed between them. Although not shown, the semiconductor package 131 is provided with a resin material such as package resin or polyimide as a filler between the plurality of semiconductor chips 132.

  The plurality of semiconductor chips 132 are arranged such that the semiconductor chips 132a and 132c are located at both ends, and the semiconductor chip 132b is located therebetween. Each of the plurality of semiconductor chips 132 is formed with a via wiring 134 penetrating the chip. By providing the metal bump 133 in contact with the via wiring 134, the plurality of semiconductor chips 132 are connected to each other in a stacked state.

  A heat spreader 136 is disposed at a position adjacent to the semiconductor chip 132c with a space between the semiconductor chip 132c and the semiconductor chip 132c. The semiconductor chip 132c and the heat spreader 136 are connected by metal bumps 133 that are in contact with the via wiring 134 formed in the semiconductor chip 132c. A heat dissipation member 135 is disposed between the semiconductor chip 132c and the heat spreader 136.

  In the present embodiment, the heat dissipation member 135 is disposed between the plurality of semiconductor chips 132 and between the semiconductor chip 132c and the heat spreader 136, but the present invention is not limited to this. For example, a cooling path may be formed in the package resin filling between these, and a cooling gas or liquid may be allowed to flow through the cooling path.

  In the present embodiment, the semiconductor chip 132b that generates a relatively small amount of heat when driven is positioned at an intermediate portion of the array of the plurality of semiconductor chips 132, and a plurality of semiconductor chips 132a and 132c that generate a relatively large amount of heat. The semiconductor chips 132 are arranged at both ends of the array. Preferably, the heat generation amount of the semiconductor chips 132a and 132b may be smaller than the heat generation amount of the semiconductor chip 132c provided adjacent to the heat spreader 136.

  A multi-chip type semiconductor package 131 according to the ninth embodiment of the present invention directly contacts and adjoins a plurality of semiconductor chips 132 arranged in one direction at intervals from each other and a plurality of semiconductor chips 132. Metal bumps 133 as metal wirings that connect the plurality of semiconductor chips 132 to each other, and heat dissipation members 135 as heat dissipation means disposed between the plurality of adjacent semiconductor chips 132 are provided. The amount of heat generated from the semiconductor chip 132b located in the middle of the plurality of semiconductor chips 132 arranged in one direction is generated from the semiconductor chips 132a and 132c located at both ends of the plurality of semiconductor chips 132 arranged in one direction. Less than the amount of heat

  The semiconductor package 131 further includes a heat spreader 136 as a heat radiating plate adjacent to the semiconductor chip 132c located at the end of the plurality of semiconductor chips 132 arranged in one direction and connected to the semiconductor chip 132c. The amount of heat generated from the other semiconductor chips 132a and 132b excluding the semiconductor chip 132c to which the heat spreader 136 is connected is smaller than the amount of heat generated from the semiconductor chip 132c to which the heat spreader 136 is connected.

  According to the semiconductor package 131 configured as described above, since the plurality of semiconductor chips 132 are connected to each other via the metal bumps 133, the generated heat can be conducted between the chips. Thereby, the temperature gradient in the direction in which the plurality of semiconductor chips 132 are arranged is reduced, and the plurality of semiconductor chips 132 are cooled by the heat spreader 136 disposed adjacent to the heat dissipation member 135 and the semiconductor chip 132c disposed between the chips. be able to.

  In general, a semiconductor chip is provided with an absolute maximum rating of a junction temperature, and there is an upper temperature limit for preventing element destruction. In addition, when a semiconductor element is operated at a high temperature, the transistor performance deteriorates due to a decrease in carrier mobility inside the semiconductor, the driver drive current / driver ability decreases and the operation speed decreases, and the junction leakage current rapidly increases. Deterioration of device characteristics such as an increase in power consumption is caused. In addition, if there is a temperature gradient between chips, it is assumed that variations in semiconductor characteristics increase and a deviation from the design operation timing occurs. In particular, if the signal transmission side and the reception side have different temperatures and a signal timing shifts, malfunction may occur. According to the semiconductor package 131 in the present embodiment, these problems can be solved by the above-described effects.

  Further, heat generated from the semiconductor chip is relatively difficult to dissipate at an intermediate portion where the plurality of semiconductor chips 132 are arranged or at a position away from the heat spreader 136. For this reason, by arranging a semiconductor chip with a large calorific value at such a position, the temperature gradient can be further reduced and the semiconductor chip can be cooled more efficiently.

(Embodiment 10)
FIG. 27 is a perspective view showing a semiconductor device according to the tenth embodiment of the present invention. FIG. 28 is a front view showing the semiconductor device as viewed from an arrow XXVIII shown in FIG.

  27 and 28, semiconductor package 151 is a multi-chip type semiconductor package in which a plurality of semiconductor chips 152 are mounted. The semiconductor package 151 includes a plurality of semiconductor chips 152 (152a, 152b, and 152c) positioned at intervals, a resin material (not shown) made of package resin, polyimide, and the like, filled between the plurality of semiconductor chips 152, And a cooling passage 155 formed in a resin material and through which a cooling gas or liquid flows.

  The semiconductor chips 152a and 152c have surfaces 161 and 163, respectively, at positions facing each other. The semiconductor chip 152b has a surface 162 at a position facing the semiconductor chip 152c. The semiconductor chips 152a and 152c are arranged so as to be shifted from each other so that a portion of the surface 161 that does not face the surface 163 is generated. In the vicinity of that portion of the surface 161 that does not face the surface 163, a space 153 is defined adjacent to the semiconductor chips 152a and 152c. Similarly, the semiconductor chip 152b has a portion on the surface 162 that does not face the surface 163 of the semiconductor chip 152c, and a space 153 is defined in the vicinity of the portion adjacent to the semiconductor chips 152b and 152c. . Further, a space 153 is defined between the semiconductor chip 152a and the semiconductor chip 152b.

  The cooling path 155 is located in the space 153 and extends along the periphery of the semiconductor chip. In addition to the cooling path 155, a heat dissipation member made of copper or the like may be disposed in the space 153.

  FIG. 29 is a front view showing a modification of the semiconductor package shown in FIG. Referring to FIG. 29, in this modification, semiconductor chips 152b and 152c are arranged in the same manner as semiconductor package 151 shown in FIG. A cooling path 155 is provided in a space 153 defined adjacent to the semiconductor chips 152b and 152c.

  FIG. 30 is a front view showing another modification of the semiconductor package shown in FIG. Referring to FIG. 30, the semiconductor package is filled with a plurality of semiconductor chips 152 (152d and 152e) positioned at a predetermined interval and a plurality of semiconductor chips 152, and is made of package resin, polyimide, or the like. A resin material (not shown) and a cooling path 155 formed in the resin material and through which a cooling gas or liquid flows are provided.

  The semiconductor chips 152d and 152e have surfaces 181 and 182 at positions facing each other. The surface 182 has a larger area than the surface 181 and has a portion that does not face the surface 181. In the vicinity of that portion of the surface 182 that does not face the surface 181, a space 153 is defined adjacent to the semiconductor chips 152 d and 152 e. The cooling path 155 is located in the space 153 and extends along the periphery of the semiconductor chip 152d.

  A multi-chip type semiconductor package 151 according to the tenth embodiment of the present invention includes a plurality of semiconductor chips 152 arranged so as to define a space 153 at positions adjacent to each other, and cooling as a heat dissipation means provided in the space 153. Path 155. The plurality of semiconductor chips 152 include two semiconductor chips 152d and 152e having surfaces 181 and 182 of different sizes at positions facing each other, and two semiconductor chips 152a and 152c (152b) arranged so as to be shifted at adjacent positions. And at least one of 152c). The heat radiating means includes at least one of a cooling path 155 through which a cooling fluid flows and a heat radiating member made of a metal material.

  According to the semiconductor package 151 configured as described above, since the cooling path 155 is formed in the space 153 defined between adjacent semiconductor chips, the semiconductor chip can be efficiently manufactured while maintaining the semiconductor package 151 compact. Can be cooled. Thereby, the number of semiconductor chips mounted on the semiconductor package 151 can be increased, and a high-performance semiconductor integrated circuit can be realized.

  The semiconductor device may be configured by appropriately combining the semiconductor devices of the first to tenth embodiments described above. In this case, the effects obtained by the combined semiconductor devices of the embodiments can be obtained comprehensively.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a perspective view showing a semiconductor device in a first embodiment of the present invention. FIG. 2 is a perspective view showing a semiconductor package provided with the semiconductor device shown in FIG. 1. It is sectional drawing which shows the structure of the pump chip | tip in FIG. It is sectional drawing which shows the 1st process of the method of manufacturing a cooling path in an interlayer insulation film. It is sectional drawing which shows the 2nd process of the method of manufacturing a cooling path in an interlayer insulation film. It is sectional drawing which shows the 3rd process of the method of manufacturing a cooling path in an interlayer insulation film. It is sectional drawing which shows the 4th process of the method of manufacturing a cooling path in an interlayer insulation film. FIG. 10 is a perspective view showing a modification of the semiconductor device shown in FIG. 1. FIG. 10 is a perspective view showing another modification of the semiconductor device shown in FIG. 1. It is sectional drawing which shows a part of semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows the modification of the semiconductor device shown in FIG. It is sectional drawing which shows another modification of the semiconductor device shown in FIG. It is sectional drawing which shows a part of semiconductor device in Embodiment 3 of this invention. It is a perspective view which shows the semiconductor device in Embodiment 4 of this invention. It is a perspective view which shows the semiconductor device in Embodiment 5 of this invention. FIG. 16 is a perspective view showing a modification of the semiconductor device shown in FIG. 15. It is sectional drawing along the XVII-XVII line | wire in FIG. FIG. 16 is a perspective view showing another modification of the semiconductor device shown in FIG. 15. It is sectional drawing along the XIX-XIX line | wire in FIG. It is sectional drawing which shows a part of semiconductor device in Embodiment 6 of this invention. It is explanatory drawing for demonstrating the Peltier effect obtained with the semiconductor device shown in FIG. It is a perspective view which shows the semiconductor device in Embodiment 7 of this invention. It is sectional drawing along the XXIII-XXIII line | wire in FIG. It is sectional drawing which shows the semiconductor device in Embodiment 8 of this invention. FIG. 25 is a cross-sectional view illustrating a modified example of the semiconductor device illustrated in FIG. 24. It is sectional drawing which shows the semiconductor device in Embodiment 9 of this invention. It is a perspective view which shows the semiconductor device in Embodiment 10 of this invention. FIG. 28 is a front view showing the semiconductor device viewed from an arrow XXVIII shown in FIG. 27. FIG. 29 is a front view showing a modification of the semiconductor package shown in FIG. 28. FIG. 29 is a front view showing another modified example of the semiconductor package shown in FIG. 28.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1a Main surface, 2 Interlayer insulation film, 2a Top surface, 3,105,155 Cooling path, 4 One end, 5 Other end, 10,132,132a, 132b, 132c, 152,152a, 152b, 152c , 152d, 152e Semiconductor chip, 10a, 181, 182 Surface, 11, 110 Package resin, 12, 49, 136 Heat spreader, 13 Pump chip, 20, 131, 151 Semiconductor package, 43, 44, 66, 67, 68, 69 Wiring, 46, 51 Metal wiring, 47, 52 Via wiring, 64, 135 Heat radiation member, 73 Antenna, 74 Inductor, 81 Semiconductor element, 82, 87 Trench, 92, 93 Peltier element, 133 Metal bump, 153 Space.

Claims (1)

A semiconductor substrate having a main surface;
A semiconductor element formed on the main surface of the semiconductor substrate;
An interlayer insulating film formed on the main surface of the semiconductor substrate and provided to cover the semiconductor element;
A cooling path for flowing a cooling fluid, formed in the interlayer insulating film,
The cooling path is formed to circulate inside the interlayer insulating film ,
The cooling path includes one end to which a cooling fluid is supplied and the other end from which the cooling fluid is discharged, and
A multilayer metal wiring layer formed inside the interlayer insulating film;
The said cooling path is a semiconductor device comprised by the groove | channel formed by patterning the said multilayer metal wiring layer .

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