JP2011040624A - Electronic equipment and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide electronic equipment for preventing any local rise in temperature of an electronic circuit. <P>SOLUTION: This electronic device has a first cooled substrate, a second cooled substrate which faces the first cooled substrate, and a thermoelectric element which comprises a first material whose endothermic joint to the first cooled substrate is carried out and a second material whose endothermic joint to the second cooled substrate is carried out, and which has undergone the first material and the second material endothermic joint between the first cooled substrate and the second cooled substrate. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electronic device including a heat generating member such as an electronic circuit.

  A three-dimensional IC (hereinafter referred to as 3D-IC) obtained by stacking a plurality of IC (Integrated Circuit) chips and connecting them with a TSV (Through Silicon Via) is known. The 3D-IC is considered to be capable of high-speed operation by shortening the distance of the signal wiring. Further, it is considered that there is a possibility that an advanced chip can be realized at low cost by combining and stacking ICs that are not so miniaturized, rather than making a highly miniaturized IC.

  However, it is difficult to incorporate an IC chip having a large calorific value such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit) into the 3D-IC for the following reasons. In the 3D-IC, heat generated from the IC chip disposed on the outermost surface can be released by air-cooling or water-cooling metal fins that are in close contact with the surface of the package. However, the heat generated from the internal IC chip away from the outermost surface is difficult to dissipate because the heat flow path in the vertical direction is closed. For this reason, the temperature of the internal IC chip is likely to rise, which causes deterioration of the performance of the IC chip and electromigration that seriously affects the reliability in the IC chip.

  In order to efficiently cool the portion that generates local heat during operation in this way, for example, a water-cooling path formed by a Si process is installed in a lattice shape inside the IC chip, and water is allowed to flow through this to cause heat from the inside. Has been proposed (see Non-Patent Document 1). However, since this cooling structure has a complicated configuration, processing is complicated, and it is difficult to ensure high reliability.

Brunschwiller, T.W. Michel, B .; Rothuzen, H .; , Kloter, U .; Wunderle, B .; , Oppermann, H .; Reichl, H .; “Forced interactive intermediary cooling in vertically integrated packages”, “Thermal and Thermomechanical Phenomena in Electronic Systems, 2008.

  An object of this invention is to provide the electronic device which prevents the local temperature rise of an electronic circuit.

According to one aspect of the invention,
A second cooled substrate facing the first cooled substrate;
A first material that is endothermicly bonded to the first substrate to be cooled; and a second material that is endothermicly bonded to the second substrate to be cooled; and the first material to be cooled between the first substrate to be cooled and the second substrate to be cooled. An electronic device comprising a thermoelectric element in which a first material and the second material are heat-bonded is provided.

According to another aspect of the present invention,
Preparing a first cooled substrate and a second cooled substrate;
Electrically bonding the first material and the second material;
Placing one of the first material and the second material in contact with the first substrate to be cooled or in the vicinity of the first substrate to be cooled;
Placing the other of the first material and the second material in contact with the second substrate to be cooled or in the vicinity of the second substrate to be cooled;
A method for manufacturing an electronic device is provided.

  The electronic device of the present invention can prevent local temperature rise of the electronic circuit.

1 is a perspective view showing a first embodiment of an electronic device of the present invention. It is sectional drawing of the electronic device of 1st Embodiment. It is a cross-sectional schematic diagram which shows the modification of the electronic device of 1st Embodiment. FIG. 4 is a schematic diagram illustrating an example of an electronic circuit and a current flow in the electronic device illustrated in FIG. 3. It is a schematic diagram which shows another example of the electronic circuit in the electronic device shown by FIG. 3, and the flow of an electric current. It is a schematic diagram which shows the electronic device of 2nd Embodiment. It is sectional drawing which shows the laminated body in the middle of manufacture of the electronic device of 2nd Embodiment. It is sectional drawing which shows the laminated body in the middle of manufacture of the electronic device of 2nd Embodiment. It is sectional drawing which shows the laminated body in the middle of manufacture of the electronic device of 2nd Embodiment. It is sectional drawing which shows the laminated body in the middle of manufacture of the electronic device of 2nd Embodiment. It is sectional drawing which shows the electronic device of 3rd Embodiment. It is sectional drawing which shows the laminated body in the middle of manufacture of the electronic device of 3rd Embodiment. It is sectional drawing which shows the laminated body in the middle of manufacture of the electronic device of 3rd Embodiment. It is sectional drawing which shows the laminated body in the middle of manufacture of the electronic device of 3rd Embodiment. It is sectional drawing which shows the laminated body in the middle of manufacture of the electronic device of 3rd Embodiment. It is sectional drawing which shows the 1st modification of the electronic device of 2nd Embodiment. It is sectional drawing which shows the 2nd modification of the electronic device of 2nd Embodiment. It is sectional drawing which shows the 3rd modification of the electronic device of 2nd Embodiment. It is sectional drawing which shows the 4th modification of the electronic device of 2nd Embodiment. It is sectional drawing which shows the 5th modification of the electronic device of 2nd Embodiment.

  FIG. 1 is a perspective view showing a first embodiment of an electronic device according to the present invention. The electronic device 10 according to the first embodiment includes a semiconductor substrate (cooled substrate) 34 provided with an electronic circuit (not shown), and a semiconductor substrate (covered) provided with an electronic circuit (not shown) facing the semiconductor substrate 34. A cooling substrate) 35, a thermoelectric element 20a in which the first material 12a and the second material 14a are electrically connected in series, and a second material 14b and the first material 12b are electrically connected in series. And a thermoelectric element 20b. Further, in the thermoelectric elements 20a and 20b, the first material 12a and 12b and the second material 14a and 14b may be joined via the heat radiation portions 13a and 13b having high thermal conductivity, respectively. In the thermoelectric elements 20a and 20b, the current inflow ends 28a and 28b are provided in the first materials 12a and 12b, and the outflow end 29a is provided in the second materials 14a and 14b. Junction portions (heat radiation portions 13 a and 13 b) of the thermoelectric elements 20 a and 20 b are disposed between the semiconductor substrates 34 and 35.

  The Peltier effect is a phenomenon in which, when two dissimilar metals or semiconductors are electrically joined in series and a direct current is passed, heat absorption and heat generation other than Joule heat occurs at the joint. A cooling element using the Peltier effect is called a thermoelectric element (Peltier element). In the electronic device 10 of the present embodiment, current flows in series in the thermoelectric elements 20a and 20b, so that heat is dissipated in the joint portions 13a and 13b between the first material 12a and 12b and the second material 14a and 14b, respectively. Heat is absorbed at the inflow ends 28a and 28b and the outflow ends 29a and 29b.

  The thermoelectric elements 20a and 20b have a form in which, for example, a P-type semiconductor as the first material 12a and 12b and an N-type semiconductor as the second material 14a and 14b are electrically joined and arranged in series. The main components of the first material 12a, 12b and the second material 14a, 14b are, for example, BiTe, PbTe, SiGe, silicide, skutterudite, transition metal oxide, zinc antimony, boron compound, Cluster solids and carbon nanotubes.

Examples of the BiTe-based material include BiTe, SbTe, BiSe, and compounds containing them. Examples of the PbTe-based material include PbTe, SnTe, AgSbTe, GeTe, and compounds containing them. Furthermore, examples of the SiGe-based material include Si, Ge, and SiGe, and examples of the silicide-based material include FeSi, MnSi, and CeSi. The skutterudite-based material is a compound described as MX ₃ or RM ₄ X ₁₂ . However, M is any element of Co, Rh, and Ir, X is any element of As, P, and Sb, and R is any element of La, Yb, and Ce.

  Transition metal oxide materials include CaMnO, NaCoO, ZnInO, SrTiO, BiSrCoO, PbSrCoO, CaBiCoO, and BaBiCoO. The zinc antimony-based material includes, for example, ZnSb, and the boron compound material includes CeB, BaB, SrB, CaB, MgB, VB, NiB, CuB, and LiB. The cluster solid material includes B cluster, Si cluster, C cluster, AlRe, and AlReSi. An example of the zinc oxide-based material is ZnO.

Bi _0.5 Sb _1.5 Te ₃ is given as a typical composition used for the first materials 12a and 12b, and Bi ₂ Te _2.85 Se ₀ is given as a typical composition used for the second materials 14a and 14b. _.15 .

  The heat radiating portions 13a and 13b are made of a material having high thermal conductivity and high electrical conductivity, and can be formed using, for example, copper.

  In the electronic device of the present invention, the current inflow end and the outflow end are in contact with or in the vicinity of either one of the pair of substrates to be cooled that sandwich the thermoelectric element. In the first embodiment, the current inflow end 28 a of the thermoelectric element 20 a is in contact with the semiconductor substrate 34, and the current outflow end 29 a is in contact with the semiconductor substrate 35. On the other hand, in the first embodiment, the current inflow end 28 b of the thermoelectric element 20 b is in contact with the semiconductor substrate 35, and the current outflow end 29 b is in contact with the semiconductor substrate 34.

  Although not shown in the electronic device of FIG. 1, vias for transmitting and receiving signals between electronic circuits provided on each semiconductor substrate may be provided.

FIG. 2 is a cross-sectional view of the electronic device of the first embodiment shown in FIG. In FIG. 2, the current flow and heat flow in the electronic device are shown. When the currents I ₁ and I ₂ flow from the current inflow ends 28a and 28b toward the outflow ends 29a and 29b, heats H ₁ and H ₂ flow from the current inflow end 28a and the outflow end 29a toward the heat radiating portion 13a. The heat H ₃ and H ₄ flow from the current inflow end 28b and the outflow end 29b toward the heat radiating portion 13b. That is, the heat generated in the semiconductor substrates 34 and 35 moves from the current inflow end 28a and the outflow end 29a and the current outflow end 29a and the outflow end 29b to the junction (the heat radiating portions 13a and 13b). Therefore, local temperature rise of the semiconductor substrates 34 and 35 can be prevented.

  Furthermore, when the heat radiation portions 13a and 13b have a form extending, for example, in a direction substantially parallel to the semiconductor substrate so as to function as heat radiation fins, the cooling efficiency of each semiconductor substrate can be increased. Further, the cooling efficiency can be increased by forcibly cooling the exposed portions of the heat radiation portions 13a and 13b. The means for forcibly cooling is not particularly limited. For example, it is possible to efficiently cool the air by sending air to this portion with a fan. Alternatively, for example, by cooling the heat dissipating fins extending from the inside of the package covering the electronic device to the outside, it is possible to cool the air efficiently without affecting the electrical circuit in the chip. Noise caused by can be suppressed.

  A circuit and a power source for generating a current to be passed through the thermoelectric elements 20a and 20b are not particularly limited. For example, a power source current (not shown) for driving an electronic circuit (not shown) provided on the semiconductor substrates 34 and 35 is used. Can be used. In addition, each substrate to be cooled can be effectively cooled by supplying a power supply current dedicated to cooling to the thermoelectric elements 20a and 20b instead of a current flowing through an electronic circuit provided on the semiconductor substrates 34 and 35. When a power supply current dedicated for cooling is supplied, current may be supplied to the thermoelectric elements 20a and 20b via a dedicated cooling path (not shown) provided on each substrate to be cooled, or on the substrate to be cooled. A current may be supplied to the thermoelectric elements 20a and 20b via wire bonding (not shown) electrically connected to an external power source without providing a cooling-dedicated path.

  FIG. 3 is a schematic cross-sectional view illustrating a modification of the electronic device according to the first embodiment. In FIG. 3, parts that are the same as those in the electronic device of the first embodiment are given the same reference numerals, and descriptions thereof are omitted. The electronic device shown in FIG. 3 has a configuration obtained by adding one semiconductor substrate 36 and two thermoelectric elements 40a and 40b to the electronic device shown in FIG. The semiconductor substrate 36 provided with an electronic circuit (not shown) faces the surface of the semiconductor substrate 35 opposite to the semiconductor substrate 34. A thermoelectric element 40a in which the first material 16a and the second material 18a are electrically connected in series between the semiconductor substrate 35 and the semiconductor substrate 36, and the second material 18b and the first material 16b are electrically connected. And a thermoelectric element 40b joined in series. Further, in the thermoelectric elements 40a and 40b, the first material 16a and 16b and the second material 18a and 18b may be joined via the heat radiating portions 17a and 17b having high thermal conductivity, respectively. In the thermoelectric elements 40a and 40b, the current inflow ends 48a and 48b are provided in the first material 16a and 16b, and the outflow end 49a is provided in the second material 18a and 18b. In FIG. 3, the current flow and heat flow in the electronic device are shown.

When the currents I ₃ and I ₄ are flown from the current inflow ends 48a and 48b toward the outflow ends 49a and 49b, heats H ₅ and H ₆ flow from the current inflow end 48a and the outflow end 49a toward the heat radiating portion 17a. , heat _{H 7} and _{H 8} flows from the inlet end 48b and an outlet end 49b of the current to the heat radiating portion 17b. That is, the heat generated in the semiconductor substrates 35 and 36 moves from the current inflow end 48a and the outflow end 49a and the current outflow end 49a and the outflow end 49b to the junction (the heat radiation portions 17a and 17b). Therefore, local temperature rise of the semiconductor substrates 35 and 36 can be prevented. Further, the operation of the thermoelectric elements 20a and 20b for cooling the semiconductor substrates 34 and 35 is the same as that of the first embodiment, and thus the description thereof is omitted.

  FIG. 4 is a schematic diagram illustrating an example of an electronic circuit and a current flow in the electronic device illustrated in FIG. 3. In FIG. 4, only the first material and the second material are shown in the thermoelectric elements 20a, 20b, 40a, and 40b of FIG. Also, connections between electronic circuits that are not connected to thermoelectric elements are not shown. The electronic device 10 includes an electronic circuit 31 provided on the semiconductor substrate 34, an electronic circuit 32 provided on the semiconductor substrate 35, and an electronic circuit 33 provided on the semiconductor substrate 36. The electronic circuits 31 to 33 are connected to the power supply 61 in parallel. The thermoelectric elements 20 a, 20 b, 40 a, 40 b are connected in series with the electronic circuit 33. The thermoelectric elements 20 a and 20 b are connected in series to the electronic circuit 32. Currents I1, I2, I3, and I4 flowing through the thermoelectric elements 20a, 20b, 40a, and 40b flow from the first material 12a, 12b, 16a, and 16b toward the second material 14a, 14b, 18a, and 18b, respectively.

  FIG. 5 is a schematic diagram illustrating another example of an electronic circuit and a current flow in the electronic device illustrated in FIG. 3. 5, only the first material and the second material are shown in the thermoelectric elements 20a, 20b, 40a, and 40b in FIG. The electronic circuits 31 to 33 are connected to the power supply 61 in parallel. The thermoelectric elements 20a, 20b, 40a, 40b are not electrically connected to the electronic circuits 31-33. The thermoelectric elements 20 a and 20 b are connected by a current path different from the electronic circuit 32 provided on the semiconductor substrate 35. The thermoelectric elements 40 a and 40 b are connected by a different current path from the electronic circuit 33 provided on the semiconductor substrate 36. The cooling power source 63 supplies current to the series circuit in which current flows in the order of the thermoelectric elements 20a, 40a, 40b, and 20b and the series circuit in which current flows in the order of the thermoelectric elements 20a and 20b via the control circuit 62. The current dedicated for cooling can be controlled by the control circuit 62 separately from the current flowing through the electronic circuits 31 to 33, and the cooling of the semiconductor substrates 34 to 36 can be effectively controlled. The control circuit 62 may be provided on the semiconductor substrates 35 and 36, or the thermoelectric elements 20a, 20b, 40a, and 40b may be directly connected to the cooling power source 63 without passing through the control circuit.

  The electronic device according to the present embodiment can be manufactured at a similar cost by various 3D-IC manufacturing methods currently being studied.

  FIG. 6 is a schematic diagram illustrating an electronic apparatus according to the second embodiment. The electronic device according to the second embodiment is incorporated in an FCBGA (Flip Chip-Ball Grid Array) package. In the electronic device illustrated in FIG. 6, a semiconductor substrate 34 including an electronic circuit 31, a semiconductor substrate 35 including an electronic circuit 32, and a semiconductor substrate 36 including an electronic circuit 33 are stacked. The electronic circuits 31 to 33 are provided on the lower surfaces of the semiconductor substrates 34 to 36, respectively. A plurality of via holes 57 and 58 are provided in the semiconductor substrates 34 and 35 as needed. Vias 25 (Through Silicon Via; TSV) are formed inside the plurality of via holes 57 and 58, respectively. The thickness of the semiconductor substrates 34 to 36 is, for example, 50 μm.

  Between the semiconductor substrates 34 and 35, there are via holes 21 and 22 for providing the thermoelectric elements 20a and 20b inside, and a plurality of via holes 37 for providing vias for joining the electronic circuit 31 and the electronic circuit 32 inside. The formed insulating layer 13, the thermoelectric element 20 a in which the first material 12 a, the metal layer 26 a, and the second material 14 a provided in the via hole 21 are stacked on the semiconductor substrate 34, and the via hole 22. A plurality of thermoelectric elements 20b in which the second material 14b, the metal layer 26b, and the first material 12b are stacked on the semiconductor substrate 34, and a plurality of materials mainly composed of, for example, tungsten (W) provided in the plurality of via holes 37. Vias 25 are provided.

  Similarly, between the semiconductor substrates 35 and 36, a plurality of via holes 23 and 24 for providing the thermoelectric elements 40a and 40b and vias for bonding the electronic circuit 32 and the electronic circuit 33 are provided inside. The insulating layer 17 in which the via hole 38 is formed, the thermoelectric element 40 a in which the first material 16 a, the metal layer 27 a, and the second material 18 a provided in the via hole 23 are stacked on the semiconductor substrate 35, and the via hole 24. A thermoelectric element 40b in which the provided second material 18b, metal layer 27b, and first material 16b are stacked on the semiconductor substrate 35, and a plurality of vias 25 made of, for example, tungsten (W) provided in the plurality of via holes 38. Is provided.

  The semiconductor substrate 34 is flip-chip mounted on a package substrate 52 provided with a plurality of solder bumps 51 on the upper surface. The periphery of the solder bump 51 is filled with an underfill 44. The electronic circuit 31 is connected to a plurality of solder bumps 51. The electronic circuit 32 is connected to the plurality of solder bumps 51 through the via 25 and the thermoelectric elements 20 a and 20 b embedded in the insulating layer 13 and the via 25 embedded in the semiconductor substrate 34. The electronic circuit 33 includes a via 25 and thermoelectric elements 40a and 40b embedded in the insulating layer 17, a via 25 embedded in the semiconductor substrate 35, a via 25 and thermoelectric elements 20a and 20b embedded in the insulating layer 13, and a semiconductor substrate. Are connected to a plurality of solder bumps 51 via vias 25 embedded in the. The solder bump 51 is connected to a solder bump 53 provided on the opposite side of the package substrate 52. The electronic circuits 31 to 33 can be connected to an external substrate or circuit via the solder bumps 53 to exchange electric signals. In addition, between the electronic circuits 31 to 33, electric signals are transmitted through the via holes 57 and 58 of the semiconductor substrates 31 and 32 and the via holes 37 and 38 embedded in the insulating layers 13 and 17, respectively. Can give and receive.

  The thermoelectric elements 20a, 20b, 40a, 40b are respectively joined portions of the first material 12a, 12b, 16a, 16b, the second material 14a, 14b, 18a, 18b, and the first material and the second material. And metal layers 26a, 26b, 27a, 27b. The first materials 12a, 12b, 16a, and 16b are P-type semiconductors, and the second materials 14a, 14b, 18a, and 18b are N-type semiconductors. The details of the first material and the second material are the same as those in the first embodiment, and will be omitted. The metal layers 26a, 26b, 27a, and 27b are formed of, for example, a material having high thermal conductivity and conductivity, like the heat radiating portions 13a and 13b of the first embodiment.

  FIG. 6 shows currents C1 and C2 passing through the thermoelectric elements 20a, 20b, 40a, and 40b. In the present embodiment, the current C1 is supplied from the DC power supply VDD of 5V via the via 25a, the thermoelectric element 20a, the via 25c, the thermoelectric element 40a, the electronic circuit 33, the thermoelectric element 40b, the via 25d, the thermoelectric element 20b, and the via 25b. It flows to the ground GND. The current C2 flows from the 5V DC power supply VDD to the ground GND via the via 25a, the thermoelectric element 20a, the electronic circuit 32, the thermoelectric element 20b, and the via 25b. When currents C1 and C2 are passed through the thermoelectric elements 20a, 20b, 40a and 40b, heat is transferred from the upper and lower ends of the thermoelectric elements 20a, 20b, 40a and 40b to the metal layers 26a, 26b, 27a and 27b by the Peltier effect. To do. Therefore, local temperature rise in the semiconductor substrates 34 to 36 provided with the electronic circuits 31 to 33 can be prevented.

  Each shape of the first material 12a, 12b, 16a, 16b and the second material 14a, 14b, 18a, 18b is different between each first material and each of the pair of semiconductor substrates provided above and below each thermoelectric element. A junction with the second material is provided, the current inlet of the first material is in contact with one semiconductor substrate or in the vicinity of one semiconductor substrate, and the current outlet of the second material is in contact with the other semiconductor substrate. Or as long as it arrange | positions in the vicinity of the other semiconductor substrate, it does not specifically limit. The shape of the first material 12a, 12b, 16a, 16b and the second material 14a, 14b, 18a, 18b is, for example, a cylindrical shape, and the diameter of the cross section parallel to the semiconductor substrate 34 is, for example, 20 μmφ. The length in the direction perpendicular to 34 is 20 μm. Between the metal layers 26a, 26b, 27a, 27b and the first material 12a, 12b, 16a, 16b, and between the metal layers 26a, 26b, 27a, 27b and the second material 14a, 14b, 18a, 18b, In order to perform electrical and mechanical connection, the first material 12a, 12b, 16a, 16b or the second material 14a, 14b, 18a, 18b / Ni plated layer / 58Bi42Sn alloy solder layer / metal layer 26a, It may have a laminated structure of 26b, 27a, 27b ("/" means that layers on both sides thereof are laminated).

The metal layers 26a, 26b and 27a, 27b are in contact with the insulating layer 13 and the insulating layer 17, respectively. The heat transferred to the metal layers 26a, 26b and 27a, 27b moves to the heat spreader 45 through the insulating layer 13 and the insulating layer 17, respectively. As described above, the insulating layers 13 and 17 fix and hold the thermoelectric materials 20a, 20b, 40a, and 40b and the via 25, and also function as a heat release path of the joint portion (the metal layer 26a and the metal layer 27a). . As a material of the insulating layers 13 and 17, for example, alumina (Al ₂ O ₃ ) can be considered. The thickness of the insulating layers 13 and 17 (the length in the direction perpendicular to the semiconductor substrate 34) is, for example, 42 μm.

  The insulating layers 13, 17 having a shape extending substantially parallel to the semiconductor substrate 34 are in good thermal contact with the heat spreader 45 via TIM (Thermal Interface Material) 41, 42. Similarly, the upper surface of the semiconductor substrate 36 is in good thermal contact with the heat spreader 45 via the TIM 43. The heat spreader 45 is cooled by, for example, air sent by a fan (not shown) or a heat sink (not shown) provided on the surface of the heat spreader 45.

  In addition to W, examples of the via material embedded in each via hole provided in each semiconductor substrate include Al and Cu. Vias using Al can be formed in substantially the same process as vias using W. In order to prevent the via made of Cu from diffusing into the semiconductor substrate, a diffusion prevention film such as SiN, TiN, TaN, Ta, etc. is provided inside the via hole of the semiconductor substrate, and then the via using Cu is formed. Also good. The antioxidant film is obtained, for example, by processing a film formed by a CVD method by lift-off. If Cu is used instead of W as the material for the via, there is a disadvantage that the number of man-hours increases. However, since Cu has better thermal conductivity than W and has a lower resistance, the heat dissipation efficiency of the semiconductor substrate is improved.

  Below, an example of the manufacturing method of the electronic device of 2nd Embodiment is demonstrated using FIGS. However, the electronic device manufacturing method described below uses a 3D-IC manufacturing method and is not necessarily limited thereto.

First, a method for processing a semiconductor substrate on which an electronic circuit is arranged will be described with reference to FIG. FIG. 7A shows a Si substrate 34 having an electronic circuit 31 disposed on the surface, which is obtained through a general Si process. A material for the mask 71 is formed thereon, and further patterned by photolithography to form the mask 71 (FIG. 7B). The mask 71 may be formed using a resist, or may be formed by depositing SiO ₂ formed by CVD at a low temperature and patterning the SiO ₂ film. Since both are performed after the electronic circuit is arranged, a high temperature process exceeding about 500 ° C. is not preferable.

  Thereafter, the Si substrate 34 is etched using this mask to form grooves 72 in the Si substrate 34 (FIG. 7C). There are wet etching and dry etching as etching types. In this case, dry etching is preferable because a hole having a high aspect ratio is formed. Thereafter, tungsten (W) 73 is embedded in the groove 72 by using a PVD (Physical Vapor Deposition) method (FIG. 7D).

  Thereafter, the mask 71 on the surface of the Si substrate 34 is removed (FIG. 7E). For example, when the mask 71 is formed of a resist, it can be selectively removed using a resist stripping solution. Next, a quartz substrate 75 is attached to the surface of the Si substrate 34 on which the tungsten 73 is embedded using a temporary adhesive 74 (FIG. 7F). Instead of the quartz substrate 75, for example, a Si substrate or another substrate may be used. The temporary fixing adhesive 74 can be easily peeled off later with, for example, a solution or ultraviolet light, and preferably has no residue on the upper surface of the tungsten 73 after peeling. Has been.

  Next, the back surface of the Si substrate 34 is polished using the quartz substrate 75 as a support. Since the thickness of the Si substrate 34 is generally about 500 to 800 μm, this is polished to a thickness of about 50 μm, for example (FIG. 7G). Then, by removing the temporary fixing adhesive 74, the stone substrate 75 and the Si substrate 34 can be separated (FIG. 7 (h)).

  Next, a method for processing the insulating layer (here, the alumina substrate) 13 will be described with reference to FIG. First, an alumina substrate 13 having a desired thickness (42 μm thickness) is prepared, and a mask 77 is applied and patterned (FIG. 8A). The mask pattern is patterned so that both the position corresponding to the via hole in which the thermoelectric material is embedded and the position corresponding to the via hole in which tungsten is embedded are opened.

  Next, the opening of this mask 77 is etched, and a groove 78 is dug to approximately half the thickness of the alumina substrate 13 (FIG. 8B). Etching uses dry etching so that the opening of the mask 77 has the same width as the groove as much as possible.

  From this, a Cr film and an Au film are sequentially formed, and a metal film (Cr / Au film) 26 is obtained. Examples of the film forming method include vapor deposition or sputtering, and the film thickness is, for example, about 20 nm for the Cr film and about 200 nm for the Au film (FIG. 8C). Thereafter, by removing the mask 77, the Cr / Au film 26 is formed only at the bottom of the hole provided in the alumina substrate 13 (FIG. 8D).

  Next, the mask 79 is applied again, and this time, a pattern having an opening 80 for embedding the N-type thermoelectric material is manufactured (FIG. 8E). Then, the N-type thermoelectric material 14a is embedded in the opening 80 (FIG. 8F). The N-type thermoelectric material 14a is usually embedded by a plating method.

  After removing the mask 79, the mask 81 is applied again, and a pattern having an opening 82 for embedding the P-type thermoelectric material 12b is manufactured (FIG. 8G).

  Then, the P-type thermoelectric material 12b is embedded in the opening 82 (FIG. 8 (h)). The P-type thermoelectric material 12b is usually embedded by a plating method.

  After removing the mask 81, the mask 83 is applied again, and this time, a pattern having an opening 84 of the signal TSV is manufactured (FIG. 8 (i)). Then, a metal 25 such as tungsten is embedded in the opening 84 (FIG. 9A). The metal 25 is formed by a PVD method or the like.

  Next, after removing the mask 83, this time, a mask 85 is applied to the back surface of the substrate, and patterning is performed (FIG. 9B). The mask pattern is patterned so that both positions corresponding to via holes in which P-type and N-type thermoelectric materials are embedded and positions corresponding to via holes in which tungsten is embedded are opened.

  Next, the opening of the mask 85 is etched, and a groove 86 is dug until the Cr / Au film 26 previously formed is exposed to the surface to approximately half the thickness of the alumina substrate 13 (FIG. 9C). . For the etching, dry etching is used so that the opening of the mask is as large as the width of the groove 86 as much as possible.

  Next, a process of embedding a P-type thermoelectric material, an N-type thermoelectric material, and a metal in the groove 86 is performed in the same manner as the processes from FIG. 8E to FIG. 8I and FIG. 9A. That is, after a resist pattern 87 having an opening 88 for embedding a P-type thermoelectric material is manufactured (FIG. 9D), the P-type thermoelectric material 12a is embedded in the opening 88 (FIG. 9E). Thereafter, after a resist pattern 89 having an opening 90 for embedding the N-type thermoelectric material is manufactured (FIG. 9F), the N-type thermoelectric material 14b is embedded (FIG. 9G). Next, a resist pattern 91 having an opening 92 of the signal TSV is manufactured (FIG. 9H). Then, a conductive metal, for example, a metal 25 such as W is embedded in the opening 92 (FIG. 9I). Finally, the resist pattern 91 is removed (FIG. 9 (j)).

  Si substrate 35 processed in the same manner as Si substrate 34 processed in FIGS. 7A to 7H, and processed in FIGS. 8A to 8I and FIGS. 9A to 9J. An alumina substrate 17 processed in the same manner as the alumina substrate 13 is prepared. In addition, one Si substrate 36 installed at the top is prepared. By stacking these and performing chip bonding, a 3D-IC is formed as shown in FIG. Chip bonding is performed, for example, by heating to about 200 ° C. and applying pressure to the stacked substrates. In the gap between the chips, an underfill or the like is finally inserted to fill the gap.

  In this example, the 3D-IC is formed using three Si substrates and two alumina substrates, but it is clear that there is no particular limitation on the number.

  When the 3D-IC manufactured in this way is assembled into, for example, a flip chip package, it has a cross section like the electronic device shown in FIG. The electronic device of FIG. 10B has the same configuration as that of FIG. 6 except that the number of vias 25 is different.

  FIG. 11 is a cross-sectional view illustrating the electronic device of the third embodiment. In addition, description is abbreviate | omitted about the structure similar to 2nd Embodiment.

  In the electronic device according to the third embodiment, a joint portion between each first material and each second material is provided between a pair of semiconductor substrates provided above and below each thermoelectric element. However, it is only necessary that at least a part of the junctions 26a and 26b of the thermoelectric elements 20a and 20b is in contact with the insulating layer 13, and at least a part of the junctions 27a and 27b of the thermoelectric elements 40a and 40b is an insulating layer. 17 may be in contact. Further, the current inlet of the first material is in contact with one semiconductor substrate, and the current outlet of the second material is in contact with the other semiconductor substrate. For example, the current inlet 28a of the thermoelectric element 20a is embedded in and in contact with the semiconductor substrate 34. The current outlet 29b of the thermoelectric element 20b is embedded in and in contact with the semiconductor substrate 34.

  In the electronic device of the third embodiment, in the thermoelectric element, the interface of the junction (metal layer) is located not at the center of the pair of semiconductor substrates but at the interface between the semiconductor substrate and the insulating layer. Therefore, the heat dissipation efficiency here is slightly inferior to that of the second embodiment. However, in the third embodiment, each via provided in the insulating layer is made of one material except for the Cr / Au layer (metal layer), and the via provided in the semiconductor substrate excludes the Cr / Au layer (metal layer). It consists of one or two kinds of materials. For example, it is easier to embed a plurality of materials in a semiconductor substrate made of Si, for example, than to embed a plurality of materials in a via hole of an insulating layer that is hard and difficult to process, such as alumina. Therefore, the electronic device of the third embodiment is highly reliable and can be manufactured at low cost.

  12-15 is sectional drawing of the laminated body in the middle of manufacture of the electronic device of 3rd Embodiment. Note that a description of the same steps as those of the electronic device manufacturing method according to the second embodiment will be omitted.

  FIG. 12A shows a Si substrate 34 having an electronic circuit 31 disposed on the surface, which is obtained through a general Si process. A material for the mask 92 is formed thereon, and further patterned by photolithography to form a mask 92 (FIG. 12B). The method for forming the mask 92 is the same as that for the mask 71 and the like.

  Thereafter, the Si substrate 34 is etched using the mask 92 to form a groove 93 in the Si substrate 34 (FIG. 12C). The etching method is the same as the etching of the groove 72. A Cr film and an Au film to be the metal layer 26 are formed from above. Examples of the film forming method include vapor deposition or sputtering, and the film thickness is, for example, about 20 nm for the Cr film and about 200 nm for the Au film (FIG. 12D). Thereafter, the mask 92 is removed (FIG. 12E).

  Next, the mask 94 is applied again, and this time, a pattern having an opening 95 for embedding the N-type thermoelectric material is manufactured (FIG. 12F). Then, the N-type thermoelectric material 12b is embedded based on the mask 94 (FIG. 12G). Usually, it is embedded by plating. The height of the N-type thermoelectric material 12b is approximately half the depth of the opening 95 (thickness: 10 μm). The remaining opening 95 is filled with a metal 25b such as tungsten (W) (FIG. 12H). As a method for embedding W, a PVD method or the like is used.

  After removing the mask 94, the mask 96 is applied again, and a pattern having an opening 97 for embedding the P-type thermoelectric material 12a is produced (FIG. 12 (i)). Then, the P-type thermoelectric material 12b is embedded based on the mask 96 (FIG. 12 (j)). The P-type thermoelectric material 12a is also usually buried by a plating method. The height of the P-type thermoelectric material 12a is approximately half the depth of the opening 97 (thickness 10 μm). A metal 25a such as W is embedded in the remaining opening 97 (FIG. 12 (k)). As a method for embedding W, a PVD method or the like is used.

  After removing the mask 96, the mask 98 is then applied again, and this time, a pattern having the opening 99 of the signal TSV is manufactured (FIG. 13A). Then, for example, a metal 25 such as W is embedded based on the mask 96 (FIG. 13B). As a method for embedding W, a PVD method or the like is used.

  Thereafter, the mask 96 on the substrate surface is removed (FIG. 13C). If it is a resist, it is easy to selectively remove it using a resist stripping solution. Then, the quartz substrate 101 is pasted using the temporary fixing adhesive 100 (FIG. 13D). The back surface of the Si substrate 34 is polished using the quartz substrate 101 side as a support. Since the thickness of the Si substrate 34 is generally about 500 to 800 μm, this is polished to a thickness of about 50 μm, for example (FIG. 13E). Then, by removing the temporary fixing adhesive 100, the stone substrate 101 and the Si substrate 34 can be separated (FIG. 13 (f)).

  Next, a processing procedure of the insulating layer (here, an alumina substrate) 13 is shown. First, an alumina substrate 13 having a desired thickness (42 μm thickness) is prepared, and a quartz substrate 103 is pasted using a temporary fixing adhesive 104 (FIG. 14A). Then, a mask 105 is applied and patterning is performed (FIG. 14B). The mask pattern is patterned so that both the position corresponding to the via hole in which the thermoelectric material is embedded and the position corresponding to the via hole in which tungsten is embedded are opened.

  Next, the opening of the mask 105 is etched, and here, the groove 106 is opened to a depth at which the temporary fixing adhesive 104 is exposed (FIG. 14C). For the etching, dry etching is used so that the opening of the mask 105 has the width of the groove 106 as it is.

  A metal film (Cr / Au film) 26 is formed from above. Examples of the film forming method include vapor deposition or sputtering, and the film thickness is, for example, about 20 nm for the Cr film and about 200 nm for the Au film (FIG. 14D). Thereafter, by removing the mask 105, the metal film 26 is formed only at the bottom of the groove 106 provided in the insulating layer 13 (FIG. 14E).

  Next, a mask 108 is applied, and a pattern having an opening 109 for embedding the P-type thermoelectric material 14b is manufactured (FIG. 14F). Then, the P-type thermoelectric material 14b is embedded based on the mask 108 (FIG. 14G). The P-type thermoelectric material 14b is usually embedded by a plating method.

  After removing the mask 108, a mask 110 is applied next, and a pattern having an opening 111 for embedding the N-type thermoelectric material 14a is manufactured (FIG. 14H). Then, an N-type thermoelectric material 14a is embedded based on the mask 110 (FIG. 15A). The N-type thermoelectric material 14a is usually embedded by a plating method.

  After removing the mask 110, the mask 112 is then applied again, and this time, a pattern having the opening 113 of the signal TSV is manufactured (FIG. 15B). Then, a metal 25 such as W is embedded based on the mask 112 (FIG. 15C). The metal 25 is formed by a PVD method or the like. Finally, by removing the mask 112, the processing of the insulating layer 13 is completed (FIG. 15D).

  Finally, the Si substrate 35 processed in the same manner as the Si substrate 34 manufactured in FIGS. 12A to 13F, and the alumina substrate 13 processed in FIGS. 14A to 15D. An alumina substrate 17 processed in the same manner as described above is prepared. In addition, one Si substrate 36 installed at the top is prepared. A 3D-IC is formed by stacking these and chip bonding. Chip bonding is performed in the same manner as in the first embodiment.

  In this example, the 3D-IC is formed using three Si chips and two heat conductive substrates, but it is clear that there is no particular limitation on the number.

  When the 3D-IC manufactured in this way is assembled into, for example, a flip chip package, it has a cross section like the electronic device shown in FIG.

  FIG. 16 is a cross-sectional view illustrating a first modification of the electronic device according to the second embodiment. The description of the same configuration as that of the second embodiment is omitted. In the electronic device of this modification, the thermoelectric elements 20a, 20b, 40a, 40b are composed of a plurality of small-diameter thermoelectric elements arranged in parallel. The vias 25a and 25b connected to the thermoelectric element and embedded in the semiconductor substrate 34, the vias 25c and 25d connected to the thermoelectric element and embedded in the semiconductor substrate 35, and the signal vias 25 are arranged in parallel. It consists of small diameter vias. The diameters of the small diameter vias and the small diameter thermoelectric elements are, for example, 1 μmφ. Further, although two vias and two thermoelectric elements are shown, the quantity is not limited. For example, a pattern of 5 vertical × 5 horizontal may be formed in the in-plane direction. According to this modification, heat can be radiated from the semiconductor substrate even if some small-diameter thermoelectric elements are disconnected. Further, the thermoelectric element and the via can be formed in a short time, and the manufacturing cost is further suppressed.

  The characteristics of the thermoelectric element are better as the thermal conductivity of the thermoelectric material constituting it is lower. Therefore, thermal conductivity can be lowered by making the diameter of the thermoelectric material smaller than the average grain size. That is, if the diameter of the thermoelectric material is made smaller than the average grain size, a large amount of lattice scattering that conducts heat on the grain size and via side surface occurs, contributing to a decrease in thermal conductivity and improving the cooling efficiency of the semiconductor substrate. The average grain size of the thermoelectric material is usually about several μm. In a thin thermoelectric element as in this modification, the diameter of the via hole (1 μmφ) is smaller than the grain size of the material constituting the thermoelectric element. At this time, since the material constituting the thermoelectric element has a so-called bamboo structure in which the crystal grain boundaries are arranged in a bamboo knot shape, the thermal conductivity of the thermoelectric material is lowered. On the other hand, in the case of the second embodiment, the diameter of the via hole (20 μmφ) is larger than the grain size of the material constituting the thermoelectric element, and the material constituting the thermoelectric element is a so-called stone wall-like polycrystal, which is a thermoelectric material having a bamboo structure. It becomes larger than thermal conductivity.

  Although there are various methods for measuring the average grain size, one of the methods suitable for the thermoelectric material handled in the present embodiment is EBSD (Electron Back Scatter Diffraction Pattern). The measuring method by a method is mentioned. In this method, the sample can be irradiated with an electron beam, each crystal grain can be discriminated from the Kikuchi line obtained by the reflected electrons, and the grain boundary can be clearly determined from the boundary line. In addition, since a large number of grains can be observed with this method, a statistically accurate value can be obtained. Therefore, the size (area) of each crystal grain and the overall distribution can be obtained from the obtained results. As in this embodiment, in a thermoelectric material embedded in a via hole having a depth of about several tens of μm, it is considered that there are a plurality of grains in the depth direction. Therefore, the average grain size is as follows. It is appropriate to use the area circle equivalent diameter calculated from the average area.

When the via hole has a small diameter as described above, the thermoelectric material and the metal can be embedded by, for example, a supercritical method. Here, in the supercritical method, for example, a substrate having a hole is immersed in supercritical CO _2, and after CO ₂ is sufficiently immersed in the hole, the precursor of the thermoelectric material is dissolved to enter the hole. This is a method of filling a hole with a thermoelectric material having a bamboo structure by diffusing a precursor of a thermoelectric material into CO ₂ and further vaporizing supercritical CO ₂ in the hole. By the supercritical method, for example, a thermoelectric material having a bamboo structure can be embedded in a groove having a high aspect ratio exceeding 100.

  FIG. 17A is a cross-sectional view showing a second modification of the electronic device of the second embodiment. The description of the same configuration as that of the second embodiment is omitted. The electronic device of this modification is incorporated in an FBGA (Fine pitch Ball Grid Array) package. In this modification, the semiconductor substrates 34 to 36 are arranged such that the electronic circuits 31 to 33 face upward. Instead of forming vias in the semiconductor substrate 34, a plurality of vias 25 are formed in the semiconductor substrate 36. A gold wire 141 formed by wire bonding is provided on the upper surface of the semiconductor substrate 36 as a wiring to the outside. The gold wire 141 is appropriately electrically connected to a plurality of solder bumps 53 provided on the opposite side across the package substrate 52. FIG. 17B is a perspective view showing an example of the insulating layers 13 and 17 used in the second modification of the electronic device of the second embodiment. As shown in FIG. 17B, a notch portion 142 is provided in each insulating layer between the semiconductor substrates. The gold wire 141 is wired so that the gold wire 141 passes through the notch portion 142.

  The FBGA package 141 is made of, for example, a mold resin. The insulating layer 13 may be exposed to the outside in order to penetrate the FBGA package and promote heat dissipation from each semiconductor substrate. The insulating layer 13 may have a mechanism that penetrates the FBGA package, protrudes to the outside, and air-cools or water-cools the protruding portion.

  FIG. 18 is a cross-sectional view showing a third modification of the electronic device of the second embodiment. The description of the same configuration as that of the second modification of the second embodiment is omitted. In this modified example, the area of the main surface is smaller as the semiconductor substrate is disposed above. Further, in this modification, vias for connecting the electronic circuits 31 to 33 and the outside are not provided, but instead, signal transmission pads 151 provided in each semiconductor substrate and connected to each electronic circuit. In addition, a gold wire 152 for signal transmission connected thereto is provided. The gold wire 152 is appropriately electrically connected to a plurality of solder bumps 53 provided on the opposite side across the package substrate 52. Further, a gold wire 154 is connected to the upper surface of the semiconductor substrate 36 as an external wiring for supplying current to the thermoelectric elements 20a, 20b, 40a, and 40b. The gold wire 154 is appropriately electrically connected to a plurality of solder bumps 53 provided on the opposite side across the package substrate 52. The gold wires 152 and 154 are concentrated on a part of the four sides of the package. The insulating layers 13 and 17 extend from the portions in contact with the semiconductor substrates disposed above and below in the direction in which the gold wires 152 and 154 are not disposed. The cooling means for the insulating layers 13 and 17 is the same as that of the second modification of the electronic device of the second embodiment. Since no signal TSV is provided, the number of process steps is greatly reduced, and it is not necessary to produce notches or the like in the heat conductive substrate, so that the cost can be reduced. In this modification, the gold wire 154 extends from the semiconductor substrate 36 toward the package substrate 52. For example, the gold wire 154 passes from the upper surface of the semiconductor substrate 36 to the semiconductor substrate 34 via a relay electrode (not shown). Then, it may be electrically connected to the package substrate 52.

FIG. 19 is a cross-sectional view illustrating a fourth modification of the electronic device of the second embodiment. The description of the same configuration as that of the second embodiment is omitted. In this modification, the diameter d1 of the thermoelectric element 20a is larger than the diameter d2 of the thermoelectric element 40a. Further, the diameter d1 of the thermoelectric element 20b is larger than the diameter d2 of the thermoelectric element 40b. Assuming that the circuit current flowing through the uppermost electronic circuit 33 is i ₁ , the circuit current flowing through the intermediate electronic circuit 32 is i ₂ , and the circuit current flowing through the lowermost electronic circuit 31 is i ₃ , the electronic circuit 32 and the electronic circuit 33 and sandwiched between thermoelectric elements 40a, current _i 1 + _{i 2} flows respectively to 40b, the electronic circuit 31 and the electronic circuit 32 and sandwiched between the thermoelectric elements 20a, current _{i 1,} respectively flows in 20b. That is, the thermoelectric element having a larger flowing current has a larger diameter. Since Joule heat generated when a current flows through the thermoelectric element can be suppressed, the cooling efficiency of the semiconductor substrate is improved.

  FIG. 20 is a cross-sectional view illustrating a fifth modification of the electronic device of the second embodiment. The description of the same configuration as that of the second embodiment is omitted. In this modification, the thermoelectric element 40a, the electronic circuit 33, and the thermoelectric element 40b are connected in series to the power source 175, and the thermoelectric element 20a, the electronic circuit 32, and the thermoelectric element 20b are connected in series to the power source 175. Further, temperature sensors 171, 172, and 173 are provided on the semiconductor substrates 34, 35, and 36. The temperature sensors 171, 172, and 173 are each connected to the control unit 174. The control unit 174 detects the temperature of the temperature sensors 171 to 173, and according to the detected temperature, the current flowing through the thermoelectric element 40a, the electronic circuit 33, and the thermoelectric element 40b, the thermoelectric element 20a, the electronic circuit 32, and the thermoelectric element The current flowing through 20b is individually controlled. The electronic device of this modification can be controlled so that the temperature of each electronic circuit is always equal to or lower than a certain temperature, for example. The control unit 174 may be incorporated inside the electronic device instead of being provided outside the electronic device. For example, the temperature sensors 171, 172, and 173 are provided on the semiconductor substrates 34, 35, and / or 36. You may provide the control part which detects and controls separately the electric current sent through the thermoelectric element 40a, the electronic circuit 33, and the thermoelectric element 40b, and the electric current sent through the thermoelectric element 20a, the electronic circuit 32, and the thermoelectric element 20b.

  In the fifth modification of the electronic device of the second embodiment shown in FIG. 20, for example, a plurality of thermoelectric elements are provided between the semiconductor substrates 35 and 36, and the semiconductor substrate is in the vicinity of the plurality of thermoelectric elements. A temperature sensor may be arranged on each of 36. Each temperature sensor is connected to the control unit 174. The control part 174 can detect the temperature of the temperature sensor provided in the vicinity of each thermoelectric element, and can send an electric current separately to each thermoelectric element according to the detected temperature. When a temperature distribution is generated in the plane of the semiconductor substrate, such an electronic device can suppress a local temperature rise and improve the reliability and characteristics of the entire electronic device.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

Here, the detailed features of the present invention will be described again.
(Appendix 1)
A first cooled substrate;
A second cooled substrate facing the first cooled substrate;
A first material that is endothermicly bonded to the first substrate to be cooled; and a second material that is endothermicly bonded to the second substrate to be cooled; and the first material to be cooled between the first substrate to be cooled and the second substrate to be cooled. An electronic device comprising: a thermoelectric element in which a first material and the second material are heat-bonded.
(Appendix 2)
The electronic device according to appendix 1, wherein the second substrate to be cooled includes an electronic circuit connected in series with the thermoelectric element.
(Appendix 3)
The electronic device according to appendix 1 or 2, wherein the first material is a P-type thermoelectric material and the second material is an N-type thermoelectric material.
(Appendix 4)
Current flows from the endothermic junction between the first substrate to be cooled and the first material to the endothermic junction between the second substrate to be cooled and the second material through the first material and the second material. The electronic device as set forth in Appendix 3, wherein
(Appendix 5)
The electron according to any one of appendices 1 to 4, wherein a diameter of the thermoelectric element in a direction substantially parallel to the substrate to be cooled is smaller than an average grain size of the first material or the second material. apparatus.
(Appendix 6)
Furthermore, any one of Supplementary notes 1 to 5, further comprising a heat radiating portion thermally connected to a joint portion between the first material and the second material and extending in an in-plane direction of the substrate to be cooled. An electronic device according to 1.
(Appendix 7)
The electronic device according to any one of appendices 1 to 6, further comprising another thermoelectric element connected to an external power source in parallel with the thermoelectric element.
(Appendix 8)
And a temperature detecting device provided in the vicinity of the thermoelectric element on the first substrate to be cooled.
Appendices 1 to 7, wherein external current control units respectively connected to the temperature detection device and the thermoelectric element control the current flowing through the thermoelectric element according to the temperature detected by the temperature detection device. The electronic device according to any one of the above.
(Appendix 9)
Furthermore, a temperature detection device provided in the vicinity of the thermoelectric element on the first cooled substrate,
A current control unit provided on the first substrate to be cooled, connected to the temperature detection device and the thermoelectric element, and configured to control a current flowing through the thermoelectric element according to a temperature detected by the temperature detection device; The electronic device according to any one of appendices 1 to 7, characterized by:
(Appendix 10)
Further, the other first material and the other second material are heat-bonded above the second cooled substrate, and one of the other first material or the other second material is the second cooled material. A second thermoelectric element for endothermic bonding to the substrate;
Any one of Supplementary notes 1 to 9, further comprising: a third substrate to be cooled which is provided on the second thermoelectric element and the other of the other first materials or the other second materials is subjected to heat absorption bonding. The electronic device as described in any one.
(Appendix 11)
The thermoelectric element and the second thermoelectric element are connected in series so that the potential of the thermoelectric element is larger than the potential of the second thermoelectric element, and the diameter of the thermoelectric element in a direction substantially parallel to the first cooled substrate. 11. The electronic device according to appendix 10, wherein the second thermoelectric element has a diameter that is larger than a diameter in a direction substantially parallel to the first substrate to be cooled.
(Appendix 12)
Preparing a first cooled substrate and a second cooled substrate;
Electrically bonding the first material and the second material;
Placing one of the first material and the second material in contact with the first substrate to be cooled or in the vicinity of the first substrate to be cooled;
Placing the other of the first material and the second material in contact with the second substrate to be cooled or in the vicinity of the second substrate to be cooled;
A method for manufacturing an electronic device, comprising:
(Appendix 13)
Furthermore, a heat radiating portion that supports the first material and the second material and releases the heat received from the joining of the first material and the second material to the outside is provided with the first cooled substrate and the first material. The manufacturing method of the electronic device according to appendix 12, which includes a step of forming between the two substrates to be cooled.
(Appendix 14)
The joining step includes
A step of forming a plate-like body that is made of a material having a higher thermal conductivity than the first material and the second material and serves as the heat dissipation part;
Forming a via hole in the plate-like body;
Forming a first layer made of one of the first material and the second material in the via hole;
The method of manufacturing an electronic device according to appendix 12 or 13, further comprising: forming a second layer made of the other of the first material and the second material on the first layer.
(Appendix 15)
The joining step includes
Forming a recess in the first substrate to be cooled;
Forming a first layer made of one of the first material and the second material in the recess;
A step of forming a plate-like body that is made of a material having a higher thermal conductivity than the first material and the second material and serves as the heat dissipation part;
Forming a via hole in the plate-like body;
The method of manufacturing an electronic device according to appendix 12 or 13, further comprising: forming a second layer made of the other one of the first material and the second material in the via hole.

DESCRIPTION OF SYMBOLS 10 Electronic device 12, 16 1st material 13, 17 Radiating part 14, 18 2nd material 21, 22, 23, 24 Via hole 20 Thermoelectric element 25, 25a-25d Via 26, 27 Metal layer 28, 48 Current inflow end 29 49 Outflow end of current 31-33 Electronic circuit 34-36 Semiconductor substrate (Si substrate)
37, 38, 57, 58 Via hole 41, 42 TIM
45 Heat spreader 51, 53 Solder bump 52 Package substrate 61 Power supply 62 Control circuit 63 Power supply for cooling 71, 77, 79, 81, 83, 85, 87, 89, 91, 92, 94, 96, 98, 105, 108, 110 112 Mask (resist pattern)
73 Tungsten 74, 100, 104 Temporary adhesive 75, 101, 103 Quartz substrate 72, 78, 86, 93, 106 Groove 80, 82, 84, 88, 90, 92, 95, 97, 99, 109, 111, 113 opening 141 gold wire 142 notch 151 transmission pad 152, 154 gold wire 171 to 173 temperature sensor 174 control unit 175 power supply

Claims (6)

A first cooled substrate;
A second cooled substrate facing the first cooled substrate;
A first material that is endothermicly bonded to the first substrate to be cooled; and a second material that is endothermicly bonded to the second substrate to be cooled; and the first material to be cooled between the first substrate to be cooled and the second substrate to be cooled. An electronic device comprising: a thermoelectric element in which a first material and the second material are heat-bonded.   The electronic device according to claim 1, wherein the second cooled substrate includes an electronic circuit connected in series with the thermoelectric element.   The electronic device according to claim 1, wherein the first material is a P-type thermoelectric material, and the second material is an N-type thermoelectric material. Further, the other first material and the other second material are heat-bonded above the second cooled substrate, and one of the other first material or the other second material is the second cooled material. A second thermoelectric element for endothermic bonding to the substrate;
The third to-be-cooled substrate provided on the second thermoelectric element and having the other first material or the other second material endothermically bonded to each other. The electronic device according to any one of the above.   The thermoelectric element and the second thermoelectric element are connected in series so that the potential of the thermoelectric element is larger than the potential of the second thermoelectric element, and the diameter of the thermoelectric element in a direction substantially parallel to the first cooled substrate. 5. The electronic device according to claim 4, wherein a diameter of the second thermoelectric element is larger than a diameter in a direction substantially parallel to the first substrate to be cooled. Preparing a first cooled substrate and a second cooled substrate;
Electrically bonding the first material and the second material;
Placing one of the first material and the second material in contact with the first substrate to be cooled or in the vicinity of the first substrate to be cooled;
Placing the other of the first material and the second material in contact with the second substrate to be cooled or in the vicinity of the second substrate to be cooled;
A method for manufacturing an electronic device, comprising: