KR20170109328A - Semiconductor Package - Google Patents

Abstract

Disclosed is a semiconductor package that emits heat efficiently from the inside of a semiconductor package including a semiconductor chip to the outside and relieves stress concentrated in a part. The semiconductor package according to the present disclosure includes at least one first semiconductor chip which has a plurality of first penetration electrodes and electrically and physically stacked via the plurality of first penetration electrodes, a second semiconductor chip which is disposed on the at least one first semiconductor chip and including a plurality of second penetration electrodes electrically connected to the plurality of first penetration electrodes, and an insulating thermoelectric pattern layer in thermal contact with the second penetration electrodes.

Description

[0001]

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of semiconductor chips stacked using through electrodes and a semiconductor chip disposed adjacent thereto.

Electronic devices are becoming smaller, lighter, and larger in capacity depending on the rapid development of the electronic industry and the demands of users. Accordingly, a semiconductor package for stacking a plurality of semiconductor chips using through electrodes has been developed.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the reliability and performance of a semiconductor package in which a plurality of semiconductor chips are stacked through through electrodes.

In order to achieve the above object, a semiconductor package according to an aspect of the technical idea of the present disclosure includes a plurality of first penetrating electrodes, at least one electrically and physically stacked one through the plurality of first penetrating electrodes A second semiconductor chip disposed on the at least one first semiconductor chip and including a plurality of second penetrating electrodes electrically connected to the plurality of first penetrating electrodes, And an insulating thermoelectric pattern layer in thermal contact with the penetrating electrodes.

According to an exemplary embodiment of the present disclosure, the thermoelectric pattern layer may be integrally formed to cover the upper portions of the plurality of second penetrating electrodes together.

According to an exemplary embodiment of the present disclosure, the thermoelectric conversion layer may have a plurality of thermoelectric patterns spaced apart from each other to cover the upper portions of the plurality of second penetrating electrodes.

According to an exemplary embodiment of the present disclosure, the second semiconductor chip comprises a first region in which the plurality of second penetrating electrodes are present and a second region in which the plurality of second penetrating electrodes are present, Wherein the thermoelectric pattern layer has a plurality of first thermoelectric patterns covering the exposed upper portions of the plurality of second penetrating electrodes and a second thermoelectric pattern spaced apart from the first thermoelectric pattern and covering an upper portion of the second region . ≪ / RTI >

According to an exemplary embodiment of the present disclosure, the first thermoelectric pattern and the second thermoelectric pattern may have a top surface of the same level.

According to an exemplary embodiment of the present disclosure, a plurality of dummy pads may be located on the second region, and the second thermoelectric pattern may cover the plurality of dummy pads.

According to an exemplary embodiment of the present disclosure, the second semiconductor chip comprises a first region in which the plurality of second penetrating electrodes are present and a second region in which the plurality of second penetrating electrodes are not present, And at least some of the plurality of first thermoelectric patterns extend from the first region to the second region. The plurality of first thermoelectric patterns may include a plurality of first thermoelectric patterns each covering an upper portion of the penetrating electrodes, and at least some of the plurality of first thermoelectric patterns extend from the first region to the second region.

According to an exemplary embodiment of the present disclosure, the thermoelectric conversion layer may be formed of any one of diamond, boron nitride, and graphite.

A semiconductor package according to an aspect of the present disclosure includes a package base substrate, at least one first semiconductor chip electrically and physically stacked via the plurality of first penetration electrodes, A second semiconductor chip disposed on the first semiconductor chip and including a plurality of second penetrating electrodes electrically connected to the plurality of first penetrating electrodes, and a second semiconductor chip disposed in thermal contact with the second penetrating electrodes A sub semiconductor package including a thermoelectric pattern layer, and a heat emitting member disposed on the thermoelectric pattern layer and in thermal contact with the thermoelectric pattern layer.

According to an exemplary embodiment of the present disclosure, a thermal interface material may be further disposed between the heat emitting member and the sub semiconductor package.

The semiconductor package according to the technical idea of the present disclosure effectively dissipates the internal heat of the laminated semiconductor chip structure to prevent deterioration of the performance of the semiconductor chip due to heat generation and disperses the stress concentration of the semiconductor chip, have.

1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;
2 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;
3 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;
4A is a plan view showing a semiconductor package according to an exemplary embodiment of the present disclosure;
4B is a cross-sectional view illustrating a portion of a semiconductor package according to an exemplary embodiment of the present disclosure;
5A is a top view of a semiconductor package according to an exemplary embodiment of the present disclosure;
5B is a cross-sectional view illustrating a portion of a semiconductor package according to an exemplary embodiment of the present disclosure;
6A is a top view of a semiconductor package according to an exemplary embodiment of the present disclosure;
6B is a cross-sectional view illustrating a portion of a semiconductor package according to an exemplary embodiment of the present disclosure;
7A is a top view of a semiconductor package according to an exemplary embodiment of the present disclosure;
7B is a cross-sectional view illustrating a portion of a semiconductor package according to an exemplary embodiment of the present disclosure;
8 is a top view of a semiconductor package according to an exemplary embodiment of the present disclosure;
9A is a plan view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;
9B is a cross-sectional view illustrating a portion of a semiconductor package according to an exemplary embodiment of the present disclosure;
10 is a plan view showing a semiconductor package according to an exemplary embodiment of the present disclosure;
11 is a top view of a semiconductor package according to an exemplary embodiment of the present disclosure;
12 schematically shows a configuration of a semiconductor package according to an exemplary embodiment of the present disclosure;

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood, however, that the description of the embodiments is provided to enable the disclosure of the invention to be complete, and will fully convey the scope of the invention to those skilled in the art to which the present invention pertains. In the accompanying drawings, the components are enlarged for the sake of convenience of explanation, and the proportions of the components can be exaggerated or reduced.

It is to be understood that when an element is referred to as being "on" or "tangent" to another element, it is to be understood that other elements may directly contact or be connected to the image, something to do. On the other hand, when an element is described as being "directly on" or "directly adjacent" another element, it can be understood that there is no other element in between. Other expressions that describe the relationship between components, for example, "between" and "directly between"

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. The word "comprising" or "having ", when used in this specification, is intended to specify the presence of stated features, integers, steps, operations, elements, A step, an operation, an element, a part, or a combination thereof.

The terms used in the embodiments of the present invention may be interpreted as commonly known to those skilled in the art unless otherwise defined.

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure;

Referring to FIG. 1, the semiconductor package 10 may include a package base substrate 121 and a laminated structure 100. The package base substrate 121 may be, for example, a printed circuit board, a ceramic substrate, or an interposer.

When the package base substrate 121 is a printed circuit board, the package base substrate 121 may include a substrate base, and upper and lower pads (not shown) and lower pads (not shown) formed on the upper and lower surfaces, respectively. The upper surface pad and the lower surface pad may be respectively exposed by a solder resist layer (not shown) covering upper and lower surfaces of the substrate base. The substrate base may be made of at least one material selected from phenol resin, epoxy resin, and polyimide. For example, the substrate base can be formed of FR4, tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, bismaleimide triazine (BT), thermalt ), A cyanate ester, a polyimide, and a liquid crystal polymer. The top and bottom pads may be made of copper, nickel, stainless steel, or beryllium copper. Internal wiring (not shown) electrically connected to the upper surface pad and the lower surface pad may be formed in the substrate base. The upper surface pad and the lower surface pad may be portions exposed by the solder resist layer, respectively, of the patterned circuit wiring after the copper foil is applied to the upper and lower surfaces of the substrate base.

When the package base substrate 121 is an interposer, the package base substrate 121 includes a substrate base made of a semiconductor material and a top pad (not shown) and a bottom pad (not shown) respectively formed on the top and bottom surfaces of the substrate base . The substrate base may be formed, for example, from a silicon wafer. Internal wirings (not shown) may be formed on the top, bottom, or inside of the substrate base. In addition, through holes (not shown) for electrically connecting the upper surface pad and the lower surface pad may be formed in the substrate base.

An external connection terminal 122 may be attached to a lower surface of the package base substrate 121. The external connection terminal 122 may be attached, for example, on the lower surface pad. The external connection terminal 122 may be, for example, a solder ball or a bump. The external connection terminal 122 can electrically connect the semiconductor package 10 and the external device.

The laminated structure 100 may include the laminated semiconductor chip structures 110 sequentially stacked. In the laminated semiconductor chip structure 110, a plurality of semiconductor chips 110a, 110b, 110c, and 110d may be stacked in a vertical direction. The stacked semiconductor chip structure 110 includes a plurality of first semiconductor chips 110b, 110c, and 110d physically and electrically stacked via through electrodes, a second semiconductor chip 110b, 110c, and 110d positioned on the first semiconductor chip, And may include a semiconductor chip 110a. The semiconductor substrate and the semiconductor elements formed as the plurality of semiconductor chips 110a, 110b, 110c, and 110d included in the laminated semiconductor chip structure 110 are similar to each other, and a detailed description thereof will be made as the second semiconductor chip 110a. The active surface of each of the plurality of semiconductor chips 110a, 110b, 110c, and 110d included in the laminated semiconductor chip structure 110 may face the base substrate 121. [ In the specification of the present invention, the term 'plurality of semiconductor chips' refers to semiconductor chips stacked in a vertical direction so as to form 'one laminated semiconductor chip structure'.

The laminated semiconductor chip structure 110 may be, for example, a memory semiconductor chip. The memory semiconductor chip may be a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM) (Ferroelectric Random Access Memory) or RRAM (Resistive Random Access Memory).

At least one of the laminated semiconductor chip structures 110 may be a logic semiconductor chip and the remainder may be a memory semiconductor chip. For example, the lowermost semiconductor chip 110d of the laminated semiconductor chip structures 110 may be a logic semiconductor chip, and the remaining semiconductor chips 110a, 110b, and 110c may be memory semiconductor chips. For example, the lowermost semiconductor chip 110d of the laminated semiconductor chip structure 110 may be a controller chip for controlling the remaining semiconductor chips 110a, 110b, and 110c, and the remaining semiconductor chips 110a, 110b, HBM (High Bandwidth Memory) DRAM semiconductor chip.

Although FIG. 1 illustrates four semiconductor chips 110a, 110b, 110c, and 110d in the laminated semiconductor chip structure 110, the present invention is not limited thereto, and two, three, or five or more semiconductor chips may be included. have. When the laminated semiconductor chip structures 110 are all memory semiconductor chips, the laminated semiconductor chip structures 110 may be multiples of two. When at least one of the laminated semiconductor chip structures 110 is a logic semiconductor chip and the remainder is a memory semiconductor chip, the number of memory semiconductor chips included in the laminated semiconductor chip structure 110 may be a multiple of two. The memory semiconductor chips included in the laminated semiconductor chip structure 110 may all be the same type of memory semiconductor chips.

The plurality of semiconductor chips 110a, 110b, 110c, and 110d included in the laminated semiconductor chip structure 110 may include a plurality of through electrodes 112, respectively. The plurality of penetrating electrodes 112 may be formed in the penetrating electrode region. In the through electrode region, for example, several hundred to several thousand through electrodes 112 may be formed. The plurality of penetrating electrodes 112 formed in the penetrating electrode region may be arranged in a matrix array with a pitch of, for example, several tens of 탆. Each of the plurality of penetrating electrodes 112 may have a diameter of several micrometers to several tens of micrometers, for example. The diameter of each of the plurality of penetrating electrodes 112 may have a smaller value than a pitch at which the plurality of penetrating electrodes 112 are arranged. For example, the plurality of penetrating electrodes 112 may have a diameter of 5 占 퐉 to 15 占 퐉 and may be disposed with a pitch of 25 占 퐉 to 50 占 퐉.

The plurality of semiconductor chips 110a, 110b, 110c, and 110d included in the laminated semiconductor chip structure 110 may be electrically connected to each other through the corresponding through electrodes 112. [ The plurality of semiconductor chips 110a, 110b, 110c and 110d included in the laminated semiconductor chip structure 110 may be electrically connected to the package base substrate 121 by a plurality of through electrodes 112. [ The plurality of penetrating electrodes 112 may provide at least one of a signal, a power source, or a ground for the laminated semiconductor chip structure 110.

Pads 111 and 114 may be attached to the upper and lower surfaces of the plurality of semiconductor chips 110a, 110b, 110c, and 110d included in the laminated semiconductor chip structure 110, respectively. The pads 111 and 114 may include a top pad 111 connected to the top surface and a bottom pad 114 connected to the bottom surface. The upper surface pad 111 and the lower surface pad 114 may be formed at positions corresponding to the penetrating electrode 112 and electrically and thermally connected to the penetrating electrode 112. However, And may be electrically connected to the penetrating electrode 112 through the re-wiring layer. The lower pad 114 may be electrically and thermally connected to the upper surface pad 111 of the semiconductor chip immediately below the semiconductor chip to which the lower surface pad 114 is attached. The pads 111 and 114 may have a diameter of, for example, several tens of micrometers. The diameters of the pads 111 and 114 may be larger than the diameter of the penetrating electrode 112 and smaller than the pitch at which the plurality of penetrating electrodes 112 are arranged. Although the pads 111 and 114 are referred to as pads for the sake of explanation, the present invention is not limited thereto. For example, the pads 111 and 114 may have a bump shape. In addition, a connecting member may be provided between the corresponding pads 111 and 114. The connection between the corresponding pads 111 and 114 may be directly connected or may be indirectly connected via a connection member.

The penetrating electrode 112 may be formed of a through silicon via (TSV). The penetrating electrode 112 may include a wiring metal layer (not shown) and a barrier metal layer (not shown) surrounding the wiring metal layer. The wiring metal layer may include Cu or W. For example, the wiring metal layer may be made of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, or W alloy, but is not limited thereto. For example, the wiring metal layer may be formed of a metal such as Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Zr, and may include one or two or more laminated structures. The barrier metal layer may comprise at least one material selected from W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, have. However, the material of the penetrating electrode 112 is not limited to the above materials. The barrier metal layer and the wiring metal layer may be formed by a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process, but the present invention is not limited thereto. A spacer insulating layer (not shown) may be interposed between the penetrating electrode 112 and the semiconductor substrate constituting each of the laminated semiconductor chip structures 110. The spacer insulating layer can prevent the semiconductor element formed on the plurality of semiconductor chips 110a, 110b, 110c, and 110d included in the laminated semiconductor chip structure 110 from contacting the through electrode 112. [ The spacer insulating layer may be formed of an oxide film, a nitride film, a carbonized film, a polymer, or a combination thereof. In some embodiments, a CVD process may be used to form the spacer insulation layer. The spacer insulation layer may be formed of a high aspect ratio process (HARP) oxide film based on O 3 / TEOS (ozone / tetra-ethyl ortho-silicate) formed by a low-pressure CVD (sub-atmospheric CVD) process.

Although the penetrating electrode 112 has been disclosed to directly connect between the plurality of semiconductor chips 110a, 110b, 110c, and 110d included in the laminated semiconductor chip structure 110, the present invention is not limited thereto, and a Via-first ), A via-middle, or a via-last structure.

Also, although the penetrating electrode 112 is shown as being uniformly disposed on the plurality of semiconductor chips 110a, 110b, 110c, and 110d, the technical idea of the present invention is not limited thereto. For example, it can be concentrated on a part of the plurality of semiconductor chips 110a, 110b, 110c, and 110d.

The laminated structure 100 may include a laminated semiconductor chip structure 110, a thermoelectric pattern layer 200, a thermal interface material 300, and a heat emitting member 400. The connection terminal 115 connected to the package base substrate 121 may be attached to the lower surface of the laminated structure 100. The connection terminal 115 may be electrically and thermally connected to the penetrating electrode 112 and the laminated structure 100 may be electrically connected to the lower package base substrate 121.

A thermoelectric pattern layer 200 is formed on the second semiconductor chip 110a.

A thermal interface material (TIM) 300 is formed on the thermoelectric conversion pattern layer 200. The thermal interface material 300 may cover the thermoelectric pattern layer 200. The thermal interface material 300 may be made of an insulating material, or may be made of a material including an insulating material and capable of maintaining electrical insulation. The thermal interface material 300 may comprise, for example, an epoxy resin. The thermal interface material 300 may comprise any suitable material such as, for example, mineral oil, grease, gap filler putty, phase change gel, hase change material pads ) Or a particle filled epoxy.

The heat emitting member 400 may be attached on the thermoelectric conversion pattern layer 200 with the thermal interface material 300 interposed therebetween. The heat emitting member 400 may be, for example, a heat sink, a heat spreader, a heat pipe, or a liquid cooled cold plate.

The semiconductor package 10 includes a package substrate 121 and a plurality of stacked semiconductor chip structures 110 disposed adjacent to each other and a thermoelectric pattern layer 200 formed on the package substrate 121, (400).

The plurality of penetrating electrodes 112 formed on the second semiconductor chip 110a may be connected to the thermoelectric pattern layer 200 through the upper surface pad 111. [ The plurality of penetrating electrodes 112 may be electrically insulated from the heat emitting member 400 by the thermoelectric pattern layer 200 and / or the thermal interface material 300 when the heat emitting member 400 is electrically conductive. The molding layer can be wrapped around the laminated semiconductor chip structure 110. This will be described in detail in Fig.

The thermoelectric pattern layer 200 can effectively dissipate heat inside the laminated semiconductor chip structure 110 to the outside. In addition, the thermoelectric pattern layer 200 can disperse stress that may be concentrated on a part of the semiconductor chip structure 110, thereby preventing distortion of the semiconductor chip structure 110. For this purpose, the thermoelectric pattern layer 200 may be a thermally insulating and insulating material having high thermal conductivity and high electrical resistance. For example, the thermoelectric pattern layer 200 may be any one of diamond, boron nitride, and a graphite-based material having a specific structure to increase electrical resistance.

In addition, heat generated from the laminated semiconductor chip structure 110 can be effectively discharged according to a pattern of the thermoelectric conversion pattern layer 200, or the stress can be effectively dispersed. The pattern may be integrally formed or formed of a plurality of patterns, and details thereof will be described with reference to FIGS. 4A to 11.

2 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure; The description overlapping with the description of FIG. 1 in the description of FIG. 2 may be omitted.

2, a sub-semiconductor package 130 including a third semiconductor chip 131 and a package molding layer 141 surrounding side surfaces of the respective stacked semiconductor chip structures 110 are formed on a package base substrate 121 . The package molding layer 141 may be made of, for example, EMC. The package molding layer 141 may be formed together with the first sub-package molding layer 142. The package molding layer 141 may be formed so as not to cover the upper surface of the sub semiconductor package 130 and the upper surface of the laminated semiconductor chip structure 110. For example, the package molding layer 141 may be formed so as not to cover the upper surface of the third semiconductor chip 131 included in the sub semiconductor package 130 and the upper surface of the thermoelectric pattern layer 200.

The top surface of the third semiconductor chip 131 and the top surface of the thermoelectric pattern layer 200 may have the same level from the package base substrate 121. For example, the third semiconductor chip 131 and the thermoelectric pattern layer 200 are attached to the package base substrate 121 with a relatively large thickness, and the package molding layer 141 is bonded to the third semiconductor chip 131 and the thermoelectric conversion pattern layer 200 and then the upper portion of the package molding layer 141 is removed until the upper surfaces of the third semiconductor chip 131 and the thermoelectric conversion pattern layer 200 are exposed, The upper surface of the third semiconductor chip 131 and the upper surface of the thermoelectric-pattern layer 200 can have the same level from the package base substrate 121. In this case, the upper surface of the third semiconductor chip 131, the upper surface of the thermoelectric-pattern layer 200, and the upper surface of the package molding layer 141 may all have the same level from the package base substrate 121.

The sub semiconductor package 130 may include a sub-package base substrate 151 and a third semiconductor chip 131 attached on the sub-package base substrate 151. The third semiconductor chip 131 may be attached on the sub-package base substrate 151 such that the active surface faces the sub-package base substrate 151. The third semiconductor chip 131 may be electrically connected to the sub-package base board 151 by the first connection terminal 132 disposed on the active surface. The first connection terminal 132 may be, for example, a solder ball or a bump. The sub semiconductor package 130 may further include a first sub-package molding layer 142 formed on the sub-package base substrate 151 so as to surround the side surface of the third semiconductor chip 131. The first sub-package molding layer 142 may not cover the upper surface of the third semiconductor chip 131, that is, the inactive surface. The first sub-package molding layer 142 may be formed to fill a space between the third semiconductor chip 131 and the sub-package base substrate 151. The first sub-package molding layer 142 may be made of, for example, an epoxy mold compound (EMC). The first sub-package molding layer 142 may be formed together with the package molding layer 141 described above.

The sub-package base board 151 may be, for example, a printed circuit board. In the case where the sub-package base board 151 is a printed circuit board, the sub-package base board 151 may include a structure similar to the case where the above-described package base board 121 is a printed circuit board, .

A first internal connection terminal 152 may be attached to the lower surface of the sub-package base board 151. The first internal connection terminal 152 may be, for example, a solder ball or a bump. The first internal connection terminal 152 may electrically connect the sub semiconductor package 130 and the package base substrate 121. A first underfill material layer 153 may be formed to fill a space between the sub semiconductor package 130 and the package base substrate 121. [ The first underfill material layer 153 may be made of, for example, an epoxy resin. The first underfill material 153 may be part of the above-described package molding layer 141 formed, for example, in a MUF (Molded Under-fill) manner.

The semiconductor substrate constituting the third semiconductor chip 131 may include silicon (Si), for example. Or the third semiconductor chip 131 may be a semiconductor element such as germanium or silicon carbide, gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP) And the like. Or the third semiconductor chip 131 may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate constituting the third semiconductor chip 131 may include a BOX layer (buried oxide layer). The semiconductor substrate constituting the third semiconductor chip 131 may include a conductive region, for example, a well doped with an impurity. The semiconductor substrate constituting the third semiconductor chip 131 may have various device isolation structures such as shallow trench isolation (STI) structures.

The third semiconductor chip 131 may be formed of a semiconductor device including a plurality of individual devices of various kinds. The plurality of discrete devices may include a variety of microelectronic devices, such as metal-oxide-semiconductor field effect transistors (MOSFETs) such as complementary metal-insulator-semiconductor transistors, An image sensor such as a CIS (CMOS imaging sensor), a micro-electro-mechanical system (MEMS), an active element, a passive element, and the like. The plurality of individual elements may be electrically connected to the conductive region of the semiconductor substrate constituting the third semiconductor chip 131. The semiconductor device further includes at least two of the plurality of individual elements or a conductive wiring or a conductive plug electrically connecting the plurality of individual elements to the conductive region of the semiconductor substrate constituting the third semiconductor chip 131 . In addition, the plurality of discrete elements may be electrically separated from other discrete elements neighboring each other by an insulating film.

The third semiconductor chip 131 may be a process unit. The third semiconductor chip 131 may be, for example, an MPU (Micro Processor Unit) or a GPU (Graphic Processor Unit). The sub semiconductor package 130 may be, for example, a known good package (KGP) whose normal operation is verified.

2, only one sub-semiconductor package 130 and one stacked semiconductor chip structure 110 included in the semiconductor package 1 are shown, but the stacked semiconductor chip structure 110 and one sub- And the technical idea of the present invention is not limited to this. For example, the semiconductor package 1 may include one or more sub-semiconductor packages 130 and / or a plurality of stacked semiconductor chip structures 110.

The laminated semiconductor chip structure 110 may be thermally connected to the thermal interface material 300 and / or the heat dissipation member 400 via the thermoelectric pattern layer 200. The sub semiconductor package 130 may also be thermally connected to the thermal interface material 300 and / or the heat emitting member 400. 2, the thermoelectric conversion pattern layer 200 is shown only on the laminated semiconductor chip structure 110, but the thermoelectric conversion pattern layer 200 may also be formed on the sub-semiconductor package 130. The technical idea of the present disclosure is not limited to this Do not.

3 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure; The description overlapping with the description of FIG. 1 in the description of FIG. 3 may be omitted.

Referring to FIG. 3, the semiconductor package 10a may include a heat-emitting member 402 having more than one surface. 1, the heat dissipation member 402 may be filled with the thermal interface material 302 and uniformly contacted with the thermoelectric pattern layer 200. In this case, Accordingly, the heat radiation member 402, which is not uniform in more than one side on the thermoelectric pattern layer 200, is raised via the thermal interface material 302 to increase the surface area, so that the heat generation of the semiconductor chip structure 110 can be efficiently It can be dissipated.

4A is a plan view showing a semiconductor package according to an exemplary embodiment of the present disclosure, and FIG. 4B is a cross-sectional view showing a part of a semiconductor package according to an exemplary embodiment of the present disclosure.

Figs. 4A, 5A, 6A, 7A, 8, 9A, 10 and 11 show plan views of the laminated structure 100 as viewed from above. The thermal interface material 300 and the heat emitting member 400 are not shown in order to efficiently explain the technical idea of the present invention.

4A, a laminated structure 100 according to an embodiment of the present disclosure may include a penetrating electrode 112, a top pad 111, a dummy pad 118, and a thermoelectric pattern 200a. The second semiconductor chip 110a may include a first region 21 in which the penetrating electrode 112 is present and a second region 22 in which the penetrating electrode 112 is not present.

The thermoelectric pattern 200a of FIG. 4A is the same as the thermoelectric pattern layer 200 of FIG. 1, and the description thereof is omitted. The thermoelectric pattern 200a may be configured to cover both the upper surface pad 111 and the dummy pad 118 covering the penetrating electrode 112. [ In FIG. 4A, the thermoelectric pattern 200a is shown to be smaller than the second semiconductor chip 110a, but the technical idea of the present disclosure is not limited thereto. In FIG. 4A, the thermoelectric pattern 200a is shown as an angular shape of a quadrangle, but this is for convenience of description, and it should be understood that the technical idea of the present disclosure is not limited thereto.

4B is a cross-sectional view taken along the line a-a 'in FIG. 4A. Referring to FIG. 4B, the thermoelectric pattern 200a may be formed to cover the upper surface pad 111 or the dummy pad 118. Referring to FIG. The upper surface of the dummy pad 118 may have the same level as the upper surface of the upper surface pad 111 and the package base substrate 121.

5A is a plan view showing a semiconductor package according to an exemplary embodiment of the present disclosure, and FIG. 5B is a cross-sectional view showing a portion of a semiconductor package according to an exemplary embodiment of the present disclosure. 5A and 5B show another embodiment of the thermoelectric conversion pattern layer 200 of FIG. 1, so that the overlapping description with FIGS. 1, 4A, and 4B will be omitted.

Referring to FIG. 5A, the thermoelectric pattern layer 200 may include a plurality of first thermoelectric patterns 210b and a plurality of second thermoelectric patterns 220b. The first thermoelectric pattern 210b may be located in the first region 21 where the penetrating electrode 112 is present and may be formed to cover the upper surface pad 111 separately. The second thermoelectric pattern 220b may be located in the second region 22 where the penetrating electrode 112 is not present and may be formed to be spaced apart from each other.

5B is a cross-sectional view taken along line b-b 'in FIG. 5A. Referring to FIG. 5B, the upper surface of the first thermoelectric pattern 210b and the upper surface of the second thermoelectric pattern 220b may have the same level from the package base substrate 121. Accordingly, the first thermoelectric pattern 210b and the second thermoelectric pattern 220b can effectively support the heat emitting member 400.

5A, the first thermoelectric pattern 210b covers the top surface pad 111, but the technical idea of the present disclosure is not limited to this. The top surface of the first thermoelectric pattern 210b may be exposed, And the upper surface of the upper surface pad 111 may have the same level from the package base substrate 121. In FIG. 5A, the first thermoelectric pattern 210b and the second thermoelectric pattern 220b are shown in an angular shape of a quadrangle, but this is for convenience of description, and it should be understood that the technical idea of the present disclosure is not limited thereto.

FIG. 6A is a top view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure, and FIG. 6B is a cross-sectional view illustrating a portion of a semiconductor package according to an exemplary embodiment of the present disclosure. 6A and 6B show another embodiment of the thermoelectric conversion pattern layer 200 of FIG. 1, so that the overlapping description with FIG. 1, FIG. 5A or FIG. 5B will be omitted.

Referring to FIG. 6A, the thermoelectric pattern layer 200 may include a plurality of first thermoelectric patterns 210c and a plurality of second thermoelectric patterns 220c. The first thermoelectric pattern 210c may be located in the first region 21 where the penetrating electrode 112 is present and may be formed to cover the upper surface pad 111 separately. The second thermoelectric pattern 220c may be located in the second region 22 where the penetrating electrode 112 is not present and may be formed to cover the dummy pad 118 separately.

6B is a cross-sectional view taken along line b-b 'in FIG. 6A. Referring to FIG. 6B, the upper surface of the first thermoelectric pattern 210c and the upper surface of the second thermoelectric pattern 220c may have the same level from the package base substrate 121, Can support.

6A, the first thermoelectric pattern 210c covers the upper surface pad 111. However, the technical idea of the present disclosure is not limited to this, and the upper surface of the first thermoelectric pattern 210c may be exposed, And the upper surface of the upper surface pad 111 may have the same level from the package base substrate 121. Although the second thermoelectric pattern 220c is also formed so as to cover the dummy pad 118, the technical idea of the present disclosure is not limited to this, and the dummy pad 118 may be exposed and the upper surface of the second thermoelectric pattern 220c The upper surface of the dummy pad 118 may have the same level from the package base substrate 121. [ In FIG. 6A, the first thermoelectric pattern 210c and the second thermoelectric pattern 220c are shown in an angular shape of a quadrangle, but this is for convenience of description, and it should be understood that the technical idea of the present disclosure is not limited thereto.

FIG. 7A is a plan view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure, and FIG. 7B is a cross-sectional view illustrating a portion of a semiconductor package according to an exemplary embodiment of the present disclosure. 7A and 7B show another embodiment of the thermoelectric conversion pattern layer 200 of FIG. 1, so that the overlapping description with FIG. 1, FIG. 5A or FIG. 5B will be omitted.

Referring to FIG. 7A, the thermoelectric pattern layer 200 may include a plurality of first thermoelectric patterns 210d and a plurality of second thermoelectric patterns 220d spaced from each other. The first thermoelectric pattern 210d may be located in the first region 21 where the penetrating electrode 112 is present and may be formed to cover the upper surface pad 111 separately. The plurality of second thermoelectric patterns 220d may be located in the second region 22 where the penetrating electrode 112 is not present and each of the plurality of dummy pads 118 may integrally cover the plurality of second thermoelectric patterns 220d.

Fig. 7B is a cross-sectional view taken along line b-b 'in Fig. 7A. 7B, the upper surface of the plurality of second thermoelectric patterns 220d and the upper surface of the first thermoelectric pattern 210d may have the same level from the package base substrate 121, Can be effectively supported.

7A, a plurality of second thermoelectric patterns 220d are formed to cover the dummy pad 118. However, the technical idea of the present disclosure is not limited to this, and the dummy pad 118 may be exposed and a plurality of thermoelectric plate patterns 220d And the upper surface of the dummy pad 118 may have the same level from the package base substrate 121. Although a plurality of the second thermoelectric patterns 220d are shown as two, the technical idea of the present disclosure is not limited to this, and it is possible to have three or more second thermoelectric patterns 220d integrally covering the plurality of dummy pads 118 .

In FIG. 7A, a plurality of second thermoelectric patterns 220d are shown in an angular shape of a quadrangle, but this is for convenience of description, and it should be understood that the technical idea of the present disclosure is not limited thereto.

8 is a top view of a semiconductor package according to an exemplary embodiment of the present disclosure; 1, 7A or 7B will be omitted.

Referring to FIG. 8, the thermoelectric pattern layer 200 may include a plurality of first thermoelectric patterns 210d and a second thermoelectric pattern 230d. The first thermoelectric pattern 210d may be located in the first region 21 where the penetrating electrode 112 is present and may be formed to cover the upper surface pad 111 separately. The second thermoelectric pattern 230d may be located in the second region 22 where the penetrating electrode 112 is not present and may be formed to cover all the plurality of dummy pads 118. [

9A is a plan view showing a semiconductor package according to an exemplary embodiment of the present disclosure, and Fig. 9B is a cross-sectional view showing a part of a semiconductor package according to an exemplary embodiment of the present disclosure. 9A and 9B show another embodiment of the thermoelectric conversion pattern layer 200 of FIG. 1, so that the overlapping description with FIG. 1, FIG. 5A or FIG. 5B will be omitted.

9A, the thermoelectric pattern layer 200 may include a plurality of first thermoelectric patterns 210e, a plurality of second thermoelectric patterns 230e, and a plurality of third thermoelectric patterns 250e. In addition, the first region 21 may include a gap region 23 in which the penetrating electrode 112 does not exist. The first thermoelectric pattern 210e may be located in the first region 21 where the penetrating electrode 112 is present and may be formed to cover the upper surface pad 111 separately. The second thermoelectric pattern 230e may cover the upper surface pad 111 and the dummy pad 118 at the same time and may extend from the first area 21 to the second area 22. Although the second thermoelectric pattern 230e extends only in a straight line in Fig. 9A, the technical idea of the present disclosure is not limited to this, and may include all the patterns extending from the first region 21 to the second region 22. [ The third thermoelectric pattern 250e may cover the dummy pad 118 and may be formed to connect the second region 22 through the gap region 23 in which the penetrating electrode 112 is not present.

Referring to FIG. 9B, the second thermoelectric pattern 230e may cover the upper surface pad 111 and the dummy pad 118. Referring to FIG. The upper surface of the second thermoelectric pattern 230e and the upper surface of the upper surface pad 111 and the upper surface of the dummy pad 118 are not exposed to the upper surface 111 and the dummy pad 118, The same level can be obtained from the package base substrate 121.

10 and 11 are plan views illustrating a semiconductor package according to an exemplary embodiment of the present disclosure; 10 and 11 show another embodiment of the thermoelectric conversion pattern layer 200 of FIG. 1, so that the contents overlapping with FIGS. 1, 4A, 5A, or 9A will be omitted.

10, the thermoelectric pattern layer 200 includes a plurality of first thermoelectric patterns 210e, a plurality of second thermoelectric patterns 230e, a plurality of third thermoelectric patterns 250e, (240e). In addition, the first region 21 may include a gap region 23 in which the penetrating electrode 112 does not exist. The fourth thermoelectric pattern 240e may be formed to cover the upper surface pad 111 separately from each other and may extend from the first area 21 to the second area 22. The fourth thermoelectric pattern 240e may be formed in a straight or curved shape.

11, the thermoelectric pattern layer 200 includes a plurality of first thermoelectric patterns 210e, a plurality of second thermoelectric patterns 230e, a plurality of fourth thermoelectric patterns 240e, 260e, and a plurality of sixth thermoelectric patterns 270e. The description of the fourth thermoelectric pattern 240e is omitted because it is the same as that of FIG. The fifth thermoelectric pattern 260e may be formed so as to cover the upper surface pad 111 separately and extend to the gap region 23 where the penetrating electrode 112 is not present. The sixth thermoelectric pattern 260e may cover the upper surface pad 111 and the dummy pad 118 and may penetrate through the gap region 23 where the penetrating electrode 112 is not present in the first region 21, 22).

12 schematically shows a configuration of a semiconductor package according to an exemplary embodiment of the present disclosure;

12, a semiconductor package 1100 includes a micro processing unit 1110, a memory 1120, an interface 1130, a graphics processing unit 1140, functional blocks 1150 and a bus 1160 connecting them. . ≪ / RTI > The semiconductor package 1100 may include both the micro processing unit 1110 and the graphics processing unit 1140, but may include only one of them.

The microprocessing unit 1110 may include a core and an L2 cache. For example, the microprocessing unit 1110 may include a multi-core. Each core of the multi-core may have the same or different performance. In addition, each core of the multi-core may be activated at the same time or may be different from each other. The memory 1120 can store the results processed by the function blocks 1150 under the control of the micro processing unit 1110. [ For example, the microprocessing unit 1110 may be stored in the memory 1120 as the contents stored in the L2 cache of the microprocessor 1110 are flushed. The interface 1130 may perform an interface with external devices. For example, the interface 1130 may interface with a camera, an LCD, a speaker, and the like.

The graphics processing unit 1140 may perform graphics functions. For example, the graphics processing unit 1140 may perform a video codec or process 3D graphics.

The function blocks 1150 can perform various functions. For example, if the semiconductor package 1100 is an AP used in a mobile device, some of the functional blocks 1150 may perform communication functions.

The semiconductor package 1100 may be the semiconductor package 10 illustrated in Figs. The microprocessing unit 1110 and / or the graphics processing unit 1140 may be the semiconductor chips 110a, 110b, 110c, and 110d illustrated in FIGS. The memory 1120 may be a laminated semiconductor chip structure 110 as illustrated in Figs. 1 to 11 or at least one of a plurality of semiconductor chips 110a, 110b, 110c, 110d, and 110e constituting a laminated semiconductor chip structure 110 As shown in FIG.

The interface 1130 and the functional blocks 1150 may correspond to a portion of the first semiconductor chips 110a, 110b, 110c, and 110d illustrated in FIGS.

The semiconductor package 1100 includes a microprocessing unit 1110 and / or a graphics processing unit 1140 and a memory 1120, and the microprocessing unit 1110 and / or the graphics processing unit 1140 Since the semiconductor package 1100 can be quickly discharged to the outside of the semiconductor package 1100, partial heat concentration that may occur in the semiconductor package 1100 can be prevented, have. In addition, it is possible to disperse the stress that can be concentrated on the part, thereby preventing distortion and warping. Therefore, the semiconductor package 1100 can have a high capacity, high performance, and high reliability.

Claims (10)

At least one first semiconductor chip having a plurality of first penetrating electrodes and electrically and physically stacked via the plurality of first penetrating electrodes;
A second semiconductor chip disposed on the at least one first semiconductor chip and including a plurality of second penetrating electrodes electrically connected to the plurality of first penetrating electrodes; And
And an insulating thermoelectric pattern layer in thermal contact with the second penetrating electrodes. The method according to claim 1,
Wherein the thermoelectric pattern layer is integrally formed to cover the upper portions of the plurality of second through electrodes. The method according to claim 1,
Wherein the thermoelectric pattern layer has a plurality of thermoelectric patterns spaced apart from each other so as to cover upper portions of the plurality of second penetrating electrodes. The method according to claim 1,
Wherein the second semiconductor chip comprises a first region in which the plurality of second penetrating electrodes are present and a second region in which the plurality of second penetrating electrodes are not present,
Wherein the thermoelectric pattern layer has a plurality of first thermoelectric patterns covering the upper portion of the plurality of second penetrating electrodes and a second thermoelectric pattern spaced apart from the first thermoelectric pattern and covering the upper portion of the second region . 5. The method of claim 4,
Wherein the first thermoelectric pattern and the second thermoelectric pattern have top surfaces of the same level. 5. The method of claim 4,
Wherein a plurality of dummy pads are located on the second region,
Wherein the second thermoelectric pattern covers the plurality of dummy pads. The method according to claim 1,
Wherein the second semiconductor chip comprises a first region in which the plurality of second penetrating electrodes are present and a second region in which the plurality of second penetrating electrodes are not present,
Wherein the thermoelectric pattern layer includes a plurality of first thermoelectric patterns each covering an upper portion of the plurality of second penetrating electrodes,
Wherein at least some of the plurality of first thermoelectric patterns extend from the first region to the second region. The method according to claim 1,
Wherein the thermoelectric pattern layer is formed of any one of diamond, boron nitride, and graphite. A package base substrate;
At least one first semiconductor chip having a plurality of first penetrating electrodes electrically and physically stacked via the plurality of first penetrating electrodes, a second semiconductor chip disposed on the first semiconductor chip, A second semiconductor chip including a plurality of second through electrodes electrically connected to the electrodes, and a thermoelectric pattern layer in thermal contact with the second through electrodes; And
And a heat radiation member disposed on the thermoelectric conversion layer and in thermal contact with the thermoelectric conversion layer. 10. The method of claim 9,
And a thermal interface material positioned between the heat emitting member and the sub semiconductor package.

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